1 /* 2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <arch.h> 9 #include <arch_helpers.h> 10 #include <common/bl_common.h> 11 #include <common/debug.h> 12 #include <drivers/console.h> 13 #include <drivers/delay_timer.h> 14 #include <drivers/arm/gic_common.h> 15 #include <drivers/arm/gicv2.h> 16 #include <drivers/ti/uart/uart_16550.h> 17 #include <drivers/generic_delay_timer.h> 18 #include <drivers/arm/gicv2.h> 19 #include <s10_mailbox.h> 20 #include <lib/xlat_tables/xlat_tables.h> 21 #include <lib/mmio.h> 22 #include <plat/common/platform.h> 23 #include <platform_def.h> 24 25 #include "socfpga_private.h" 26 #include "s10_reset_manager.h" 27 #include "s10_memory_controller.h" 28 #include "s10_pinmux.h" 29 #include "s10_clock_manager.h" 30 #include "s10_system_manager.h" 31 32 static entry_point_info_t bl32_image_ep_info; 33 static entry_point_info_t bl33_image_ep_info; 34 35 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 36 { 37 entry_point_info_t *next_image_info; 38 39 next_image_info = (type == NON_SECURE) ? 40 &bl33_image_ep_info : &bl32_image_ep_info; 41 42 /* None of the images on this platform can have 0x0 as the entrypoint */ 43 if (next_image_info->pc) 44 return next_image_info; 45 else 46 return NULL; 47 } 48 49 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 50 u_register_t arg2, u_register_t arg3) 51 { 52 static console_16550_t console; 53 54 console_16550_register(PLAT_UART0_BASE, PLAT_UART_CLOCK, PLAT_BAUDRATE, 55 &console); 56 /* 57 * Check params passed from BL31 should not be NULL, 58 */ 59 void *from_bl2 = (void *) arg0; 60 61 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; 62 63 assert(params_from_bl2 != NULL); 64 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); 65 assert(params_from_bl2->h.version >= VERSION_2); 66 67 /* 68 * Copy BL32 (if populated by BL31) and BL33 entry point information. 69 * They are stored in Secure RAM, in BL31's address space. 70 */ 71 72 bl_params_node_t *bl_params = params_from_bl2->head; 73 74 while (bl_params) { 75 if (bl_params->image_id == BL33_IMAGE_ID) 76 bl33_image_ep_info = *bl_params->ep_info; 77 78 bl_params = bl_params->next_params_info; 79 } 80 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 81 } 82 83 static const interrupt_prop_t s10_interrupt_props[] = { 84 PLAT_INTEL_SOCFPGA_G1S_IRQ_PROPS(GICV2_INTR_GROUP0), 85 PLAT_INTEL_SOCFPGA_G0_IRQ_PROPS(GICV2_INTR_GROUP0) 86 }; 87 88 static unsigned int target_mask_array[PLATFORM_CORE_COUNT]; 89 90 static const gicv2_driver_data_t plat_gicv2_gic_data = { 91 .gicd_base = PLAT_INTEL_SOCFPGA_GICD_BASE, 92 .gicc_base = PLAT_INTEL_SOCFPGA_GICC_BASE, 93 .interrupt_props = s10_interrupt_props, 94 .interrupt_props_num = ARRAY_SIZE(s10_interrupt_props), 95 .target_masks = target_mask_array, 96 .target_masks_num = ARRAY_SIZE(target_mask_array), 97 }; 98 99 /******************************************************************************* 100 * Perform any BL3-1 platform setup code 101 ******************************************************************************/ 102 void bl31_platform_setup(void) 103 { 104 /* Initialize the gic cpu and distributor interfaces */ 105 gicv2_driver_init(&plat_gicv2_gic_data); 106 gicv2_distif_init(); 107 gicv2_pcpu_distif_init(); 108 gicv2_cpuif_enable(); 109 } 110 111 const mmap_region_t plat_stratix10_mmap[] = { 112 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE, 113 MT_MEMORY | MT_RW | MT_NS), 114 MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, 115 MT_DEVICE | MT_RW | MT_NS), 116 MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE, 117 MT_DEVICE | MT_RW | MT_SECURE), 118 MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE, 119 MT_NON_CACHEABLE | MT_RW | MT_SECURE), 120 MAP_REGION_FLAT(DEVICE3_BASE, DEVICE3_SIZE, 121 MT_DEVICE | MT_RW | MT_SECURE), 122 MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE, 123 MT_DEVICE | MT_RW | MT_NS), 124 MAP_REGION_FLAT(DEVICE4_BASE, DEVICE4_SIZE, 125 MT_DEVICE | MT_RW | MT_NS), 126 {0} 127 }; 128 129 /******************************************************************************* 130 * Perform the very early platform specific architectural setup here. At the 131 * moment this is only intializes the mmu in a quick and dirty way. 132 ******************************************************************************/ 133 void bl31_plat_arch_setup(void) 134 { 135 const mmap_region_t bl_regions[] = { 136 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE, 137 MT_MEMORY | MT_RW | MT_SECURE), 138 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, 139 MT_CODE | MT_SECURE), 140 MAP_REGION_FLAT(BL_RO_DATA_BASE, 141 BL_RO_DATA_END - BL_RO_DATA_BASE, 142 MT_RO_DATA | MT_SECURE), 143 #if USE_COHERENT_MEM 144 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, 145 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, 146 MT_DEVICE | MT_RW | MT_SECURE), 147 #endif 148 {0} 149 }; 150 151 setup_page_tables(bl_regions, plat_stratix10_mmap); 152 enable_mmu_el3(0); 153 } 154 155