1 /* 2 * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __TEGRA_DEF_H__ 8 #define __TEGRA_DEF_H__ 9 10 #include <lib/utils_def.h> 11 12 /******************************************************************************* 13 * These values are used by the PSCI implementation during the `CPU_SUSPEND` 14 * and `SYSTEM_SUSPEND` calls as the `state-id` field in the 'power state' 15 * parameter. 16 ******************************************************************************/ 17 #define PSTATE_ID_CORE_IDLE 6 18 #define PSTATE_ID_CORE_POWERDN 7 19 #define PSTATE_ID_SOC_POWERDN 2 20 21 /******************************************************************************* 22 * Platform power states (used by PSCI framework) 23 * 24 * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID 25 * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID 26 ******************************************************************************/ 27 #define PLAT_MAX_RET_STATE 1 28 #define PLAT_MAX_OFF_STATE 8 29 30 /******************************************************************************* 31 * Secure IRQ definitions 32 ******************************************************************************/ 33 #define TEGRA186_MAX_SEC_IRQS 5 34 #define TEGRA186_BPMP_WDT_IRQ 46 35 #define TEGRA186_SPE_WDT_IRQ 47 36 #define TEGRA186_SCE_WDT_IRQ 48 37 #define TEGRA186_TOP_WDT_IRQ 49 38 #define TEGRA186_AON_WDT_IRQ 50 39 40 #define TEGRA186_SEC_IRQ_TARGET_MASK 0xFF /* 8 Carmel */ 41 42 /******************************************************************************* 43 * Tegra Miscellanous register constants 44 ******************************************************************************/ 45 #define TEGRA_MISC_BASE 0x00100000 46 #define HARDWARE_REVISION_OFFSET 0x4 47 48 #define MISCREG_PFCFG 0x200C 49 50 /******************************************************************************* 51 * Tegra TSA Controller constants 52 ******************************************************************************/ 53 #define TEGRA_TSA_BASE 0x02000000 54 55 #define TSA_CONFIG_STATIC0_CSW_SESWR 0x1010 56 #define TSA_CONFIG_STATIC0_CSW_SESWR_RESET 0x1100 57 #define TSA_CONFIG_STATIC0_CSW_ETRW 0xD034 58 #define TSA_CONFIG_STATIC0_CSW_ETRW_RESET 0x1100 59 #define TSA_CONFIG_STATIC0_CSW_SDMMCWAB 0x3020 60 #define TSA_CONFIG_STATIC0_CSW_SDMMCWAB_RESET 0x1100 61 #define TSA_CONFIG_STATIC0_CSW_AXISW 0x8008 62 #define TSA_CONFIG_STATIC0_CSW_AXISW_RESET 0x1100 63 #define TSA_CONFIG_STATIC0_CSW_HDAW 0xD008 64 #define TSA_CONFIG_STATIC0_CSW_HDAW_RESET 0x1100 65 #define TSA_CONFIG_STATIC0_CSW_AONDMAW 0xE018 66 #define TSA_CONFIG_STATIC0_CSW_AONDMAW_RESET 0x1100 67 #define TSA_CONFIG_STATIC0_CSW_SCEDMAW 0x9008 68 #define TSA_CONFIG_STATIC0_CSW_SCEDMAW_RESET 0x1100 69 #define TSA_CONFIG_STATIC0_CSW_BPMPDMAW 0x9028 70 #define TSA_CONFIG_STATIC0_CSW_BPMPDMAW_RESET 0x1100 71 #define TSA_CONFIG_STATIC0_CSW_APEDMAW 0xB008 72 #define TSA_CONFIG_STATIC0_CSW_APEDMAW_RESET 0x1100 73 #define TSA_CONFIG_STATIC0_CSW_UFSHCW 0x6008 74 #define TSA_CONFIG_STATIC0_CSW_UFSHCW_RESET 0x1100 75 #define TSA_CONFIG_STATIC0_CSW_AFIW 0xF008 76 #define TSA_CONFIG_STATIC0_CSW_AFIW_RESET 0x1100 77 #define TSA_CONFIG_STATIC0_CSW_SATAW 0x4008 78 #define TSA_CONFIG_STATIC0_CSW_SATAW_RESET 0x1100 79 #define TSA_CONFIG_STATIC0_CSW_EQOSW 0x3038 80 #define TSA_CONFIG_STATIC0_CSW_EQOSW_RESET 0x1100 81 #define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW 0x6018 82 #define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW_RESET 0x1100 83 #define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW 0x6028 84 #define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW_RESET 0x1100 85 86 #define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK (0x3 << 11) 87 #define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU (0 << 11) 88 89 /******************************************************************************* 90 * Tegra Memory Controller constants 91 ******************************************************************************/ 92 #define TEGRA_MC_STREAMID_BASE 0x02C00000 93 #define TEGRA_MC_BASE 0x02C10000 94 95 /* General Security Carveout register macros */ 96 #define MC_GSC_CONFIG_REGS_SIZE 0x40 97 #define MC_GSC_LOCK_CFG_SETTINGS_BIT (1 << 1) 98 #define MC_GSC_ENABLE_TZ_LOCK_BIT (1 << 0) 99 #define MC_GSC_SIZE_RANGE_4KB_SHIFT 27 100 #define MC_GSC_BASE_LO_SHIFT 12 101 #define MC_GSC_BASE_LO_MASK 0xFFFFF 102 #define MC_GSC_BASE_HI_SHIFT 0 103 #define MC_GSC_BASE_HI_MASK 3 104 105 /* TZDRAM carveout configuration registers */ 106 #define MC_SECURITY_CFG0_0 0x70 107 #define MC_SECURITY_CFG1_0 0x74 108 #define MC_SECURITY_CFG3_0 0x9BC 109 110 /* Video Memory carveout configuration registers */ 111 #define MC_VIDEO_PROTECT_BASE_HI 0x978 112 #define MC_VIDEO_PROTECT_BASE_LO 0x648 113 #define MC_VIDEO_PROTECT_SIZE_MB 0x64c 114 115 /* 116 * Carveout (MC_SECURITY_CARVEOUT24) registers used to clear the 117 * non-overlapping Video memory region 118 */ 119 #define MC_VIDEO_PROTECT_CLEAR_CFG 0x25A0 120 #define MC_VIDEO_PROTECT_CLEAR_BASE_LO 0x25A4 121 #define MC_VIDEO_PROTECT_CLEAR_BASE_HI 0x25A8 122 #define MC_VIDEO_PROTECT_CLEAR_SIZE 0x25AC 123 #define MC_VIDEO_PROTECT_CLEAR_ACCESS_CFG0 0x25B0 124 125 /* TZRAM carveout (MC_SECURITY_CARVEOUT11) configuration registers */ 126 #define MC_TZRAM_CARVEOUT_CFG 0x2190 127 #define MC_TZRAM_BASE_LO 0x2194 128 #define MC_TZRAM_BASE_HI 0x2198 129 #define MC_TZRAM_SIZE 0x219C 130 #define MC_TZRAM_CLIENT_ACCESS_CFG0 0x21A0 131 132 /* Memory Controller Reset Control registers */ 133 #define MC_CLIENT_HOTRESET_CTRL1_VIFAL_FLUSH_ENB (1 << 27) 134 #define MC_CLIENT_HOTRESET_CTRL1_DLAA_FLUSH_ENB (1 << 28) 135 #define MC_CLIENT_HOTRESET_CTRL1_DLA1A_FLUSH_ENB (1 << 29) 136 #define MC_CLIENT_HOTRESET_CTRL1_PVA0A_FLUSH_ENB (1 << 30) 137 #define MC_CLIENT_HOTRESET_CTRL1_PVA1A_FLUSH_ENB (1 << 31) 138 139 /******************************************************************************* 140 * Tegra UART Controller constants 141 ******************************************************************************/ 142 #define TEGRA_UARTA_BASE 0x03100000 143 #define TEGRA_UARTB_BASE 0x03110000 144 #define TEGRA_UARTC_BASE 0x0C280000 145 #define TEGRA_UARTD_BASE 0x03130000 146 #define TEGRA_UARTE_BASE 0x03140000 147 #define TEGRA_UARTF_BASE 0x03150000 148 #define TEGRA_UARTG_BASE 0x0C290000 149 150 /******************************************************************************* 151 * Tegra Fuse Controller related constants 152 ******************************************************************************/ 153 #define TEGRA_FUSE_BASE 0x03820000 154 #define OPT_SUBREVISION 0x248 155 #define SUBREVISION_MASK 0xF 156 157 /******************************************************************************* 158 * GICv2 & interrupt handling related constants 159 ******************************************************************************/ 160 #define TEGRA_GICD_BASE 0x03881000 161 #define TEGRA_GICC_BASE 0x03882000 162 163 /******************************************************************************* 164 * Security Engine related constants 165 ******************************************************************************/ 166 #define TEGRA_SE0_BASE 0x03AC0000 167 #define SE_MUTEX_WATCHDOG_NS_LIMIT 0x6C 168 #define TEGRA_PKA1_BASE 0x03AD0000 169 #define PKA_MUTEX_WATCHDOG_NS_LIMIT 0x8144 170 #define TEGRA_RNG1_BASE 0x03AE0000 171 #define RNG_MUTEX_WATCHDOG_NS_LIMIT 0xFE0 172 173 /******************************************************************************* 174 * Tegra micro-seconds timer constants 175 ******************************************************************************/ 176 #define TEGRA_TMRUS_BASE 0x0C2E0000 177 #define TEGRA_TMRUS_SIZE 0x10000 178 179 /******************************************************************************* 180 * Tegra Power Mgmt Controller constants 181 ******************************************************************************/ 182 #define TEGRA_PMC_BASE 0x0C360000 183 184 /******************************************************************************* 185 * Tegra scratch registers constants 186 ******************************************************************************/ 187 #define TEGRA_SCRATCH_BASE 0x0C390000 188 #define SECURE_SCRATCH_RSV1_LO 0x06C 189 #define SECURE_SCRATCH_RSV1_HI 0x070 190 #define SECURE_SCRATCH_RSV6 0x094 191 #define SECURE_SCRATCH_RSV11_LO 0x0BC 192 #define SECURE_SCRATCH_RSV11_HI 0x0C0 193 #define SECURE_SCRATCH_RSV53_LO 0x20C 194 #define SECURE_SCRATCH_RSV53_HI 0x210 195 #define SECURE_SCRATCH_RSV54_HI 0x218 196 #define SECURE_SCRATCH_RSV55_LO 0x21C 197 #define SECURE_SCRATCH_RSV55_HI 0x220 198 199 /******************************************************************************* 200 * Tegra Memory Mapped Control Register Access Bus constants 201 ******************************************************************************/ 202 #define TEGRA_MMCRAB_BASE 0x0E000000 203 204 /******************************************************************************* 205 * Tegra SMMU Controller constants 206 ******************************************************************************/ 207 #define TEGRA_SMMU0_BASE 0x12000000 208 #define TEGRA_SMMU1_BASE 0x11000000 209 #define TEGRA_SMMU2_BASE 0x10000000 210 211 /******************************************************************************* 212 * Tegra TZRAM constants 213 ******************************************************************************/ 214 #define TEGRA_TZRAM_BASE 0x40000000 215 #define TEGRA_TZRAM_SIZE 0x40000 216 217 /******************************************************************************* 218 * Tegra Clock and Reset Controller constants 219 ******************************************************************************/ 220 #define TEGRA_CAR_RESET_BASE 0x200000000 221 #define TEGRA_GPU_RESET_REG_OFFSET 0x18UL 222 #define GPU_RESET_BIT (1UL << 0) 223 224 /******************************************************************************* 225 * Stream ID Override Config registers 226 ******************************************************************************/ 227 #define MC_STREAMID_OVERRIDE_CFG_ISPFALR 0x228U 228 #define MC_STREAMID_OVERRIDE_CFG_AXIAPR 0x410U 229 #define MC_STREAMID_OVERRIDE_CFG_AXIAPW 0x418U 230 #define MC_STREAMID_OVERRIDE_CFG_MIU0R 0x530U 231 #define MC_STREAMID_OVERRIDE_CFG_MIU0W 0x538U 232 #define MC_STREAMID_OVERRIDE_CFG_MIU1R 0x540U 233 #define MC_STREAMID_OVERRIDE_CFG_MIU1W 0x548U 234 #define MC_STREAMID_OVERRIDE_CFG_MIU2R 0x570U 235 #define MC_STREAMID_OVERRIDE_CFG_MIU2W 0x578U 236 #define MC_STREAMID_OVERRIDE_CFG_MIU3R 0x580U 237 #define MC_STREAMID_OVERRIDE_CFG_MIU3W 0x588U 238 #define MC_STREAMID_OVERRIDE_CFG_VIFALR 0x5E0U 239 #define MC_STREAMID_OVERRIDE_CFG_VIFALW 0x5E8U 240 #define MC_STREAMID_OVERRIDE_CFG_DLA0RDA 0x5F0U 241 #define MC_STREAMID_OVERRIDE_CFG_DLA0FALRDB 0x5F8U 242 #define MC_STREAMID_OVERRIDE_CFG_DLA0WRA 0x600U 243 #define MC_STREAMID_OVERRIDE_CFG_DLA0FALWRB 0x608U 244 #define MC_STREAMID_OVERRIDE_CFG_DLA1RDA 0x610U 245 #define MC_STREAMID_OVERRIDE_CFG_DLA1FALRDB 0x618U 246 #define MC_STREAMID_OVERRIDE_CFG_DLA1WRA 0x620U 247 #define MC_STREAMID_OVERRIDE_CFG_DLA1FALWRB 0x628U 248 #define MC_STREAMID_OVERRIDE_CFG_PVA0RDA 0x630U 249 #define MC_STREAMID_OVERRIDE_CFG_PVA0RDB 0x638U 250 #define MC_STREAMID_OVERRIDE_CFG_PVA0RDC 0x640U 251 #define MC_STREAMID_OVERRIDE_CFG_PVA0WRA 0x648U 252 #define MC_STREAMID_OVERRIDE_CFG_PVA0WRB 0x650U 253 #define MC_STREAMID_OVERRIDE_CFG_PVA0WRC 0x658U 254 #define MC_STREAMID_OVERRIDE_CFG_PVA1RDA 0x660U 255 #define MC_STREAMID_OVERRIDE_CFG_PVA1RDB 0x668U 256 #define MC_STREAMID_OVERRIDE_CFG_PVA1RDC 0x670U 257 #define MC_STREAMID_OVERRIDE_CFG_PVA1WRA 0x678U 258 #define MC_STREAMID_OVERRIDE_CFG_PVA1WRB 0x680U 259 #define MC_STREAMID_OVERRIDE_CFG_PVA1WRC 0x688U 260 #define MC_STREAMID_OVERRIDE_CFG_RCER 0x690U 261 #define MC_STREAMID_OVERRIDE_CFG_RCEW 0x698U 262 #define MC_STREAMID_OVERRIDE_CFG_RCEDMAR 0x6A0U 263 #define MC_STREAMID_OVERRIDE_CFG_RCEDMAW 0x6A8U 264 #define MC_STREAMID_OVERRIDE_CFG_NVENC1SRD 0x6B0U 265 #define MC_STREAMID_OVERRIDE_CFG_NVENC1SWR 0x6B8U 266 #define MC_STREAMID_OVERRIDE_CFG_PCIE0R 0x6C0U 267 #define MC_STREAMID_OVERRIDE_CFG_PCIE0W 0x6C8U 268 #define MC_STREAMID_OVERRIDE_CFG_PCIE1R 0x6D0U 269 #define MC_STREAMID_OVERRIDE_CFG_PCIE1W 0x6D8U 270 #define MC_STREAMID_OVERRIDE_CFG_PCIE2AR 0x6E0U 271 #define MC_STREAMID_OVERRIDE_CFG_PCIE2AW 0x6E8U 272 #define MC_STREAMID_OVERRIDE_CFG_PCIE3R 0x6F0U 273 #define MC_STREAMID_OVERRIDE_CFG_PCIE3W 0x6F8U 274 #define MC_STREAMID_OVERRIDE_CFG_PCIE4R 0x700U 275 #define MC_STREAMID_OVERRIDE_CFG_PCIE4W 0x708U 276 #define MC_STREAMID_OVERRIDE_CFG_PCIE5R 0x710U 277 #define MC_STREAMID_OVERRIDE_CFG_PCIE5W 0x718U 278 #define MC_STREAMID_OVERRIDE_CFG_ISPFALW 0x720U 279 #define MC_STREAMID_OVERRIDE_CFG_DLA0RDA1 0x748U 280 #define MC_STREAMID_OVERRIDE_CFG_DLA1RDA1 0x750U 281 #define MC_STREAMID_OVERRIDE_CFG_PVA0RDA1 0x758U 282 #define MC_STREAMID_OVERRIDE_CFG_PVA0RDB1 0x760U 283 #define MC_STREAMID_OVERRIDE_CFG_PVA1RDA1 0x768U 284 #define MC_STREAMID_OVERRIDE_CFG_PVA1RDB1 0x770U 285 #define MC_STREAMID_OVERRIDE_CFG_PCIE5R1 0x778U 286 #define MC_STREAMID_OVERRIDE_CFG_NVENCSRD1 0x780U 287 #define MC_STREAMID_OVERRIDE_CFG_NVENC1SRD1 0x788U 288 #define MC_STREAMID_OVERRIDE_CFG_ISPRA1 0x790U 289 #define MC_STREAMID_OVERRIDE_CFG_PCIE0R1 0x798U 290 #define MC_STREAMID_OVERRIDE_CFG_NVDEC1SRD 0x7C8U 291 #define MC_STREAMID_OVERRIDE_CFG_NVDEC1SRD1 0x7D0U 292 #define MC_STREAMID_OVERRIDE_CFG_NVDEC1SWR 0x7D8U 293 294 /******************************************************************************* 295 * Memory Controller transaction override config registers 296 ******************************************************************************/ 297 #define MC_TXN_OVERRIDE_CONFIG_MIU0R 0x1530 298 #define MC_TXN_OVERRIDE_CONFIG_MIU0W 0x1538 299 #define MC_TXN_OVERRIDE_CONFIG_MIU1R 0x1540 300 #define MC_TXN_OVERRIDE_CONFIG_MIU1W 0x1548 301 #define MC_TXN_OVERRIDE_CONFIG_MIU2R 0x1570 302 #define MC_TXN_OVERRIDE_CONFIG_MIU2W 0x1578 303 #define MC_TXN_OVERRIDE_CONFIG_MIU3R 0x1580 304 #define MC_TXN_OVERRIDE_CONFIG_MIU3W 0x158C 305 #define MC_TXN_OVERRIDE_CONFIG_VIFALR 0x15E4 306 #define MC_TXN_OVERRIDE_CONFIG_VIFALW 0x15EC 307 #define MC_TXN_OVERRIDE_CONFIG_DLA0RDA 0x15F4 308 #define MC_TXN_OVERRIDE_CONFIG_DLA0FALRDB 0x15FC 309 #define MC_TXN_OVERRIDE_CONFIG_DLA0WRA 0x1604 310 #define MC_TXN_OVERRIDE_CONFIG_DLA0FALWRB 0x160C 311 #define MC_TXN_OVERRIDE_CONFIG_DLA1RDA 0x1614 312 #define MC_TXN_OVERRIDE_CONFIG_DLA1FALRDB 0x161C 313 #define MC_TXN_OVERRIDE_CONFIG_DLA1WRA 0x1624 314 #define MC_TXN_OVERRIDE_CONFIG_DLA1FALWRB 0x162C 315 #define MC_TXN_OVERRIDE_CONFIG_PVA0RDA 0x1634 316 #define MC_TXN_OVERRIDE_CONFIG_PVA0RDB 0x163C 317 #define MC_TXN_OVERRIDE_CONFIG_PVA0RDC 0x1644 318 #define MC_TXN_OVERRIDE_CONFIG_PVA0WRA 0x164C 319 #define MC_TXN_OVERRIDE_CONFIG_PVA0WRB 0x1654 320 #define MC_TXN_OVERRIDE_CONFIG_PVA0WRC 0x165C 321 #define MC_TXN_OVERRIDE_CONFIG_PVA1RDA 0x1664 322 #define MC_TXN_OVERRIDE_CONFIG_PVA1RDB 0x166C 323 #define MC_TXN_OVERRIDE_CONFIG_PVA1RDC 0x1674 324 #define MC_TXN_OVERRIDE_CONFIG_PVA1WRA 0x167C 325 #define MC_TXN_OVERRIDE_CONFIG_PVA1WRB 0x1684 326 #define MC_TXN_OVERRIDE_CONFIG_PVA1WRC 0x168C 327 #define MC_TXN_OVERRIDE_CONFIG_RCER 0x1694 328 #define MC_TXN_OVERRIDE_CONFIG_RCEW 0x169C 329 #define MC_TXN_OVERRIDE_CONFIG_RCEDMAR 0x16A4 330 #define MC_TXN_OVERRIDE_CONFIG_RCEDMAW 0x16AC 331 #define MC_TXN_OVERRIDE_CONFIG_NVENC1SRD 0x16B4 332 #define MC_TXN_OVERRIDE_CONFIG_NVENC1SWR 0x16BC 333 #define MC_TXN_OVERRIDE_CONFIG_PCIE0R 0x16C4 334 #define MC_TXN_OVERRIDE_CONFIG_PCIE0W 0x16CC 335 #define MC_TXN_OVERRIDE_CONFIG_PCIE1R 0x16D4 336 #define MC_TXN_OVERRIDE_CONFIG_PCIE1W 0x16DC 337 #define MC_TXN_OVERRIDE_CONFIG_PCIE2AR 0x16E4 338 #define MC_TXN_OVERRIDE_CONFIG_PCIE2AW 0x16EC 339 #define MC_TXN_OVERRIDE_CONFIG_PCIE3R 0x16F4 340 #define MC_TXN_OVERRIDE_CONFIG_PCIE3W 0x16FC 341 #define MC_TXN_OVERRIDE_CONFIG_PCIE4R 0x1704 342 #define MC_TXN_OVERRIDE_CONFIG_PCIE4W 0x170C 343 #define MC_TXN_OVERRIDE_CONFIG_PCIE5R 0x1714 344 #define MC_TXN_OVERRIDE_CONFIG_PCIE5W 0x171C 345 #define MC_TXN_OVERRIDE_CONFIG_ISPFALW 0x1724 346 #define MC_TXN_OVERRIDE_CONFIG_DLA0RDA1 0x174C 347 #define MC_TXN_OVERRIDE_CONFIG_DLA1RDA1 0x1754 348 #define MC_TXN_OVERRIDE_CONFIG_PVA0RDA1 0x175C 349 #define MC_TXN_OVERRIDE_CONFIG_PVA0RDB1 0x1764 350 #define MC_TXN_OVERRIDE_CONFIG_PVA1RDA1 0x176C 351 #define MC_TXN_OVERRIDE_CONFIG_PVA1RDB1 0x1774 352 #define MC_TXN_OVERRIDE_CONFIG_PCIE5R1 0x177C 353 #define MC_TXN_OVERRIDE_CONFIG_NVENCSRD1 0x1784 354 #define MC_TXN_OVERRIDE_CONFIG_NVENC1SRD1 0x178C 355 #define MC_TXN_OVERRIDE_CONFIG_ISPRA1 0x1794 356 #define MC_TXN_OVERRIDE_CONFIG_PCIE0R1 0x179C 357 #define MC_TXN_OVERRIDE_CONFIG_NVDEC1SRD 0x17CC 358 #define MC_TXN_OVERRIDE_CONFIG_NVDEC1SRD1 0x17D4 359 #define MC_TXN_OVERRIDE_CONFIG_NVDEC1SWR 0x17DC 360 361 #endif /* __TEGRA_DEF_H__ */ 362