Merge pull request #1304 from antonio-nino-diaz-arm/an/fix-copyright

tegra: Use SPDX license identifier

Rename 'smcc' to 'smccc'

When the source code says 'SMCC' it is talking about the SMC Calling
Convention. The correct acronym is SMCCC. This affects a few definitions
and file names.

Some files hav

Rename 'smcc' to 'smccc'

When the source code says 'SMCC' it is talking about the SMC Calling
Convention. The correct acronym is SMCCC. This affects a few definitions
and file names.

Some files have been renamed (smcc.h, smcc_helpers.h and smcc_macros.S)
but the old files have been kept for compatibility, they include the
new ones with an ERROR_DEPRECATED guard.

Change-Id: I78f94052a502436fdd97ca32c0fe86bd58173f2f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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qemu: Add support for stack canary protection

Allow qemu users to enable stack protection. Since the virt platform
does not provide an RNG, use a basic, timer-based, canary generation,
similarly to

qemu: Add support for stack canary protection

Allow qemu users to enable stack protection. Since the virt platform
does not provide an RNG, use a basic, timer-based, canary generation,
similarly to FVP.

Increase SRAM size and BL2 size to fit images when stack protection is
enabled.

Notice that stack protection is not enabled by default in qemu.

Fixes ARM-software/tf-issues#568

Signed-off-by: Michalis Pappas <mpappas@fastmail.fm>

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rockchip/rk3399: save/restore watchdog register correctly

there are two fix for save/restore watchdog register:
1. watchdog plck will shutdown after secure_watchdog_disable(), so need
to save reg

rockchip/rk3399: save/restore watchdog register correctly

there are two fix for save/restore watchdog register:
1. watchdog plck will shutdown after secure_watchdog_disable(), so need
to save register before it and restore after secure_watchdog_enable().
2. need write 0x76 to cnt_restart to keep watchdog alive when restore
watchdog register.

Change-Id: I1f6fbceae22186e3b72a87df6332a110adf37479
Signed-off-by: Lin Huang <hl@rock-chips.com>

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FVP: change the method for translating MPIDR values to a linear indices

x3 will be assigned by the folloing instructions.
So the first instruction is not needed any more.

old method:
(ClusterId *

FVP: change the method for translating MPIDR values to a linear indices

x3 will be assigned by the folloing instructions.
So the first instruction is not needed any more.

old method:
(ClusterId * FVP_MAX_CPUS_PER_CLUSTER)
+ (CPUId * FVP_MAX_PE_PER_CPU)
+ ThreadId

it should be
(ClusterId * FVP_MAX_CPUS_PER_CLUSTER) * FVP_MAX_PE_PER_CPU
+ (CPUId * FVP_MAX_PE_PER_CPU)
+ ThreadId

which can be simplified as:
(ClusterId * FVP_MAX_CPUS_PER_CLUSTER + CPUId) * FVP_MAX_PE_PER_CPU + ThreadId

Signed-off-by: Wang Feng <feng_feng.wang@spreadtrum.com>

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zynqmp: pm: Minor corrections for MISRA compliance

Various changes to comply with MISRA static analysis rules

Signed-off-by: Jolly Shah <jollys@xilinx.com>

zynqmp: pm_service: Support multiple SDIO modes

Existing database allows to set only single mode for SDIO.
SDIO can have different groups (8 bit, 4 bit and 1 bit).
As there is only single SDIO group

zynqmp: pm_service: Support multiple SDIO modes

Existing database allows to set only single mode for SDIO.
SDIO can have different groups (8 bit, 4 bit and 1 bit).
As there is only single SDIO group in each pin, it is not
possible to use different mode groups for SDIO.

Extend database in generic way to allow multiuple function
groups in single pin. Add different SDIO groups to pins and
create separate functions for each modes.

Signed-off-by: Rajan Vaja <rajanv@xilinx.com>

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zynqmp: pm: Support ATF PM version check

Add SMC call to query ATF PM version. This version
can be used by Linux to match with expected version.

Signed-off-by: Rajan Vaja <rajanv@xilinx.com>

zynqmp: pm: Update API version to 1.0

With new EEMI APIs addition, version is updated to 1.0

Signed-off-by: Jolly Shah <jollys@xilinx.com>

zynqmp: Use DDR memory when DEBUG is enabled

Define default DDR location to which ATF has to compiled
if DEBUG option is enabled. This is required now, as the ATF cant fit
in OCM with DEBUG option e

zynqmp: Use DDR memory when DEBUG is enabled

Define default DDR location to which ATF has to compiled
if DEBUG option is enabled. This is required now, as the ATF cant fit
in OCM with DEBUG option enabled. The default value is 0x1000 and can be
used till 0x7ffff. User can still override as per wish/requirement
using current commandline options.

Signed-off-by: Jolly Shah <jollys@xilinx.com>

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zynqmp: pm: Add APIs for pin control queries

Add pin control APIs which driver can use to query
pin information from firmware. Using these APIs,
driver do not need to maintain hard-coded pin databas

zynqmp: pm: Add APIs for pin control queries

Add pin control APIs which driver can use to query
pin information from firmware. Using these APIs,
driver do not need to maintain hard-coded pin database.

Major changes in patch are:
- Add pin database with pins, functions and function groups
information
- Implement APIs for pin information queries
- Update pin control APIs for get/set functions to use new
pin control database. Remove pin database which was added
earlier.

Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>

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zynqmp: pm: Add IOCTLs for global storage access

Add IOCTLs to read/write global general storage and
persistent global general storage registers access.

Signed-off-by: Rajan Vaja <rajanv@xilinx.com

zynqmp: pm: Add IOCTLs for global storage access

Add IOCTLs to read/write global general storage and
persistent global general storage registers access.

Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>

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zynqmp: pm: Implement clock APIs

- Add clock entries and information to clock database.
- Implement APIs to provide clock topology and other
information to caller.
- Implement APIs to control cloc

zynqmp: pm: Implement clock APIs

- Add clock entries and information to clock database.
- Implement APIs to provide clock topology and other
information to caller.
- Implement APIs to control clocks and PLLs.

Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>

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zynqmp: pm: Add clock control EEMI API and ioctl functions

These are empty functions with no logic right now. Code
will be added in subsequent commits.

Signed-off-by: Rajan Vaja <rajanv@xilinx.com>

zynqmp: pm: Add clock control EEMI API and ioctl functions

These are empty functions with no logic right now. Code
will be added in subsequent commits.

Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>

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zynqmp: pm: Implement IOCTL APIs for device control

Implement ioctl APIs which uses MMIO operations
to configure devices. Below IOCTLs are supported
in this patch:
* Set tap delay bypass
* Set S

zynqmp: pm: Implement IOCTL APIs for device control

Implement ioctl APIs which uses MMIO operations
to configure devices. Below IOCTLs are supported
in this patch:
* Set tap delay bypass
* Set SGMII mode
* SD reset
* Set SD/MMC tap delay

Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>

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zynqmp: pm: Implement IOCTL APIs for remoteproc

Implement ioctl APIs which uses MMIO operations
to control RPU operations. Below IOCTLs are supported
in this patch:
* Get RPU operation mode
* Se

zynqmp: pm: Implement IOCTL APIs for remoteproc

Implement ioctl APIs which uses MMIO operations
to control RPU operations. Below IOCTLs are supported
in this patch:
* Get RPU operation mode
* Set RPU operation mode
* Configure RPU boot address (OCM/TCM)
* Configure TCM combined mode

Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>

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zynqmp: pm: Implement pin control APIs for configurations

Implement pin control APIs which uses MMIO operations
to set/get values of configuration parameters.

Signed-off-by: Rajan Vaja <rajanv@xili

zynqmp: pm: Implement pin control APIs for configurations

Implement pin control APIs which uses MMIO operations
to set/get values of configuration parameters.

Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>

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zynqmp: pm: Implement pin control APIs for get/set functions

Implement pin control APIs which uses MMIO operations
to set/get functions for the given pin.

Signed-off-by: Rajan Vaja <rajanv@xilinx.c

zynqmp: pm: Implement pin control APIs for get/set functions

Implement pin control APIs which uses MMIO operations
to set/get functions for the given pin.

Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>

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zynqmp: pm: Add wrappers for Pin control APIs

Add wrappers for pin control APIs. Actual implementation of
these APIs would be done in subsequent changes.

Signed-off-by: Rajan Vaja <rajanv@xilinx.co

zynqmp: pm: Add wrappers for Pin control APIs

Add wrappers for pin control APIs. Actual implementation of
these APIs would be done in subsequent changes.

Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>

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zynqmp: Add new function and node IDs

Add new function and node IDs supported by PMUFW in
function list and node list respectively.

Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
Signed-off-by: Joll

zynqmp: Add new function and node IDs

Add new function and node IDs supported by PMUFW in
function list and node list respectively.

Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>

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FVP AArch32: Fix flash access in BL32 for mem_protect

The FVP platform port for SP_MIN (BL32) didn't map the flash memory
in BL32 for stroring the mem_protect enable state information leading
to syn

FVP AArch32: Fix flash access in BL32 for mem_protect

The FVP platform port for SP_MIN (BL32) didn't map the flash memory
in BL32 for stroring the mem_protect enable state information leading
to synchronous exception. The patch fixes it by adding the region to
the BL32 mmap tables.

Change-Id: I37eec83c3e1ea43d1b5504d3683eebc32a57eadf
Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>

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plat/hikey: boot memory layout to dedicated file

Boot memory layout is specific for a platform, but should not be
mixed up with other platform specific attributes. A separate file is
much cleaner an

plat/hikey: boot memory layout to dedicated file

Boot memory layout is specific for a platform, but should not be
mixed up with other platform specific attributes. A separate file is
much cleaner and better to compare with other platforms. Take a look
at plat/poplar where it is done the same way.

Moved hikey_def.h to system include folder and moved includes from
hikey_def.h to more general platform_def.h.

Signed-off-by: Michael Brandl <git@fineon.pw>

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Merge pull request #1303 from soby-mathew/sm/fix_juno_fwu

Juno: Fixes for firmware update

tegra: Use SPDX license identifier

Change-Id: I770b2db68c8d115d10067bb557e32b5e269c94a5
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Merge pull request #1277 from hzhuang1/testing/bl2_el3_v0.6

hikey: migrate to BL2_EL3