1 /* 2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 /* 8 * ZynqMP system level PM-API functions for pin control. 9 */ 10 11 #ifndef _PM_API_IOCTL_H_ 12 #define _PM_API_IOCTL_H_ 13 14 #include "pm_common.h" 15 16 enum pm_ioctl_id { 17 IOCTL_GET_RPU_OPER_MODE, 18 IOCTL_SET_RPU_OPER_MODE, 19 IOCTL_RPU_BOOT_ADDR_CONFIG, 20 IOCTL_TCM_COMB_CONFIG, 21 IOCTL_SET_TAPDELAY_BYPASS, 22 IOCTL_SET_SGMII_MODE, 23 IOCTL_SD_DLL_RESET, 24 IOCTL_SET_SD_TAPDELAY, 25 /* Ioctl for clock driver */ 26 IOCTL_SET_PLL_FRAC_MODE, 27 IOCTL_GET_PLL_FRAC_MODE, 28 IOCTL_SET_PLL_FRAC_DATA, 29 IOCTL_GET_PLL_FRAC_DATA, 30 IOCTL_WRITE_GGS, 31 IOCTL_READ_GGS, 32 IOCTL_WRITE_PGGS, 33 IOCTL_READ_PGGS, 34 }; 35 36 enum rpu_oper_mode { 37 PM_RPU_MODE_LOCKSTEP, 38 PM_RPU_MODE_SPLIT, 39 }; 40 41 enum rpu_boot_mem { 42 PM_RPU_BOOTMEM_LOVEC, 43 PM_RPU_BOOTMEM_HIVEC, 44 }; 45 46 enum rpu_tcm_comb { 47 PM_RPU_TCM_SPLIT, 48 PM_RPU_TCM_COMB, 49 }; 50 51 enum tap_delay_signal_type { 52 PM_TAPDELAY_NAND_DQS_IN, 53 PM_TAPDELAY_NAND_DQS_OUT, 54 PM_TAPDELAY_QSPI, 55 PM_TAPDELAY_MAX, 56 }; 57 58 enum tap_delay_bypass_ctrl { 59 PM_TAPDELAY_BYPASS_DISABLE, 60 PM_TAPDELAY_BYPASS_ENABLE, 61 }; 62 63 enum sgmii_mode { 64 PM_SGMII_DISABLE, 65 PM_SGMII_ENABLE, 66 }; 67 68 enum tap_delay_type { 69 PM_TAPDELAY_INPUT, 70 PM_TAPDELAY_OUTPUT, 71 }; 72 73 enum dll_reset_type { 74 PM_DLL_RESET_ASSERT, 75 PM_DLL_RESET_RELEASE, 76 PM_DLL_RESET_PULSE, 77 }; 78 79 enum pm_ret_status pm_api_ioctl(enum pm_node_id nid, 80 unsigned int ioctl_id, 81 unsigned int arg1, 82 unsigned int arg2, 83 unsigned int *value); 84 #endif /* _PM_API_IOCTL_H_ */ 85