1 /* 2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 /* 8 * ZynqMP system level PM-API functions for pin control. 9 */ 10 11 #ifndef _PM_API_IOCTL_H_ 12 #define _PM_API_IOCTL_H_ 13 14 #include "pm_common.h" 15 16 enum pm_ioctl_id { 17 IOCTL_GET_RPU_OPER_MODE, 18 IOCTL_SET_RPU_OPER_MODE, 19 IOCTL_RPU_BOOT_ADDR_CONFIG, 20 IOCTL_TCM_COMB_CONFIG, 21 IOCTL_SET_TAPDELAY_BYPASS, 22 IOCTL_SET_SGMII_MODE, 23 IOCTL_SD_DLL_RESET, 24 IOCTL_SET_SD_TAPDELAY, 25 /* Ioctl for clock driver */ 26 IOCTL_SET_PLL_FRAC_MODE, 27 IOCTL_GET_PLL_FRAC_MODE, 28 IOCTL_SET_PLL_FRAC_DATA, 29 IOCTL_GET_PLL_FRAC_DATA, 30 }; 31 32 enum rpu_oper_mode { 33 PM_RPU_MODE_LOCKSTEP, 34 PM_RPU_MODE_SPLIT, 35 }; 36 37 enum rpu_boot_mem { 38 PM_RPU_BOOTMEM_LOVEC, 39 PM_RPU_BOOTMEM_HIVEC, 40 }; 41 42 enum rpu_tcm_comb { 43 PM_RPU_TCM_SPLIT, 44 PM_RPU_TCM_COMB, 45 }; 46 47 enum tap_delay_signal_type { 48 PM_TAPDELAY_NAND_DQS_IN, 49 PM_TAPDELAY_NAND_DQS_OUT, 50 PM_TAPDELAY_QSPI, 51 PM_TAPDELAY_MAX, 52 }; 53 54 enum tap_delay_bypass_ctrl { 55 PM_TAPDELAY_BYPASS_DISABLE, 56 PM_TAPDELAY_BYPASS_ENABLE, 57 }; 58 59 enum sgmii_mode { 60 PM_SGMII_DISABLE, 61 PM_SGMII_ENABLE, 62 }; 63 64 enum tap_delay_type { 65 PM_TAPDELAY_INPUT, 66 PM_TAPDELAY_OUTPUT, 67 }; 68 69 enum dll_reset_type { 70 PM_DLL_RESET_ASSERT, 71 PM_DLL_RESET_RELEASE, 72 PM_DLL_RESET_PULSE, 73 }; 74 75 enum pm_ret_status pm_api_ioctl(enum pm_node_id nid, 76 unsigned int ioctl_id, 77 unsigned int arg1, 78 unsigned int arg2, 79 unsigned int *value); 80 #endif /* _PM_API_IOCTL_H_ */ 81