1Trusted Firmware-A Porting Guide 2================================ 3 4 5.. section-numbering:: 6 :suffix: . 7 8.. contents:: 9 10-------------- 11 12Introduction 13------------ 14 15Please note that this document has been updated for the new platform API 16as required by the PSCI v1.0 implementation. Please refer to the 17`Migration Guide`_ for the previous platform API. 18 19Porting Trusted Firmware-A (TF-A) to a new platform involves making some 20mandatory and optional modifications for both the cold and warm boot paths. 21Modifications consist of: 22 23- Implementing a platform-specific function or variable, 24- Setting up the execution context in a certain way, or 25- Defining certain constants (for example #defines). 26 27The platform-specific functions and variables are declared in 28`include/plat/common/platform.h`_. The firmware provides a default implementation 29of variables and functions to fulfill the optional requirements. These 30implementations are all weakly defined; they are provided to ease the porting 31effort. Each platform port can override them with its own implementation if the 32default implementation is inadequate. 33 34Platform ports that want to be aligned with standard Arm platforms (for example 35FVP and Juno) may also use `include/plat/arm/common/plat\_arm.h`_ and the 36corresponding source files in ``plat/arm/common/``. These provide standard 37implementations for some of the required platform porting functions. However, 38using these functions requires the platform port to implement additional 39Arm standard platform porting functions. These additional functions are not 40documented here. 41 42Some modifications are common to all Boot Loader (BL) stages. Section 2 43discusses these in detail. The subsequent sections discuss the remaining 44modifications for each BL stage in detail. 45 46This document should be read in conjunction with the TF-A `User Guide`_. 47 48Common modifications 49-------------------- 50 51This section covers the modifications that should be made by the platform for 52each BL stage to correctly port the firmware stack. They are categorized as 53either mandatory or optional. 54 55Common mandatory modifications 56------------------------------ 57 58A platform port must enable the Memory Management Unit (MMU) as well as the 59instruction and data caches for each BL stage. Setting up the translation 60tables is the responsibility of the platform port because memory maps differ 61across platforms. A memory translation library (see ``lib/xlat_tables/``) is 62provided to help in this setup. 63 64Note that although this library supports non-identity mappings, this is intended 65only for re-mapping peripheral physical addresses and allows platforms with high 66I/O addresses to reduce their virtual address space. All other addresses 67corresponding to code and data must currently use an identity mapping. 68 69Also, the only translation granule size supported in TF-A is 4KB, as various 70parts of the code assume that is the case. It is not possible to switch to 7116 KB or 64 KB granule sizes at the moment. 72 73In Arm standard platforms, each BL stage configures the MMU in the 74platform-specific architecture setup function, ``blX_plat_arch_setup()``, and uses 75an identity mapping for all addresses. 76 77If the build option ``USE_COHERENT_MEM`` is enabled, each platform can allocate a 78block of identity mapped secure memory with Device-nGnRE attributes aligned to 79page boundary (4K) for each BL stage. All sections which allocate coherent 80memory are grouped under ``coherent_ram``. For ex: Bakery locks are placed in a 81section identified by name ``bakery_lock`` inside ``coherent_ram`` so that its 82possible for the firmware to place variables in it using the following C code 83directive: 84 85:: 86 87 __section("bakery_lock") 88 89Or alternatively the following assembler code directive: 90 91:: 92 93 .section bakery_lock 94 95The ``coherent_ram`` section is a sum of all sections like ``bakery_lock`` which are 96used to allocate any data structures that are accessed both when a CPU is 97executing with its MMU and caches enabled, and when it's running with its MMU 98and caches disabled. Examples are given below. 99 100The following variables, functions and constants must be defined by the platform 101for the firmware to work correctly. 102 103File : platform\_def.h [mandatory] 104~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 105 106Each platform must ensure that a header file of this name is in the system 107include path with the following constants defined. This may require updating the 108list of ``PLAT_INCLUDES`` in the ``platform.mk`` file. In the Arm development 109platforms, this file is found in ``plat/arm/board/<plat_name>/include/``. 110 111Platform ports may optionally use the file `include/plat/common/common\_def.h`_, 112which provides typical values for some of the constants below. These values are 113likely to be suitable for all platform ports. 114 115Platform ports that want to be aligned with standard Arm platforms (for example 116FVP and Juno) may also use `include/plat/arm/common/arm\_def.h`_, which provides 117standard values for some of the constants below. However, this requires the 118platform port to define additional platform porting constants in 119``platform_def.h``. These additional constants are not documented here. 120 121- **#define : PLATFORM\_LINKER\_FORMAT** 122 123 Defines the linker format used by the platform, for example 124 ``elf64-littleaarch64``. 125 126- **#define : PLATFORM\_LINKER\_ARCH** 127 128 Defines the processor architecture for the linker by the platform, for 129 example ``aarch64``. 130 131- **#define : PLATFORM\_STACK\_SIZE** 132 133 Defines the normal stack memory available to each CPU. This constant is used 134 by `plat/common/aarch64/platform\_mp\_stack.S`_ and 135 `plat/common/aarch64/platform\_up\_stack.S`_. 136 137- **define : CACHE\_WRITEBACK\_GRANULE** 138 139 Defines the size in bits of the largest cache line across all the cache 140 levels in the platform. 141 142- **#define : FIRMWARE\_WELCOME\_STR** 143 144 Defines the character string printed by BL1 upon entry into the ``bl1_main()`` 145 function. 146 147- **#define : PLATFORM\_CORE\_COUNT** 148 149 Defines the total number of CPUs implemented by the platform across all 150 clusters in the system. 151 152- **#define : PLAT\_NUM\_PWR\_DOMAINS** 153 154 Defines the total number of nodes in the power domain topology 155 tree at all the power domain levels used by the platform. 156 This macro is used by the PSCI implementation to allocate 157 data structures to represent power domain topology. 158 159- **#define : PLAT\_MAX\_PWR\_LVL** 160 161 Defines the maximum power domain level that the power management operations 162 should apply to. More often, but not always, the power domain level 163 corresponds to affinity level. This macro allows the PSCI implementation 164 to know the highest power domain level that it should consider for power 165 management operations in the system that the platform implements. For 166 example, the Base AEM FVP implements two clusters with a configurable 167 number of CPUs and it reports the maximum power domain level as 1. 168 169- **#define : PLAT\_MAX\_OFF\_STATE** 170 171 Defines the local power state corresponding to the deepest power down 172 possible at every power domain level in the platform. The local power 173 states for each level may be sparsely allocated between 0 and this value 174 with 0 being reserved for the RUN state. The PSCI implementation uses this 175 value to initialize the local power states of the power domain nodes and 176 to specify the requested power state for a PSCI\_CPU\_OFF call. 177 178- **#define : PLAT\_MAX\_RET\_STATE** 179 180 Defines the local power state corresponding to the deepest retention state 181 possible at every power domain level in the platform. This macro should be 182 a value less than PLAT\_MAX\_OFF\_STATE and greater than 0. It is used by the 183 PSCI implementation to distinguish between retention and power down local 184 power states within PSCI\_CPU\_SUSPEND call. 185 186- **#define : PLAT\_MAX\_PWR\_LVL\_STATES** 187 188 Defines the maximum number of local power states per power domain level 189 that the platform supports. The default value of this macro is 2 since 190 most platforms just support a maximum of two local power states at each 191 power domain level (power-down and retention). If the platform needs to 192 account for more local power states, then it must redefine this macro. 193 194 Currently, this macro is used by the Generic PSCI implementation to size 195 the array used for PSCI\_STAT\_COUNT/RESIDENCY accounting. 196 197- **#define : BL1\_RO\_BASE** 198 199 Defines the base address in secure ROM where BL1 originally lives. Must be 200 aligned on a page-size boundary. 201 202- **#define : BL1\_RO\_LIMIT** 203 204 Defines the maximum address in secure ROM that BL1's actual content (i.e. 205 excluding any data section allocated at runtime) can occupy. 206 207- **#define : BL1\_RW\_BASE** 208 209 Defines the base address in secure RAM where BL1's read-write data will live 210 at runtime. Must be aligned on a page-size boundary. 211 212- **#define : BL1\_RW\_LIMIT** 213 214 Defines the maximum address in secure RAM that BL1's read-write data can 215 occupy at runtime. 216 217- **#define : BL2\_BASE** 218 219 Defines the base address in secure RAM where BL1 loads the BL2 binary image. 220 Must be aligned on a page-size boundary. 221 222- **#define : BL2\_LIMIT** 223 224 Defines the maximum address in secure RAM that the BL2 image can occupy. 225 226- **#define : BL31\_BASE** 227 228 Defines the base address in secure RAM where BL2 loads the BL31 binary 229 image. Must be aligned on a page-size boundary. 230 231- **#define : BL31\_LIMIT** 232 233 Defines the maximum address in secure RAM that the BL31 image can occupy. 234 235For every image, the platform must define individual identifiers that will be 236used by BL1 or BL2 to load the corresponding image into memory from non-volatile 237storage. For the sake of performance, integer numbers will be used as 238identifiers. The platform will use those identifiers to return the relevant 239information about the image to be loaded (file handler, load address, 240authentication information, etc.). The following image identifiers are 241mandatory: 242 243- **#define : BL2\_IMAGE\_ID** 244 245 BL2 image identifier, used by BL1 to load BL2. 246 247- **#define : BL31\_IMAGE\_ID** 248 249 BL31 image identifier, used by BL2 to load BL31. 250 251- **#define : BL33\_IMAGE\_ID** 252 253 BL33 image identifier, used by BL2 to load BL33. 254 255If Trusted Board Boot is enabled, the following certificate identifiers must 256also be defined: 257 258- **#define : TRUSTED\_BOOT\_FW\_CERT\_ID** 259 260 BL2 content certificate identifier, used by BL1 to load the BL2 content 261 certificate. 262 263- **#define : TRUSTED\_KEY\_CERT\_ID** 264 265 Trusted key certificate identifier, used by BL2 to load the trusted key 266 certificate. 267 268- **#define : SOC\_FW\_KEY\_CERT\_ID** 269 270 BL31 key certificate identifier, used by BL2 to load the BL31 key 271 certificate. 272 273- **#define : SOC\_FW\_CONTENT\_CERT\_ID** 274 275 BL31 content certificate identifier, used by BL2 to load the BL31 content 276 certificate. 277 278- **#define : NON\_TRUSTED\_FW\_KEY\_CERT\_ID** 279 280 BL33 key certificate identifier, used by BL2 to load the BL33 key 281 certificate. 282 283- **#define : NON\_TRUSTED\_FW\_CONTENT\_CERT\_ID** 284 285 BL33 content certificate identifier, used by BL2 to load the BL33 content 286 certificate. 287 288- **#define : FWU\_CERT\_ID** 289 290 Firmware Update (FWU) certificate identifier, used by NS\_BL1U to load the 291 FWU content certificate. 292 293- **#define : PLAT\_CRYPTOCELL\_BASE** 294 295 This defines the base address of Arm® TrustZone® CryptoCell and must be 296 defined if CryptoCell crypto driver is used for Trusted Board Boot. For 297 capable Arm platforms, this driver is used if ``ARM_CRYPTOCELL_INTEG`` is 298 set. 299 300If the AP Firmware Updater Configuration image, BL2U is used, the following 301must also be defined: 302 303- **#define : BL2U\_BASE** 304 305 Defines the base address in secure memory where BL1 copies the BL2U binary 306 image. Must be aligned on a page-size boundary. 307 308- **#define : BL2U\_LIMIT** 309 310 Defines the maximum address in secure memory that the BL2U image can occupy. 311 312- **#define : BL2U\_IMAGE\_ID** 313 314 BL2U image identifier, used by BL1 to fetch an image descriptor 315 corresponding to BL2U. 316 317If the SCP Firmware Update Configuration Image, SCP\_BL2U is used, the following 318must also be defined: 319 320- **#define : SCP\_BL2U\_IMAGE\_ID** 321 322 SCP\_BL2U image identifier, used by BL1 to fetch an image descriptor 323 corresponding to SCP\_BL2U. 324 NOTE: TF-A does not provide source code for this image. 325 326If the Non-Secure Firmware Updater ROM, NS\_BL1U is used, the following must 327also be defined: 328 329- **#define : NS\_BL1U\_BASE** 330 331 Defines the base address in non-secure ROM where NS\_BL1U executes. 332 Must be aligned on a page-size boundary. 333 NOTE: TF-A does not provide source code for this image. 334 335- **#define : NS\_BL1U\_IMAGE\_ID** 336 337 NS\_BL1U image identifier, used by BL1 to fetch an image descriptor 338 corresponding to NS\_BL1U. 339 340If the Non-Secure Firmware Updater, NS\_BL2U is used, the following must also 341be defined: 342 343- **#define : NS\_BL2U\_BASE** 344 345 Defines the base address in non-secure memory where NS\_BL2U executes. 346 Must be aligned on a page-size boundary. 347 NOTE: TF-A does not provide source code for this image. 348 349- **#define : NS\_BL2U\_IMAGE\_ID** 350 351 NS\_BL2U image identifier, used by BL1 to fetch an image descriptor 352 corresponding to NS\_BL2U. 353 354For the the Firmware update capability of TRUSTED BOARD BOOT, the following 355macros may also be defined: 356 357- **#define : PLAT\_FWU\_MAX\_SIMULTANEOUS\_IMAGES** 358 359 Total number of images that can be loaded simultaneously. If the platform 360 doesn't specify any value, it defaults to 10. 361 362If a SCP\_BL2 image is supported by the platform, the following constants must 363also be defined: 364 365- **#define : SCP\_BL2\_IMAGE\_ID** 366 367 SCP\_BL2 image identifier, used by BL2 to load SCP\_BL2 into secure memory 368 from platform storage before being transfered to the SCP. 369 370- **#define : SCP\_FW\_KEY\_CERT\_ID** 371 372 SCP\_BL2 key certificate identifier, used by BL2 to load the SCP\_BL2 key 373 certificate (mandatory when Trusted Board Boot is enabled). 374 375- **#define : SCP\_FW\_CONTENT\_CERT\_ID** 376 377 SCP\_BL2 content certificate identifier, used by BL2 to load the SCP\_BL2 378 content certificate (mandatory when Trusted Board Boot is enabled). 379 380If a BL32 image is supported by the platform, the following constants must 381also be defined: 382 383- **#define : BL32\_IMAGE\_ID** 384 385 BL32 image identifier, used by BL2 to load BL32. 386 387- **#define : TRUSTED\_OS\_FW\_KEY\_CERT\_ID** 388 389 BL32 key certificate identifier, used by BL2 to load the BL32 key 390 certificate (mandatory when Trusted Board Boot is enabled). 391 392- **#define : TRUSTED\_OS\_FW\_CONTENT\_CERT\_ID** 393 394 BL32 content certificate identifier, used by BL2 to load the BL32 content 395 certificate (mandatory when Trusted Board Boot is enabled). 396 397- **#define : BL32\_BASE** 398 399 Defines the base address in secure memory where BL2 loads the BL32 binary 400 image. Must be aligned on a page-size boundary. 401 402- **#define : BL32\_LIMIT** 403 404 Defines the maximum address that the BL32 image can occupy. 405 406If the Test Secure-EL1 Payload (TSP) instantiation of BL32 is supported by the 407platform, the following constants must also be defined: 408 409- **#define : TSP\_SEC\_MEM\_BASE** 410 411 Defines the base address of the secure memory used by the TSP image on the 412 platform. This must be at the same address or below ``BL32_BASE``. 413 414- **#define : TSP\_SEC\_MEM\_SIZE** 415 416 Defines the size of the secure memory used by the BL32 image on the 417 platform. ``TSP_SEC_MEM_BASE`` and ``TSP_SEC_MEM_SIZE`` must fully accomodate 418 the memory required by the BL32 image, defined by ``BL32_BASE`` and 419 ``BL32_LIMIT``. 420 421- **#define : TSP\_IRQ\_SEC\_PHY\_TIMER** 422 423 Defines the ID of the secure physical generic timer interrupt used by the 424 TSP's interrupt handling code. 425 426If the platform port uses the translation table library code, the following 427constants must also be defined: 428 429- **#define : PLAT\_XLAT\_TABLES\_DYNAMIC** 430 431 Optional flag that can be set per-image to enable the dynamic allocation of 432 regions even when the MMU is enabled. If not defined, only static 433 functionality will be available, if defined and set to 1 it will also 434 include the dynamic functionality. 435 436- **#define : MAX\_XLAT\_TABLES** 437 438 Defines the maximum number of translation tables that are allocated by the 439 translation table library code. To minimize the amount of runtime memory 440 used, choose the smallest value needed to map the required virtual addresses 441 for each BL stage. If ``PLAT_XLAT_TABLES_DYNAMIC`` flag is enabled for a BL 442 image, ``MAX_XLAT_TABLES`` must be defined to accommodate the dynamic regions 443 as well. 444 445- **#define : MAX\_MMAP\_REGIONS** 446 447 Defines the maximum number of regions that are allocated by the translation 448 table library code. A region consists of physical base address, virtual base 449 address, size and attributes (Device/Memory, RO/RW, Secure/Non-Secure), as 450 defined in the ``mmap_region_t`` structure. The platform defines the regions 451 that should be mapped. Then, the translation table library will create the 452 corresponding tables and descriptors at runtime. To minimize the amount of 453 runtime memory used, choose the smallest value needed to register the 454 required regions for each BL stage. If ``PLAT_XLAT_TABLES_DYNAMIC`` flag is 455 enabled for a BL image, ``MAX_MMAP_REGIONS`` must be defined to accommodate 456 the dynamic regions as well. 457 458- **#define : ADDR\_SPACE\_SIZE** 459 460 Defines the total size of the address space in bytes. For example, for a 32 461 bit address space, this value should be ``(1ULL << 32)``. This definition is 462 now deprecated, platforms should use ``PLAT_PHY_ADDR_SPACE_SIZE`` and 463 ``PLAT_VIRT_ADDR_SPACE_SIZE`` instead. 464 465- **#define : PLAT\_VIRT\_ADDR\_SPACE\_SIZE** 466 467 Defines the total size of the virtual address space in bytes. For example, 468 for a 32 bit virtual address space, this value should be ``(1ULL << 32)``. 469 470- **#define : PLAT\_PHY\_ADDR\_SPACE\_SIZE** 471 472 Defines the total size of the physical address space in bytes. For example, 473 for a 32 bit physical address space, this value should be ``(1ULL << 32)``. 474 475If the platform port uses the IO storage framework, the following constants 476must also be defined: 477 478- **#define : MAX\_IO\_DEVICES** 479 480 Defines the maximum number of registered IO devices. Attempting to register 481 more devices than this value using ``io_register_device()`` will fail with 482 -ENOMEM. 483 484- **#define : MAX\_IO\_HANDLES** 485 486 Defines the maximum number of open IO handles. Attempting to open more IO 487 entities than this value using ``io_open()`` will fail with -ENOMEM. 488 489- **#define : MAX\_IO\_BLOCK\_DEVICES** 490 491 Defines the maximum number of registered IO block devices. Attempting to 492 register more devices this value using ``io_dev_open()`` will fail 493 with -ENOMEM. MAX\_IO\_BLOCK\_DEVICES should be less than MAX\_IO\_DEVICES. 494 With this macro, multiple block devices could be supported at the same 495 time. 496 497If the platform needs to allocate data within the per-cpu data framework in 498BL31, it should define the following macro. Currently this is only required if 499the platform decides not to use the coherent memory section by undefining the 500``USE_COHERENT_MEM`` build flag. In this case, the framework allocates the 501required memory within the the per-cpu data to minimize wastage. 502 503- **#define : PLAT\_PCPU\_DATA\_SIZE** 504 505 Defines the memory (in bytes) to be reserved within the per-cpu data 506 structure for use by the platform layer. 507 508The following constants are optional. They should be defined when the platform 509memory layout implies some image overlaying like in Arm standard platforms. 510 511- **#define : BL31\_PROGBITS\_LIMIT** 512 513 Defines the maximum address in secure RAM that the BL31's progbits sections 514 can occupy. 515 516- **#define : TSP\_PROGBITS\_LIMIT** 517 518 Defines the maximum address that the TSP's progbits sections can occupy. 519 520If the platform port uses the PL061 GPIO driver, the following constant may 521optionally be defined: 522 523- **PLAT\_PL061\_MAX\_GPIOS** 524 Maximum number of GPIOs required by the platform. This allows control how 525 much memory is allocated for PL061 GPIO controllers. The default value is 526 527 #. $(eval $(call add\_define,PLAT\_PL061\_MAX\_GPIOS)) 528 529If the platform port uses the partition driver, the following constant may 530optionally be defined: 531 532- **PLAT\_PARTITION\_MAX\_ENTRIES** 533 Maximum number of partition entries required by the platform. This allows 534 control how much memory is allocated for partition entries. The default 535 value is 128. 536 `For example, define the build flag in platform.mk`_: 537 PLAT\_PARTITION\_MAX\_ENTRIES := 12 538 $(eval $(call add\_define,PLAT\_PARTITION\_MAX\_ENTRIES)) 539 540The following constant is optional. It should be defined to override the default 541behaviour of the ``assert()`` function (for example, to save memory). 542 543- **PLAT\_LOG\_LEVEL\_ASSERT** 544 If ``PLAT_LOG_LEVEL_ASSERT`` is higher or equal than ``LOG_LEVEL_VERBOSE``, 545 ``assert()`` prints the name of the file, the line number and the asserted 546 expression. Else if it is higher than ``LOG_LEVEL_INFO``, it prints the file 547 name and the line number. Else if it is lower than ``LOG_LEVEL_INFO``, it 548 doesn't print anything to the console. If ``PLAT_LOG_LEVEL_ASSERT`` isn't 549 defined, it defaults to ``LOG_LEVEL``. 550 551If the platform port uses the Activity Monitor Unit, the following constants 552may be defined: 553 554- **PLAT\_AMU\_GROUP1\_COUNTERS\_MASK** 555 This mask reflects the set of group counters that should be enabled. The 556 maximum number of group 1 counters supported by AMUv1 is 16 so the mask 557 can be at most 0xffff. If the platform does not define this mask, no group 1 558 counters are enabled. If the platform defines this mask, the following 559 constant needs to also be defined. 560 561- **PLAT\_AMU\_GROUP1\_NR\_COUNTERS** 562 This value is used to allocate an array to save and restore the counters 563 specified by ``PLAT_AMU_GROUP1_COUNTERS_MASK`` on CPU suspend. 564 This value should be equal to the highest bit position set in the 565 mask, plus 1. The maximum number of group 1 counters in AMUv1 is 16. 566 567File : plat\_macros.S [mandatory] 568~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 569 570Each platform must ensure a file of this name is in the system include path with 571the following macro defined. In the Arm development platforms, this file is 572found in ``plat/arm/board/<plat_name>/include/plat_macros.S``. 573 574- **Macro : plat\_crash\_print\_regs** 575 576 This macro allows the crash reporting routine to print relevant platform 577 registers in case of an unhandled exception in BL31. This aids in debugging 578 and this macro can be defined to be empty in case register reporting is not 579 desired. 580 581 For instance, GIC or interconnect registers may be helpful for 582 troubleshooting. 583 584Handling Reset 585-------------- 586 587BL1 by default implements the reset vector where execution starts from a cold 588or warm boot. BL31 can be optionally set as a reset vector using the 589``RESET_TO_BL31`` make variable. 590 591For each CPU, the reset vector code is responsible for the following tasks: 592 593#. Distinguishing between a cold boot and a warm boot. 594 595#. In the case of a cold boot and the CPU being a secondary CPU, ensuring that 596 the CPU is placed in a platform-specific state until the primary CPU 597 performs the necessary steps to remove it from this state. 598 599#. In the case of a warm boot, ensuring that the CPU jumps to a platform- 600 specific address in the BL31 image in the same processor mode as it was 601 when released from reset. 602 603The following functions need to be implemented by the platform port to enable 604reset vector code to perform the above tasks. 605 606Function : plat\_get\_my\_entrypoint() [mandatory when PROGRAMMABLE\_RESET\_ADDRESS == 0] 607~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 608 609:: 610 611 Argument : void 612 Return : uintptr_t 613 614This function is called with the MMU and caches disabled 615(``SCTLR_EL3.M`` = 0 and ``SCTLR_EL3.C`` = 0). The function is responsible for 616distinguishing between a warm and cold reset for the current CPU using 617platform-specific means. If it's a warm reset, then it returns the warm 618reset entrypoint point provided to ``plat_setup_psci_ops()`` during 619BL31 initialization. If it's a cold reset then this function must return zero. 620 621This function does not follow the Procedure Call Standard used by the 622Application Binary Interface for the Arm 64-bit architecture. The caller should 623not assume that callee saved registers are preserved across a call to this 624function. 625 626This function fulfills requirement 1 and 3 listed above. 627 628Note that for platforms that support programming the reset address, it is 629expected that a CPU will start executing code directly at the right address, 630both on a cold and warm reset. In this case, there is no need to identify the 631type of reset nor to query the warm reset entrypoint. Therefore, implementing 632this function is not required on such platforms. 633 634Function : plat\_secondary\_cold\_boot\_setup() [mandatory when COLD\_BOOT\_SINGLE\_CPU == 0] 635~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 636 637:: 638 639 Argument : void 640 641This function is called with the MMU and data caches disabled. It is responsible 642for placing the executing secondary CPU in a platform-specific state until the 643primary CPU performs the necessary actions to bring it out of that state and 644allow entry into the OS. This function must not return. 645 646In the Arm FVP port, when using the normal boot flow, each secondary CPU powers 647itself off. The primary CPU is responsible for powering up the secondary CPUs 648when normal world software requires them. When booting an EL3 payload instead, 649they stay powered on and are put in a holding pen until their mailbox gets 650populated. 651 652This function fulfills requirement 2 above. 653 654Note that for platforms that can't release secondary CPUs out of reset, only the 655primary CPU will execute the cold boot code. Therefore, implementing this 656function is not required on such platforms. 657 658Function : plat\_is\_my\_cpu\_primary() [mandatory when COLD\_BOOT\_SINGLE\_CPU == 0] 659~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 660 661:: 662 663 Argument : void 664 Return : unsigned int 665 666This function identifies whether the current CPU is the primary CPU or a 667secondary CPU. A return value of zero indicates that the CPU is not the 668primary CPU, while a non-zero return value indicates that the CPU is the 669primary CPU. 670 671Note that for platforms that can't release secondary CPUs out of reset, only the 672primary CPU will execute the cold boot code. Therefore, there is no need to 673distinguish between primary and secondary CPUs and implementing this function is 674not required. 675 676Function : platform\_mem\_init() [mandatory] 677~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 678 679:: 680 681 Argument : void 682 Return : void 683 684This function is called before any access to data is made by the firmware, in 685order to carry out any essential memory initialization. 686 687Function: plat\_get\_rotpk\_info() 688~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 689 690:: 691 692 Argument : void *, void **, unsigned int *, unsigned int * 693 Return : int 694 695This function is mandatory when Trusted Board Boot is enabled. It returns a 696pointer to the ROTPK stored in the platform (or a hash of it) and its length. 697The ROTPK must be encoded in DER format according to the following ASN.1 698structure: 699 700:: 701 702 AlgorithmIdentifier ::= SEQUENCE { 703 algorithm OBJECT IDENTIFIER, 704 parameters ANY DEFINED BY algorithm OPTIONAL 705 } 706 707 SubjectPublicKeyInfo ::= SEQUENCE { 708 algorithm AlgorithmIdentifier, 709 subjectPublicKey BIT STRING 710 } 711 712In case the function returns a hash of the key: 713 714:: 715 716 DigestInfo ::= SEQUENCE { 717 digestAlgorithm AlgorithmIdentifier, 718 digest OCTET STRING 719 } 720 721The function returns 0 on success. Any other value is treated as error by the 722Trusted Board Boot. The function also reports extra information related 723to the ROTPK in the flags parameter: 724 725:: 726 727 ROTPK_IS_HASH : Indicates that the ROTPK returned by the platform is a 728 hash. 729 ROTPK_NOT_DEPLOYED : This allows the platform to skip certificate ROTPK 730 verification while the platform ROTPK is not deployed. 731 When this flag is set, the function does not need to 732 return a platform ROTPK, and the authentication 733 framework uses the ROTPK in the certificate without 734 verifying it against the platform value. This flag 735 must not be used in a deployed production environment. 736 737Function: plat\_get\_nv\_ctr() 738~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 739 740:: 741 742 Argument : void *, unsigned int * 743 Return : int 744 745This function is mandatory when Trusted Board Boot is enabled. It returns the 746non-volatile counter value stored in the platform in the second argument. The 747cookie in the first argument may be used to select the counter in case the 748platform provides more than one (for example, on platforms that use the default 749TBBR CoT, the cookie will correspond to the OID values defined in 750TRUSTED\_FW\_NVCOUNTER\_OID or NON\_TRUSTED\_FW\_NVCOUNTER\_OID). 751 752The function returns 0 on success. Any other value means the counter value could 753not be retrieved from the platform. 754 755Function: plat\_set\_nv\_ctr() 756~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 757 758:: 759 760 Argument : void *, unsigned int 761 Return : int 762 763This function is mandatory when Trusted Board Boot is enabled. It sets a new 764counter value in the platform. The cookie in the first argument may be used to 765select the counter (as explained in plat\_get\_nv\_ctr()). The second argument is 766the updated counter value to be written to the NV counter. 767 768The function returns 0 on success. Any other value means the counter value could 769not be updated. 770 771Function: plat\_set\_nv\_ctr2() 772~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 773 774:: 775 776 Argument : void *, const auth_img_desc_t *, unsigned int 777 Return : int 778 779This function is optional when Trusted Board Boot is enabled. If this 780interface is defined, then ``plat_set_nv_ctr()`` need not be defined. The 781first argument passed is a cookie and is typically used to 782differentiate between a Non Trusted NV Counter and a Trusted NV 783Counter. The second argument is a pointer to an authentication image 784descriptor and may be used to decide if the counter is allowed to be 785updated or not. The third argument is the updated counter value to 786be written to the NV counter. 787 788The function returns 0 on success. Any other value means the counter value 789either could not be updated or the authentication image descriptor indicates 790that it is not allowed to be updated. 791 792Common mandatory function modifications 793--------------------------------------- 794 795The following functions are mandatory functions which need to be implemented 796by the platform port. 797 798Function : plat\_my\_core\_pos() 799~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 800 801:: 802 803 Argument : void 804 Return : unsigned int 805 806This funtion returns the index of the calling CPU which is used as a 807CPU-specific linear index into blocks of memory (for example while allocating 808per-CPU stacks). This function will be invoked very early in the 809initialization sequence which mandates that this function should be 810implemented in assembly and should not rely on the avalability of a C 811runtime environment. This function can clobber x0 - x8 and must preserve 812x9 - x29. 813 814This function plays a crucial role in the power domain topology framework in 815PSCI and details of this can be found in `Power Domain Topology Design`_. 816 817Function : plat\_core\_pos\_by\_mpidr() 818~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 819 820:: 821 822 Argument : u_register_t 823 Return : int 824 825This function validates the ``MPIDR`` of a CPU and converts it to an index, 826which can be used as a CPU-specific linear index into blocks of memory. In 827case the ``MPIDR`` is invalid, this function returns -1. This function will only 828be invoked by BL31 after the power domain topology is initialized and can 829utilize the C runtime environment. For further details about how TF-A 830represents the power domain topology and how this relates to the linear CPU 831index, please refer `Power Domain Topology Design`_. 832 833Common optional modifications 834----------------------------- 835 836The following are helper functions implemented by the firmware that perform 837common platform-specific tasks. A platform may choose to override these 838definitions. 839 840Function : plat\_set\_my\_stack() 841~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 842 843:: 844 845 Argument : void 846 Return : void 847 848This function sets the current stack pointer to the normal memory stack that 849has been allocated for the current CPU. For BL images that only require a 850stack for the primary CPU, the UP version of the function is used. The size 851of the stack allocated to each CPU is specified by the platform defined 852constant ``PLATFORM_STACK_SIZE``. 853 854Common implementations of this function for the UP and MP BL images are 855provided in `plat/common/aarch64/platform\_up\_stack.S`_ and 856`plat/common/aarch64/platform\_mp\_stack.S`_ 857 858Function : plat\_get\_my\_stack() 859~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 860 861:: 862 863 Argument : void 864 Return : uintptr_t 865 866This function returns the base address of the normal memory stack that 867has been allocated for the current CPU. For BL images that only require a 868stack for the primary CPU, the UP version of the function is used. The size 869of the stack allocated to each CPU is specified by the platform defined 870constant ``PLATFORM_STACK_SIZE``. 871 872Common implementations of this function for the UP and MP BL images are 873provided in `plat/common/aarch64/platform\_up\_stack.S`_ and 874`plat/common/aarch64/platform\_mp\_stack.S`_ 875 876Function : plat\_report\_exception() 877~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 878 879:: 880 881 Argument : unsigned int 882 Return : void 883 884A platform may need to report various information about its status when an 885exception is taken, for example the current exception level, the CPU security 886state (secure/non-secure), the exception type, and so on. This function is 887called in the following circumstances: 888 889- In BL1, whenever an exception is taken. 890- In BL2, whenever an exception is taken. 891 892The default implementation doesn't do anything, to avoid making assumptions 893about the way the platform displays its status information. 894 895For AArch64, this function receives the exception type as its argument. 896Possible values for exceptions types are listed in the 897`include/common/bl\_common.h`_ header file. Note that these constants are not 898related to any architectural exception code; they are just a TF-A convention. 899 900For AArch32, this function receives the exception mode as its argument. 901Possible values for exception modes are listed in the 902`include/lib/aarch32/arch.h`_ header file. 903 904Function : plat\_reset\_handler() 905~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 906 907:: 908 909 Argument : void 910 Return : void 911 912A platform may need to do additional initialization after reset. This function 913allows the platform to do the platform specific intializations. Platform 914specific errata workarounds could also be implemented here. The api should 915preserve the values of callee saved registers x19 to x29. 916 917The default implementation doesn't do anything. If a platform needs to override 918the default implementation, refer to the `Firmware Design`_ for general 919guidelines. 920 921Function : plat\_disable\_acp() 922~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 923 924:: 925 926 Argument : void 927 Return : void 928 929This api allows a platform to disable the Accelerator Coherency Port (if 930present) during a cluster power down sequence. The default weak implementation 931doesn't do anything. Since this api is called during the power down sequence, 932it has restrictions for stack usage and it can use the registers x0 - x17 as 933scratch registers. It should preserve the value in x18 register as it is used 934by the caller to store the return address. 935 936Function : plat\_error\_handler() 937~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 938 939:: 940 941 Argument : int 942 Return : void 943 944This API is called when the generic code encounters an error situation from 945which it cannot continue. It allows the platform to perform error reporting or 946recovery actions (for example, reset the system). This function must not return. 947 948The parameter indicates the type of error using standard codes from ``errno.h``. 949Possible errors reported by the generic code are: 950 951- ``-EAUTH``: a certificate or image could not be authenticated (when Trusted 952 Board Boot is enabled) 953- ``-ENOENT``: the requested image or certificate could not be found or an IO 954 error was detected 955- ``-ENOMEM``: resources exhausted. TF-A does not use dynamic memory, so this 956 error is usually an indication of an incorrect array size 957 958The default implementation simply spins. 959 960Function : plat\_panic\_handler() 961~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 962 963:: 964 965 Argument : void 966 Return : void 967 968This API is called when the generic code encounters an unexpected error 969situation from which it cannot recover. This function must not return, 970and must be implemented in assembly because it may be called before the C 971environment is initialized. 972 973Note: The address from where it was called is stored in x30 (Link Register). 974The default implementation simply spins. 975 976Function : plat\_get\_bl\_image\_load\_info() 977~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 978 979:: 980 981 Argument : void 982 Return : bl_load_info_t * 983 984This function returns pointer to the list of images that the platform has 985populated to load. This function is currently invoked in BL2 to load the 986BL3xx images, when LOAD\_IMAGE\_V2 is enabled. 987 988Function : plat\_get\_next\_bl\_params() 989~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 990 991:: 992 993 Argument : void 994 Return : bl_params_t * 995 996This function returns a pointer to the shared memory that the platform has 997kept aside to pass TF-A related information that next BL image needs. This 998function is currently invoked in BL2 to pass this information to the next BL 999image, when LOAD\_IMAGE\_V2 is enabled. 1000 1001Function : plat\_get\_stack\_protector\_canary() 1002~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1003 1004:: 1005 1006 Argument : void 1007 Return : u_register_t 1008 1009This function returns a random value that is used to initialize the canary used 1010when the stack protector is enabled with ENABLE\_STACK\_PROTECTOR. A predictable 1011value will weaken the protection as the attacker could easily write the right 1012value as part of the attack most of the time. Therefore, it should return a 1013true random number. 1014 1015Note: For the protection to be effective, the global data need to be placed at 1016a lower address than the stack bases. Failure to do so would allow an attacker 1017to overwrite the canary as part of the stack buffer overflow attack. 1018 1019Function : plat\_flush\_next\_bl\_params() 1020~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1021 1022:: 1023 1024 Argument : void 1025 Return : void 1026 1027This function flushes to main memory all the image params that are passed to 1028next image. This function is currently invoked in BL2 to flush this information 1029to the next BL image, when LOAD\_IMAGE\_V2 is enabled. 1030 1031Function : plat\_log\_get\_prefix() 1032~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1033 1034:: 1035 1036 Argument : unsigned int 1037 Return : const char * 1038 1039This function defines the prefix string corresponding to the `log_level` to be 1040prepended to all the log output from TF-A. The `log_level` (argument) will 1041correspond to one of the standard log levels defined in debug.h. The platform 1042can override the common implementation to define a different prefix string for 1043the log output. The implementation should be robust to future changes that 1044increase the number of log levels. 1045 1046Modifications specific to a Boot Loader stage 1047--------------------------------------------- 1048 1049Boot Loader Stage 1 (BL1) 1050------------------------- 1051 1052BL1 implements the reset vector where execution starts from after a cold or 1053warm boot. For each CPU, BL1 is responsible for the following tasks: 1054 1055#. Handling the reset as described in section 2.2 1056 1057#. In the case of a cold boot and the CPU being the primary CPU, ensuring that 1058 only this CPU executes the remaining BL1 code, including loading and passing 1059 control to the BL2 stage. 1060 1061#. Identifying and starting the Firmware Update process (if required). 1062 1063#. Loading the BL2 image from non-volatile storage into secure memory at the 1064 address specified by the platform defined constant ``BL2_BASE``. 1065 1066#. Populating a ``meminfo`` structure with the following information in memory, 1067 accessible by BL2 immediately upon entry. 1068 1069 :: 1070 1071 meminfo.total_base = Base address of secure RAM visible to BL2 1072 meminfo.total_size = Size of secure RAM visible to BL2 1073 meminfo.free_base = Base address of secure RAM available for 1074 allocation to BL2 1075 meminfo.free_size = Size of secure RAM available for allocation to BL2 1076 1077 By default, BL1 places this ``meminfo`` structure at the beginning of the 1078 free memory available for its use. Since BL1 cannot allocate memory 1079 dynamically at the moment, its free memory will be available for BL2's use 1080 as-is. However, this means that BL2 must read the ``meminfo`` structure 1081 before it starts using its free memory (this is discussed in Section 3.2). 1082 1083 It is possible for the platform to decide where it wants to place the 1084 ``meminfo`` structure for BL2 or restrict the amount of memory visible to 1085 BL2 by overriding the weak default implementation of 1086 ``bl1_plat_handle_post_image_load`` API. 1087 1088The following functions need to be implemented by the platform port to enable 1089BL1 to perform the above tasks. 1090 1091Function : bl1\_early\_platform\_setup() [mandatory] 1092~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1093 1094:: 1095 1096 Argument : void 1097 Return : void 1098 1099This function executes with the MMU and data caches disabled. It is only called 1100by the primary CPU. 1101 1102On Arm standard platforms, this function: 1103 1104- Enables a secure instance of SP805 to act as the Trusted Watchdog. 1105 1106- Initializes a UART (PL011 console), which enables access to the ``printf`` 1107 family of functions in BL1. 1108 1109- Enables issuing of snoop and DVM (Distributed Virtual Memory) requests to 1110 the CCI slave interface corresponding to the cluster that includes the 1111 primary CPU. 1112 1113Function : bl1\_plat\_arch\_setup() [mandatory] 1114~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1115 1116:: 1117 1118 Argument : void 1119 Return : void 1120 1121This function performs any platform-specific and architectural setup that the 1122platform requires. Platform-specific setup might include configuration of 1123memory controllers and the interconnect. 1124 1125In Arm standard platforms, this function enables the MMU. 1126 1127This function helps fulfill requirement 2 above. 1128 1129Function : bl1\_platform\_setup() [mandatory] 1130~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1131 1132:: 1133 1134 Argument : void 1135 Return : void 1136 1137This function executes with the MMU and data caches enabled. It is responsible 1138for performing any remaining platform-specific setup that can occur after the 1139MMU and data cache have been enabled. 1140 1141if support for multiple boot sources is required, it initializes the boot 1142sequence used by plat\_try\_next\_boot\_source(). 1143 1144In Arm standard platforms, this function initializes the storage abstraction 1145layer used to load the next bootloader image. 1146 1147This function helps fulfill requirement 4 above. 1148 1149Function : bl1\_plat\_sec\_mem\_layout() [mandatory] 1150~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1151 1152:: 1153 1154 Argument : void 1155 Return : meminfo * 1156 1157This function should only be called on the cold boot path. It executes with the 1158MMU and data caches enabled. The pointer returned by this function must point to 1159a ``meminfo`` structure containing the extents and availability of secure RAM for 1160the BL1 stage. 1161 1162:: 1163 1164 meminfo.total_base = Base address of secure RAM visible to BL1 1165 meminfo.total_size = Size of secure RAM visible to BL1 1166 meminfo.free_base = Base address of secure RAM available for allocation 1167 to BL1 1168 meminfo.free_size = Size of secure RAM available for allocation to BL1 1169 1170This information is used by BL1 to load the BL2 image in secure RAM. BL1 also 1171populates a similar structure to tell BL2 the extents of memory available for 1172its own use. 1173 1174This function helps fulfill requirements 4 and 5 above. 1175 1176Function : bl1\_plat\_prepare\_exit() [optional] 1177~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1178 1179:: 1180 1181 Argument : entry_point_info_t * 1182 Return : void 1183 1184This function is called prior to exiting BL1 in response to the 1185``BL1_SMC_RUN_IMAGE`` SMC request raised by BL2. It should be used to perform 1186platform specific clean up or bookkeeping operations before transferring 1187control to the next image. It receives the address of the ``entry_point_info_t`` 1188structure passed from BL2. This function runs with MMU disabled. 1189 1190Function : bl1\_plat\_set\_ep\_info() [optional] 1191~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1192 1193:: 1194 1195 Argument : unsigned int image_id, entry_point_info_t *ep_info 1196 Return : void 1197 1198This function allows platforms to override ``ep_info`` for the given ``image_id``. 1199 1200The default implementation just returns. 1201 1202Function : bl1\_plat\_get\_next\_image\_id() [optional] 1203~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1204 1205:: 1206 1207 Argument : void 1208 Return : unsigned int 1209 1210This and the following function must be overridden to enable the FWU feature. 1211 1212BL1 calls this function after platform setup to identify the next image to be 1213loaded and executed. If the platform returns ``BL2_IMAGE_ID`` then BL1 proceeds 1214with the normal boot sequence, which loads and executes BL2. If the platform 1215returns a different image id, BL1 assumes that Firmware Update is required. 1216 1217The default implementation always returns ``BL2_IMAGE_ID``. The Arm development 1218platforms override this function to detect if firmware update is required, and 1219if so, return the first image in the firmware update process. 1220 1221Function : bl1\_plat\_get\_image\_desc() [optional] 1222~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1223 1224:: 1225 1226 Argument : unsigned int image_id 1227 Return : image_desc_t * 1228 1229BL1 calls this function to get the image descriptor information ``image_desc_t`` 1230for the provided ``image_id`` from the platform. 1231 1232The default implementation always returns a common BL2 image descriptor. Arm 1233standard platforms return an image descriptor corresponding to BL2 or one of 1234the firmware update images defined in the Trusted Board Boot Requirements 1235specification. 1236 1237Function : bl1\_plat\_handle\_pre\_image\_load() [optional] 1238~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1239 1240:: 1241 1242 Argument : unsigned int image_id 1243 Return : int 1244 1245This function can be used by the platforms to update/use image information 1246corresponding to ``image_id``. This function is invoked in BL1, both in cold 1247boot and FWU code path, before loading the image. 1248 1249Function : bl1\_plat\_handle\_post\_image\_load() [optional] 1250~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1251 1252:: 1253 1254 Argument : unsigned int image_id 1255 Return : int 1256 1257This function can be used by the platforms to update/use image information 1258corresponding to ``image_id``. This function is invoked in BL1, both in cold 1259boot and FWU code path, after loading and authenticating the image. 1260 1261The default weak implementation of this function calculates the amount of 1262Trusted SRAM that can be used by BL2 and allocates a ``meminfo_t`` 1263structure at the beginning of this free memory and populates it. The address 1264of ``meminfo_t`` structure is updated in ``arg1`` of the entrypoint 1265information to BL2. 1266 1267Function : bl1\_plat\_fwu\_done() [optional] 1268~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1269 1270:: 1271 1272 Argument : unsigned int image_id, uintptr_t image_src, 1273 unsigned int image_size 1274 Return : void 1275 1276BL1 calls this function when the FWU process is complete. It must not return. 1277The platform may override this function to take platform specific action, for 1278example to initiate the normal boot flow. 1279 1280The default implementation spins forever. 1281 1282Function : bl1\_plat\_mem\_check() [mandatory] 1283~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1284 1285:: 1286 1287 Argument : uintptr_t mem_base, unsigned int mem_size, 1288 unsigned int flags 1289 Return : int 1290 1291BL1 calls this function while handling FWU related SMCs, more specifically when 1292copying or authenticating an image. Its responsibility is to ensure that the 1293region of memory identified by ``mem_base`` and ``mem_size`` is mapped in BL1, and 1294that this memory corresponds to either a secure or non-secure memory region as 1295indicated by the security state of the ``flags`` argument. 1296 1297This function can safely assume that the value resulting from the addition of 1298``mem_base`` and ``mem_size`` fits into a ``uintptr_t`` type variable and does not 1299overflow. 1300 1301This function must return 0 on success, a non-null error code otherwise. 1302 1303The default implementation of this function asserts therefore platforms must 1304override it when using the FWU feature. 1305 1306Boot Loader Stage 2 (BL2) 1307------------------------- 1308 1309The BL2 stage is executed only by the primary CPU, which is determined in BL1 1310using the ``platform_is_primary_cpu()`` function. BL1 passed control to BL2 at 1311``BL2_BASE``. BL2 executes in Secure EL1 and is responsible for: 1312 1313#. (Optional) Loading the SCP\_BL2 binary image (if present) from platform 1314 provided non-volatile storage. To load the SCP\_BL2 image, BL2 makes use of 1315 the ``meminfo`` returned by the ``bl2_plat_get_scp_bl2_meminfo()`` function. 1316 The platform also defines the address in memory where SCP\_BL2 is loaded 1317 through the optional constant ``SCP_BL2_BASE``. BL2 uses this information 1318 to determine if there is enough memory to load the SCP\_BL2 image. 1319 Subsequent handling of the SCP\_BL2 image is platform-specific and is 1320 implemented in the ``bl2_plat_handle_scp_bl2()`` function. 1321 If ``SCP_BL2_BASE`` is not defined then this step is not performed. 1322 1323#. Loading the BL31 binary image into secure RAM from non-volatile storage. To 1324 load the BL31 image, BL2 makes use of the ``meminfo`` structure passed to it 1325 by BL1. This structure allows BL2 to calculate how much secure RAM is 1326 available for its use. The platform also defines the address in secure RAM 1327 where BL31 is loaded through the constant ``BL31_BASE``. BL2 uses this 1328 information to determine if there is enough memory to load the BL31 image. 1329 1330#. (Optional) Loading the BL32 binary image (if present) from platform 1331 provided non-volatile storage. To load the BL32 image, BL2 makes use of 1332 the ``meminfo`` returned by the ``bl2_plat_get_bl32_meminfo()`` function. 1333 The platform also defines the address in memory where BL32 is loaded 1334 through the optional constant ``BL32_BASE``. BL2 uses this information 1335 to determine if there is enough memory to load the BL32 image. 1336 If ``BL32_BASE`` is not defined then this and the next step is not performed. 1337 1338#. (Optional) Arranging to pass control to the BL32 image (if present) that 1339 has been pre-loaded at ``BL32_BASE``. BL2 populates an ``entry_point_info`` 1340 structure in memory provided by the platform with information about how 1341 BL31 should pass control to the BL32 image. 1342 1343#. (Optional) Loading the normal world BL33 binary image (if not loaded by 1344 other means) into non-secure DRAM from platform storage and arranging for 1345 BL31 to pass control to this image. This address is determined using the 1346 ``plat_get_ns_image_entrypoint()`` function described below. 1347 1348#. BL2 populates an ``entry_point_info`` structure in memory provided by the 1349 platform with information about how BL31 should pass control to the 1350 other BL images. 1351 1352The following functions must be implemented by the platform port to enable BL2 1353to perform the above tasks. 1354 1355Function : bl2\_early\_platform\_setup() [mandatory] 1356~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1357 1358:: 1359 1360 Argument : meminfo * 1361 Return : void 1362 1363This function executes with the MMU and data caches disabled. It is only called 1364by the primary CPU. The arguments to this function is the address of the 1365``meminfo`` structure populated by BL1. 1366 1367The platform may copy the contents of the ``meminfo`` structure into a private 1368variable as the original memory may be subsequently overwritten by BL2. The 1369copied structure is made available to all BL2 code through the 1370``bl2_plat_sec_mem_layout()`` function. 1371 1372On Arm standard platforms, this function also: 1373 1374- Initializes a UART (PL011 console), which enables access to the ``printf`` 1375 family of functions in BL2. 1376 1377- Initializes the storage abstraction layer used to load further bootloader 1378 images. It is necessary to do this early on platforms with a SCP\_BL2 image, 1379 since the later ``bl2_platform_setup`` must be done after SCP\_BL2 is loaded. 1380 1381Function : bl2\_plat\_arch\_setup() [mandatory] 1382~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1383 1384:: 1385 1386 Argument : void 1387 Return : void 1388 1389This function executes with the MMU and data caches disabled. It is only called 1390by the primary CPU. 1391 1392The purpose of this function is to perform any architectural initialization 1393that varies across platforms. 1394 1395On Arm standard platforms, this function enables the MMU. 1396 1397Function : bl2\_platform\_setup() [mandatory] 1398~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1399 1400:: 1401 1402 Argument : void 1403 Return : void 1404 1405This function may execute with the MMU and data caches enabled if the platform 1406port does the necessary initialization in ``bl2_plat_arch_setup()``. It is only 1407called by the primary CPU. 1408 1409The purpose of this function is to perform any platform initialization 1410specific to BL2. 1411 1412In Arm standard platforms, this function performs security setup, including 1413configuration of the TrustZone controller to allow non-secure masters access 1414to most of DRAM. Part of DRAM is reserved for secure world use. 1415 1416Function : bl2\_plat\_sec\_mem\_layout() [mandatory] 1417~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1418 1419:: 1420 1421 Argument : void 1422 Return : meminfo * 1423 1424This function should only be called on the cold boot path. It may execute with 1425the MMU and data caches enabled if the platform port does the necessary 1426initialization in ``bl2_plat_arch_setup()``. It is only called by the primary CPU. 1427 1428The purpose of this function is to return a pointer to a ``meminfo`` structure 1429populated with the extents of secure RAM available for BL2 to use. See 1430``bl2_early_platform_setup()`` above. 1431 1432Following functions are optionally used only when LOAD\_IMAGE\_V2 is enabled. 1433 1434Function : bl2\_plat\_handle\_pre\_image\_load() [optional] 1435~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1436 1437:: 1438 1439 Argument : unsigned int 1440 Return : int 1441 1442This function can be used by the platforms to update/use image information 1443for given ``image_id``. This function is currently invoked in BL2 before 1444loading each image, when LOAD\_IMAGE\_V2 is enabled. 1445 1446Function : bl2\_plat\_handle\_post\_image\_load() [optional] 1447~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1448 1449:: 1450 1451 Argument : unsigned int 1452 Return : int 1453 1454This function can be used by the platforms to update/use image information 1455for given ``image_id``. This function is currently invoked in BL2 after 1456loading each image, when LOAD\_IMAGE\_V2 is enabled. 1457 1458Following functions are required only when LOAD\_IMAGE\_V2 is disabled. 1459 1460Function : bl2\_plat\_get\_scp\_bl2\_meminfo() [mandatory] 1461~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1462 1463:: 1464 1465 Argument : meminfo * 1466 Return : void 1467 1468This function is used to get the memory limits where BL2 can load the 1469SCP\_BL2 image. The meminfo provided by this is used by load\_image() to 1470validate whether the SCP\_BL2 image can be loaded within the given 1471memory from the given base. 1472 1473Function : bl2\_plat\_handle\_scp\_bl2() [mandatory] 1474~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1475 1476:: 1477 1478 Argument : image_info * 1479 Return : int 1480 1481This function is called after loading SCP\_BL2 image and it is used to perform 1482any platform-specific actions required to handle the SCP firmware. Typically it 1483transfers the image into SCP memory using a platform-specific protocol and waits 1484until SCP executes it and signals to the Application Processor (AP) for BL2 1485execution to continue. 1486 1487This function returns 0 on success, a negative error code otherwise. 1488 1489Function : bl2\_plat\_get\_bl31\_params() [mandatory] 1490~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1491 1492:: 1493 1494 Argument : void 1495 Return : bl31_params * 1496 1497BL2 platform code needs to return a pointer to a ``bl31_params`` structure it 1498will use for passing information to BL31. The ``bl31_params`` structure carries 1499the following information. 1500- Header describing the version information for interpreting the bl31\_param 1501structure 1502- Information about executing the BL33 image in the ``bl33_ep_info`` field 1503- Information about executing the BL32 image in the ``bl32_ep_info`` field 1504- Information about the type and extents of BL31 image in the 1505``bl31_image_info`` field 1506- Information about the type and extents of BL32 image in the 1507``bl32_image_info`` field 1508- Information about the type and extents of BL33 image in the 1509``bl33_image_info`` field 1510 1511The memory pointed by this structure and its sub-structures should be 1512accessible from BL31 initialisation code. BL31 might choose to copy the 1513necessary content, or maintain the structures until BL33 is initialised. 1514 1515Funtion : bl2\_plat\_get\_bl31\_ep\_info() [mandatory] 1516~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1517 1518:: 1519 1520 Argument : void 1521 Return : entry_point_info * 1522 1523BL2 platform code returns a pointer which is used to populate the entry point 1524information for BL31 entry point. The location pointed by it should be 1525accessible from BL1 while processing the synchronous exception to run to BL31. 1526 1527In Arm standard platforms this is allocated inside a bl2\_to\_bl31\_params\_mem 1528structure in BL2 memory. 1529 1530Function : bl2\_plat\_set\_bl31\_ep\_info() [mandatory] 1531~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1532 1533:: 1534 1535 Argument : image_info *, entry_point_info * 1536 Return : void 1537 1538In the normal boot flow, this function is called after loading BL31 image and 1539it can be used to overwrite the entry point set by loader and also set the 1540security state and SPSR which represents the entry point system state for BL31. 1541 1542When booting an EL3 payload instead, this function is called after populating 1543its entry point address and can be used for the same purpose for the payload 1544image. It receives a null pointer as its first argument in this case. 1545 1546Function : bl2\_plat\_set\_bl32\_ep\_info() [mandatory] 1547~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1548 1549:: 1550 1551 Argument : image_info *, entry_point_info * 1552 Return : void 1553 1554This function is called after loading BL32 image and it can be used to 1555overwrite the entry point set by loader and also set the security state 1556and SPSR which represents the entry point system state for BL32. 1557 1558Function : bl2\_plat\_set\_bl33\_ep\_info() [mandatory] 1559~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1560 1561:: 1562 1563 Argument : image_info *, entry_point_info * 1564 Return : void 1565 1566This function is called after loading BL33 image and it can be used to 1567overwrite the entry point set by loader and also set the security state 1568and SPSR which represents the entry point system state for BL33. 1569 1570In the preloaded BL33 alternative boot flow, this function is called after 1571populating its entry point address. It is passed a null pointer as its first 1572argument in this case. 1573 1574Function : bl2\_plat\_get\_bl32\_meminfo() [mandatory] 1575~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1576 1577:: 1578 1579 Argument : meminfo * 1580 Return : void 1581 1582This function is used to get the memory limits where BL2 can load the 1583BL32 image. The meminfo provided by this is used by load\_image() to 1584validate whether the BL32 image can be loaded with in the given 1585memory from the given base. 1586 1587Function : bl2\_plat\_get\_bl33\_meminfo() [mandatory] 1588~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1589 1590:: 1591 1592 Argument : meminfo * 1593 Return : void 1594 1595This function is used to get the memory limits where BL2 can load the 1596BL33 image. The meminfo provided by this is used by load\_image() to 1597validate whether the BL33 image can be loaded with in the given 1598memory from the given base. 1599 1600This function isn't needed if either ``PRELOADED_BL33_BASE`` or ``EL3_PAYLOAD_BASE`` 1601build options are used. 1602 1603Function : bl2\_plat\_flush\_bl31\_params() [mandatory] 1604~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1605 1606:: 1607 1608 Argument : void 1609 Return : void 1610 1611Once BL2 has populated all the structures that needs to be read by BL1 1612and BL31 including the bl31\_params structures and its sub-structures, 1613the bl31\_ep\_info structure and any platform specific data. It flushes 1614all these data to the main memory so that it is available when we jump to 1615later Bootloader stages with MMU off 1616 1617Function : plat\_get\_ns\_image\_entrypoint() [mandatory] 1618~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1619 1620:: 1621 1622 Argument : void 1623 Return : uintptr_t 1624 1625As previously described, BL2 is responsible for arranging for control to be 1626passed to a normal world BL image through BL31. This function returns the 1627entrypoint of that image, which BL31 uses to jump to it. 1628 1629BL2 is responsible for loading the normal world BL33 image (e.g. UEFI). 1630 1631This function isn't needed if either ``PRELOADED_BL33_BASE`` or ``EL3_PAYLOAD_BASE`` 1632build options are used. 1633 1634Function : bl2\_plat\_preload\_setup [optional] 1635~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1636 1637:: 1638 Argument : void 1639 Return : void 1640 1641This optional function performs any BL2 platform initialization 1642required before image loading, that is not done later in 1643bl2\_platform\_setup(). Specifically, if support for multiple 1644boot sources is required, it initializes the boot sequence used by 1645plat\_try\_next\_boot\_source(). 1646 1647Function : plat\_try\_next\_boot\_source() [optional] 1648~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1649 1650:: 1651 Argument : void 1652 Return : int 1653 1654This optional function passes to the next boot source in the redundancy 1655sequence. 1656 1657This function moves the current boot redundancy source to the next 1658element in the boot sequence. If there are no more boot sources then it 1659must return 0, otherwise it must return 1. The default implementation 1660of this always returns 0. 1661 1662Boot Loader Stage 2 (BL2) at EL3 1663-------------------------------- 1664 1665When the platform has a non-TF-A Boot ROM it is desirable to jump 1666directly to BL2 instead of TF-A BL1. In this case BL2 is expected to 1667execute at EL3 instead of executing at EL1. Refer to the `Firmware 1668Design`_ for more information. 1669 1670All mandatory functions of BL2 must be implemented, except the functions 1671bl2\_early\_platform\_setup and bl2\_el3\_plat\_arch\_setup, because 1672their work is done now by bl2\_el3\_early\_platform\_setup and 1673bl2\_el3\_plat\_arch\_setup. These functions should generally implement 1674the bl1\_plat\_xxx() and bl2\_plat\_xxx() functionality combined. 1675 1676 1677Function : bl2\_el3\_early\_platform\_setup() [mandatory] 1678~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1679 1680:: 1681 Argument : u_register_t, u_register_t, u_register_t, u_register_t 1682 Return : void 1683 1684This function executes with the MMU and data caches disabled. It is only called 1685by the primary CPU. This function receives four parameters which can be used 1686by the platform to pass any needed information from the Boot ROM to BL2. 1687 1688On Arm standard platforms, this function does the following: 1689 1690- Initializes a UART (PL011 console), which enables access to the ``printf`` 1691 family of functions in BL2. 1692 1693- Initializes the storage abstraction layer used to load further bootloader 1694 images. It is necessary to do this early on platforms with a SCP\_BL2 image, 1695 since the later ``bl2_platform_setup`` must be done after SCP\_BL2 is loaded. 1696 1697- Initializes the private variables that define the memory layout used. 1698 1699Function : bl2\_el3\_plat\_arch\_setup() [mandatory] 1700~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1701 1702:: 1703 Argument : void 1704 Return : void 1705 1706This function executes with the MMU and data caches disabled. It is only called 1707by the primary CPU. 1708 1709The purpose of this function is to perform any architectural initialization 1710that varies across platforms. 1711 1712On Arm standard platforms, this function enables the MMU. 1713 1714Function : bl2\_el3\_plat\_prepare\_exit() [optional] 1715~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1716 1717:: 1718 Argument : void 1719 Return : void 1720 1721This function is called prior to exiting BL2 and run the next image. 1722It should be used to perform platform specific clean up or bookkeeping 1723operations before transferring control to the next image. This function 1724runs with MMU disabled. 1725 1726FWU Boot Loader Stage 2 (BL2U) 1727------------------------------ 1728 1729The AP Firmware Updater Configuration, BL2U, is an optional part of the FWU 1730process and is executed only by the primary CPU. BL1 passes control to BL2U at 1731``BL2U_BASE``. BL2U executes in Secure-EL1 and is responsible for: 1732 1733#. (Optional) Transfering the optional SCP\_BL2U binary image from AP secure 1734 memory to SCP RAM. BL2U uses the SCP\_BL2U ``image_info`` passed by BL1. 1735 ``SCP_BL2U_BASE`` defines the address in AP secure memory where SCP\_BL2U 1736 should be copied from. Subsequent handling of the SCP\_BL2U image is 1737 implemented by the platform specific ``bl2u_plat_handle_scp_bl2u()`` function. 1738 If ``SCP_BL2U_BASE`` is not defined then this step is not performed. 1739 1740#. Any platform specific setup required to perform the FWU process. For 1741 example, Arm standard platforms initialize the TZC controller so that the 1742 normal world can access DDR memory. 1743 1744The following functions must be implemented by the platform port to enable 1745BL2U to perform the tasks mentioned above. 1746 1747Function : bl2u\_early\_platform\_setup() [mandatory] 1748~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1749 1750:: 1751 1752 Argument : meminfo *mem_info, void *plat_info 1753 Return : void 1754 1755This function executes with the MMU and data caches disabled. It is only 1756called by the primary CPU. The arguments to this function is the address 1757of the ``meminfo`` structure and platform specific info provided by BL1. 1758 1759The platform may copy the contents of the ``mem_info`` and ``plat_info`` into 1760private storage as the original memory may be subsequently overwritten by BL2U. 1761 1762On Arm CSS platforms ``plat_info`` is interpreted as an ``image_info_t`` structure, 1763to extract SCP\_BL2U image information, which is then copied into a private 1764variable. 1765 1766Function : bl2u\_plat\_arch\_setup() [mandatory] 1767~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1768 1769:: 1770 1771 Argument : void 1772 Return : void 1773 1774This function executes with the MMU and data caches disabled. It is only 1775called by the primary CPU. 1776 1777The purpose of this function is to perform any architectural initialization 1778that varies across platforms, for example enabling the MMU (since the memory 1779map differs across platforms). 1780 1781Function : bl2u\_platform\_setup() [mandatory] 1782~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1783 1784:: 1785 1786 Argument : void 1787 Return : void 1788 1789This function may execute with the MMU and data caches enabled if the platform 1790port does the necessary initialization in ``bl2u_plat_arch_setup()``. It is only 1791called by the primary CPU. 1792 1793The purpose of this function is to perform any platform initialization 1794specific to BL2U. 1795 1796In Arm standard platforms, this function performs security setup, including 1797configuration of the TrustZone controller to allow non-secure masters access 1798to most of DRAM. Part of DRAM is reserved for secure world use. 1799 1800Function : bl2u\_plat\_handle\_scp\_bl2u() [optional] 1801~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1802 1803:: 1804 1805 Argument : void 1806 Return : int 1807 1808This function is used to perform any platform-specific actions required to 1809handle the SCP firmware. Typically it transfers the image into SCP memory using 1810a platform-specific protocol and waits until SCP executes it and signals to the 1811Application Processor (AP) for BL2U execution to continue. 1812 1813This function returns 0 on success, a negative error code otherwise. 1814This function is included if SCP\_BL2U\_BASE is defined. 1815 1816Boot Loader Stage 3-1 (BL31) 1817---------------------------- 1818 1819During cold boot, the BL31 stage is executed only by the primary CPU. This is 1820determined in BL1 using the ``platform_is_primary_cpu()`` function. BL1 passes 1821control to BL31 at ``BL31_BASE``. During warm boot, BL31 is executed by all 1822CPUs. BL31 executes at EL3 and is responsible for: 1823 1824#. Re-initializing all architectural and platform state. Although BL1 performs 1825 some of this initialization, BL31 remains resident in EL3 and must ensure 1826 that EL3 architectural and platform state is completely initialized. It 1827 should make no assumptions about the system state when it receives control. 1828 1829#. Passing control to a normal world BL image, pre-loaded at a platform- 1830 specific address by BL2. BL31 uses the ``entry_point_info`` structure that BL2 1831 populated in memory to do this. 1832 1833#. Providing runtime firmware services. Currently, BL31 only implements a 1834 subset of the Power State Coordination Interface (PSCI) API as a runtime 1835 service. See Section 3.3 below for details of porting the PSCI 1836 implementation. 1837 1838#. Optionally passing control to the BL32 image, pre-loaded at a platform- 1839 specific address by BL2. BL31 exports a set of apis that allow runtime 1840 services to specify the security state in which the next image should be 1841 executed and run the corresponding image. BL31 uses the ``entry_point_info`` 1842 structure populated by BL2 to do this. 1843 1844If BL31 is a reset vector, It also needs to handle the reset as specified in 1845section 2.2 before the tasks described above. 1846 1847The following functions must be implemented by the platform port to enable BL31 1848to perform the above tasks. 1849 1850Function : bl31\_early\_platform\_setup() [mandatory] 1851~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1852 1853:: 1854 1855 Argument : bl31_params *, void * 1856 Return : void 1857 1858This function executes with the MMU and data caches disabled. It is only called 1859by the primary CPU. The arguments to this function are: 1860 1861- The address of the ``bl31_params`` structure populated by BL2. 1862- An opaque pointer that the platform may use as needed. 1863 1864The platform can copy the contents of the ``bl31_params`` structure and its 1865sub-structures into private variables if the original memory may be 1866subsequently overwritten by BL31 and similarly the ``void *`` pointing 1867to the platform data also needs to be saved. 1868 1869In Arm standard platforms, BL2 passes a pointer to a ``bl31_params`` structure 1870in BL2 memory. BL31 copies the information in this pointer to internal data 1871structures. It also performs the following: 1872 1873- Initialize a UART (PL011 console), which enables access to the ``printf`` 1874 family of functions in BL31. 1875 1876- Enable issuing of snoop and DVM (Distributed Virtual Memory) requests to the 1877 CCI slave interface corresponding to the cluster that includes the primary 1878 CPU. 1879 1880Function : bl31\_plat\_arch\_setup() [mandatory] 1881~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1882 1883:: 1884 1885 Argument : void 1886 Return : void 1887 1888This function executes with the MMU and data caches disabled. It is only called 1889by the primary CPU. 1890 1891The purpose of this function is to perform any architectural initialization 1892that varies across platforms. 1893 1894On Arm standard platforms, this function enables the MMU. 1895 1896Function : bl31\_platform\_setup() [mandatory] 1897~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1898 1899:: 1900 1901 Argument : void 1902 Return : void 1903 1904This function may execute with the MMU and data caches enabled if the platform 1905port does the necessary initialization in ``bl31_plat_arch_setup()``. It is only 1906called by the primary CPU. 1907 1908The purpose of this function is to complete platform initialization so that both 1909BL31 runtime services and normal world software can function correctly. 1910 1911On Arm standard platforms, this function does the following: 1912 1913- Initialize the generic interrupt controller. 1914 1915 Depending on the GIC driver selected by the platform, the appropriate GICv2 1916 or GICv3 initialization will be done, which mainly consists of: 1917 1918 - Enable secure interrupts in the GIC CPU interface. 1919 - Disable the legacy interrupt bypass mechanism. 1920 - Configure the priority mask register to allow interrupts of all priorities 1921 to be signaled to the CPU interface. 1922 - Mark SGIs 8-15 and the other secure interrupts on the platform as secure. 1923 - Target all secure SPIs to CPU0. 1924 - Enable these secure interrupts in the GIC distributor. 1925 - Configure all other interrupts as non-secure. 1926 - Enable signaling of secure interrupts in the GIC distributor. 1927 1928- Enable system-level implementation of the generic timer counter through the 1929 memory mapped interface. 1930 1931- Grant access to the system counter timer module 1932 1933- Initialize the power controller device. 1934 1935 In particular, initialise the locks that prevent concurrent accesses to the 1936 power controller device. 1937 1938Function : bl31\_plat\_runtime\_setup() [optional] 1939~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1940 1941:: 1942 1943 Argument : void 1944 Return : void 1945 1946The purpose of this function is allow the platform to perform any BL31 runtime 1947setup just prior to BL31 exit during cold boot. The default weak 1948implementation of this function will invoke ``console_switch_state()`` to switch 1949console output to consoles marked for use in the ``runtime`` state. 1950 1951Function : bl31\_get\_next\_image\_info() [mandatory] 1952~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1953 1954:: 1955 1956 Argument : unsigned int 1957 Return : entry_point_info * 1958 1959This function may execute with the MMU and data caches enabled if the platform 1960port does the necessary initializations in ``bl31_plat_arch_setup()``. 1961 1962This function is called by ``bl31_main()`` to retrieve information provided by 1963BL2 for the next image in the security state specified by the argument. BL31 1964uses this information to pass control to that image in the specified security 1965state. This function must return a pointer to the ``entry_point_info`` structure 1966(that was copied during ``bl31_early_platform_setup()``) if the image exists. It 1967should return NULL otherwise. 1968 1969Function : plat\_get\_syscnt\_freq2() [mandatory] 1970~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1971 1972:: 1973 1974 Argument : void 1975 Return : unsigned int 1976 1977This function is used by the architecture setup code to retrieve the counter 1978frequency for the CPU's generic timer. This value will be programmed into the 1979``CNTFRQ_EL0`` register. In Arm standard platforms, it returns the base frequency 1980of the system counter, which is retrieved from the first entry in the frequency 1981modes table. 1982 1983#define : PLAT\_PERCPU\_BAKERY\_LOCK\_SIZE [optional] 1984~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1985 1986When ``USE_COHERENT_MEM = 0``, this constant defines the total memory (in 1987bytes) aligned to the cache line boundary that should be allocated per-cpu to 1988accommodate all the bakery locks. 1989 1990If this constant is not defined when ``USE_COHERENT_MEM = 0``, the linker 1991calculates the size of the ``bakery_lock`` input section, aligns it to the 1992nearest ``CACHE_WRITEBACK_GRANULE``, multiplies it with ``PLATFORM_CORE_COUNT`` 1993and stores the result in a linker symbol. This constant prevents a platform 1994from relying on the linker and provide a more efficient mechanism for 1995accessing per-cpu bakery lock information. 1996 1997If this constant is defined and its value is not equal to the value 1998calculated by the linker then a link time assertion is raised. A compile time 1999assertion is raised if the value of the constant is not aligned to the cache 2000line boundary. 2001 2002SDEI porting requirements 2003~~~~~~~~~~~~~~~~~~~~~~~~~ 2004 2005The SDEI dispatcher requires the platform to provide the following macros 2006and functions, of which some are optional, and some others mandatory. 2007 2008Macros 2009...... 2010 2011Macro: PLAT_SDEI_NORMAL_PRI [mandatory] 2012^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2013 2014This macro must be defined to the EL3 exception priority level associated with 2015Normal SDEI events on the platform. This must have a higher value (therefore of 2016lower priority) than ``PLAT_SDEI_CRITICAL_PRI``. 2017 2018Macro: PLAT_SDEI_CRITICAL_PRI [mandatory] 2019^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2020 2021This macro must be defined to the EL3 exception priority level associated with 2022Critical SDEI events on the platform. This must have a lower value (therefore of 2023higher priority) than ``PLAT_SDEI_NORMAL_PRI``. 2024 2025**Note**: SDEI exception priorities must be the lowest among Secure priorities. 2026Among the SDEI exceptions, Critical SDEI priority must be higher than Normal 2027SDEI priority. 2028 2029Functions 2030......... 2031 2032Function: int plat_sdei_validate_entry_point(uintptr_t ep) [optional] 2033^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2034 2035:: 2036 2037 Argument: uintptr_t 2038 Return: int 2039 2040This function validates the address of client entry points provided for both 2041event registration and *Complete and Resume* SDEI calls. The function takes one 2042argument, which is the address of the handler the SDEI client requested to 2043register. The function must return ``0`` for successful validation, or ``-1`` 2044upon failure. 2045 2046The default implementation always returns ``0``. On Arm platforms, this function 2047is implemented to translate the entry point to physical address, and further to 2048ensure that the address is located in Non-secure DRAM. 2049 2050Function: void plat_sdei_handle_masked_trigger(uint64_t mpidr, unsigned int intr) [optional] 2051^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2052 2053:: 2054 2055 Argument: uint64_t 2056 Argument: unsigned int 2057 Return: void 2058 2059SDEI specification requires that a PE comes out of reset with the events masked. 2060The client therefore is expected to call ``PE_UNMASK`` to unmask SDEI events on 2061the PE. No SDEI events can be dispatched until such time. 2062 2063Should a PE receive an interrupt that was bound to an SDEI event while the 2064events are masked on the PE, the dispatcher implementation invokes the function 2065``plat_sdei_handle_masked_trigger``. The MPIDR of the PE that received the 2066interrupt and the interrupt ID are passed as parameters. 2067 2068The default implementation only prints out a warning message. 2069 2070Power State Coordination Interface (in BL31) 2071-------------------------------------------- 2072 2073The TF-A implementation of the PSCI API is based around the concept of a 2074*power domain*. A *power domain* is a CPU or a logical group of CPUs which 2075share some state on which power management operations can be performed as 2076specified by `PSCI`_. Each CPU in the system is assigned a cpu index which is 2077a unique number between ``0`` and ``PLATFORM_CORE_COUNT - 1``. The 2078*power domains* are arranged in a hierarchical tree structure and each 2079*power domain* can be identified in a system by the cpu index of any CPU that 2080is part of that domain and a *power domain level*. A processing element (for 2081example, a CPU) is at level 0. If the *power domain* node above a CPU is a 2082logical grouping of CPUs that share some state, then level 1 is that group of 2083CPUs (for example, a cluster), and level 2 is a group of clusters (for 2084example, the system). More details on the power domain topology and its 2085organization can be found in `Power Domain Topology Design`_. 2086 2087BL31's platform initialization code exports a pointer to the platform-specific 2088power management operations required for the PSCI implementation to function 2089correctly. This information is populated in the ``plat_psci_ops`` structure. The 2090PSCI implementation calls members of the ``plat_psci_ops`` structure for performing 2091power management operations on the power domains. For example, the target 2092CPU is specified by its ``MPIDR`` in a PSCI ``CPU_ON`` call. The ``pwr_domain_on()`` 2093handler (if present) is called for the CPU power domain. 2094 2095The ``power-state`` parameter of a PSCI ``CPU_SUSPEND`` call can be used to 2096describe composite power states specific to a platform. The PSCI implementation 2097defines a generic representation of the power-state parameter viz which is an 2098array of local power states where each index corresponds to a power domain 2099level. Each entry contains the local power state the power domain at that power 2100level could enter. It depends on the ``validate_power_state()`` handler to 2101convert the power-state parameter (possibly encoding a composite power state) 2102passed in a PSCI ``CPU_SUSPEND`` call to this representation. 2103 2104The following functions form part of platform port of PSCI functionality. 2105 2106Function : plat\_psci\_stat\_accounting\_start() [optional] 2107~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2108 2109:: 2110 2111 Argument : const psci_power_state_t * 2112 Return : void 2113 2114This is an optional hook that platforms can implement for residency statistics 2115accounting before entering a low power state. The ``pwr_domain_state`` field of 2116``state_info`` (first argument) can be inspected if stat accounting is done 2117differently at CPU level versus higher levels. As an example, if the element at 2118index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down 2119state, special hardware logic may be programmed in order to keep track of the 2120residency statistics. For higher levels (array indices > 0), the residency 2121statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the 2122default implementation will use PMF to capture timestamps. 2123 2124Function : plat\_psci\_stat\_accounting\_stop() [optional] 2125~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2126 2127:: 2128 2129 Argument : const psci_power_state_t * 2130 Return : void 2131 2132This is an optional hook that platforms can implement for residency statistics 2133accounting after exiting from a low power state. The ``pwr_domain_state`` field 2134of ``state_info`` (first argument) can be inspected if stat accounting is done 2135differently at CPU level versus higher levels. As an example, if the element at 2136index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down 2137state, special hardware logic may be programmed in order to keep track of the 2138residency statistics. For higher levels (array indices > 0), the residency 2139statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the 2140default implementation will use PMF to capture timestamps. 2141 2142Function : plat\_psci\_stat\_get\_residency() [optional] 2143~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2144 2145:: 2146 2147 Argument : unsigned int, const psci_power_state_t *, int 2148 Return : u_register_t 2149 2150This is an optional interface that is is invoked after resuming from a low power 2151state and provides the time spent resident in that low power state by the power 2152domain at a particular power domain level. When a CPU wakes up from suspend, 2153all its parent power domain levels are also woken up. The generic PSCI code 2154invokes this function for each parent power domain that is resumed and it 2155identified by the ``lvl`` (first argument) parameter. The ``state_info`` (second 2156argument) describes the low power state that the power domain has resumed from. 2157The current CPU is the first CPU in the power domain to resume from the low 2158power state and the ``last_cpu_idx`` (third parameter) is the index of the last 2159CPU in the power domain to suspend and may be needed to calculate the residency 2160for that power domain. 2161 2162Function : plat\_get\_target\_pwr\_state() [optional] 2163~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2164 2165:: 2166 2167 Argument : unsigned int, const plat_local_state_t *, unsigned int 2168 Return : plat_local_state_t 2169 2170The PSCI generic code uses this function to let the platform participate in 2171state coordination during a power management operation. The function is passed 2172a pointer to an array of platform specific local power state ``states`` (second 2173argument) which contains the requested power state for each CPU at a particular 2174power domain level ``lvl`` (first argument) within the power domain. The function 2175is expected to traverse this array of upto ``ncpus`` (third argument) and return 2176a coordinated target power state by the comparing all the requested power 2177states. The target power state should not be deeper than any of the requested 2178power states. 2179 2180A weak definition of this API is provided by default wherein it assumes 2181that the platform assigns a local state value in order of increasing depth 2182of the power state i.e. for two power states X & Y, if X < Y 2183then X represents a shallower power state than Y. As a result, the 2184coordinated target local power state for a power domain will be the minimum 2185of the requested local power state values. 2186 2187Function : plat\_get\_power\_domain\_tree\_desc() [mandatory] 2188~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2189 2190:: 2191 2192 Argument : void 2193 Return : const unsigned char * 2194 2195This function returns a pointer to the byte array containing the power domain 2196topology tree description. The format and method to construct this array are 2197described in `Power Domain Topology Design`_. The BL31 PSCI initilization code 2198requires this array to be described by the platform, either statically or 2199dynamically, to initialize the power domain topology tree. In case the array 2200is populated dynamically, then plat\_core\_pos\_by\_mpidr() and 2201plat\_my\_core\_pos() should also be implemented suitably so that the topology 2202tree description matches the CPU indices returned by these APIs. These APIs 2203together form the platform interface for the PSCI topology framework. 2204 2205Function : plat\_setup\_psci\_ops() [mandatory] 2206~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2207 2208:: 2209 2210 Argument : uintptr_t, const plat_psci_ops ** 2211 Return : int 2212 2213This function may execute with the MMU and data caches enabled if the platform 2214port does the necessary initializations in ``bl31_plat_arch_setup()``. It is only 2215called by the primary CPU. 2216 2217This function is called by PSCI initialization code. Its purpose is to let 2218the platform layer know about the warm boot entrypoint through the 2219``sec_entrypoint`` (first argument) and to export handler routines for 2220platform-specific psci power management actions by populating the passed 2221pointer with a pointer to BL31's private ``plat_psci_ops`` structure. 2222 2223A description of each member of this structure is given below. Please refer to 2224the Arm FVP specific implementation of these handlers in 2225`plat/arm/board/fvp/fvp\_pm.c`_ as an example. For each PSCI function that the 2226platform wants to support, the associated operation or operations in this 2227structure must be provided and implemented (Refer section 4 of 2228`Firmware Design`_ for the PSCI API supported in TF-A). To disable a PSCI 2229function in a platform port, the operation should be removed from this 2230structure instead of providing an empty implementation. 2231 2232plat\_psci\_ops.cpu\_standby() 2233.............................. 2234 2235Perform the platform-specific actions to enter the standby state for a cpu 2236indicated by the passed argument. This provides a fast path for CPU standby 2237wherein overheads of PSCI state management and lock acquistion is avoided. 2238For this handler to be invoked by the PSCI ``CPU_SUSPEND`` API implementation, 2239the suspend state type specified in the ``power-state`` parameter should be 2240STANDBY and the target power domain level specified should be the CPU. The 2241handler should put the CPU into a low power retention state (usually by 2242issuing a wfi instruction) and ensure that it can be woken up from that 2243state by a normal interrupt. The generic code expects the handler to succeed. 2244 2245plat\_psci\_ops.pwr\_domain\_on() 2246................................. 2247 2248Perform the platform specific actions to power on a CPU, specified 2249by the ``MPIDR`` (first argument). The generic code expects the platform to 2250return PSCI\_E\_SUCCESS on success or PSCI\_E\_INTERN\_FAIL for any failure. 2251 2252plat\_psci\_ops.pwr\_domain\_off() 2253.................................. 2254 2255Perform the platform specific actions to prepare to power off the calling CPU 2256and its higher parent power domain levels as indicated by the ``target_state`` 2257(first argument). It is called by the PSCI ``CPU_OFF`` API implementation. 2258 2259The ``target_state`` encodes the platform coordinated target local power states 2260for the CPU power domain and its parent power domain levels. The handler 2261needs to perform power management operation corresponding to the local state 2262at each power level. 2263 2264For this handler, the local power state for the CPU power domain will be a 2265power down state where as it could be either power down, retention or run state 2266for the higher power domain levels depending on the result of state 2267coordination. The generic code expects the handler to succeed. 2268 2269plat\_psci\_ops.pwr\_domain\_suspend\_pwrdown\_early() [optional] 2270................................................................. 2271 2272This optional function may be used as a performance optimization to replace 2273or complement pwr_domain_suspend() on some platforms. Its calling semantics 2274are identical to pwr_domain_suspend(), except the PSCI implementation only 2275calls this function when suspending to a power down state, and it guarantees 2276that data caches are enabled. 2277 2278When HW_ASSISTED_COHERENCY = 0, the PSCI implementation disables data caches 2279before calling pwr_domain_suspend(). If the target_state corresponds to a 2280power down state and it is safe to perform some or all of the platform 2281specific actions in that function with data caches enabled, it may be more 2282efficient to move those actions to this function. When HW_ASSISTED_COHERENCY 2283= 1, data caches remain enabled throughout, and so there is no advantage to 2284moving platform specific actions to this function. 2285 2286plat\_psci\_ops.pwr\_domain\_suspend() 2287...................................... 2288 2289Perform the platform specific actions to prepare to suspend the calling 2290CPU and its higher parent power domain levels as indicated by the 2291``target_state`` (first argument). It is called by the PSCI ``CPU_SUSPEND`` 2292API implementation. 2293 2294The ``target_state`` has a similar meaning as described in 2295the ``pwr_domain_off()`` operation. It encodes the platform coordinated 2296target local power states for the CPU power domain and its parent 2297power domain levels. The handler needs to perform power management operation 2298corresponding to the local state at each power level. The generic code 2299expects the handler to succeed. 2300 2301The difference between turning a power domain off versus suspending it is that 2302in the former case, the power domain is expected to re-initialize its state 2303when it is next powered on (see ``pwr_domain_on_finish()``). In the latter 2304case, the power domain is expected to save enough state so that it can resume 2305execution by restoring this state when its powered on (see 2306``pwr_domain_suspend_finish()``). 2307 2308When suspending a core, the platform can also choose to power off the GICv3 2309Redistributor and ITS through an implementation-defined sequence. To achieve 2310this safely, the ITS context must be saved first. The architectural part is 2311implemented by the ``gicv3_its_save_disable()`` helper, but most of the needed 2312sequence is implementation defined and it is therefore the responsibility of 2313the platform code to implement the necessary sequence. Then the GIC 2314Redistributor context can be saved using the ``gicv3_rdistif_save()`` helper. 2315Powering off the Redistributor requires the implementation to support it and it 2316is the responsibility of the platform code to execute the right implementation 2317defined sequence. 2318 2319When a system suspend is requested, the platform can also make use of the 2320``gicv3_distif_save()`` helper to save the context of the GIC Distributor after 2321it has saved the context of the Redistributors and ITS of all the cores in the 2322system. The context of the Distributor can be large and may require it to be 2323allocated in a special area if it cannot fit in the platform's global static 2324data, for example in DRAM. The Distributor can then be powered down using an 2325implementation-defined sequence. 2326 2327plat\_psci\_ops.pwr\_domain\_pwr\_down\_wfi() 2328............................................. 2329 2330This is an optional function and, if implemented, is expected to perform 2331platform specific actions including the ``wfi`` invocation which allows the 2332CPU to powerdown. Since this function is invoked outside the PSCI locks, 2333the actions performed in this hook must be local to the CPU or the platform 2334must ensure that races between multiple CPUs cannot occur. 2335 2336The ``target_state`` has a similar meaning as described in the ``pwr_domain_off()`` 2337operation and it encodes the platform coordinated target local power states for 2338the CPU power domain and its parent power domain levels. This function must 2339not return back to the caller. 2340 2341If this function is not implemented by the platform, PSCI generic 2342implementation invokes ``psci_power_down_wfi()`` for power down. 2343 2344plat\_psci\_ops.pwr\_domain\_on\_finish() 2345......................................... 2346 2347This function is called by the PSCI implementation after the calling CPU is 2348powered on and released from reset in response to an earlier PSCI ``CPU_ON`` call. 2349It performs the platform-specific setup required to initialize enough state for 2350this CPU to enter the normal world and also provide secure runtime firmware 2351services. 2352 2353The ``target_state`` (first argument) is the prior state of the power domains 2354immediately before the CPU was turned on. It indicates which power domains 2355above the CPU might require initialization due to having previously been in 2356low power states. The generic code expects the handler to succeed. 2357 2358plat\_psci\_ops.pwr\_domain\_suspend\_finish() 2359.............................................. 2360 2361This function is called by the PSCI implementation after the calling CPU is 2362powered on and released from reset in response to an asynchronous wakeup 2363event, for example a timer interrupt that was programmed by the CPU during the 2364``CPU_SUSPEND`` call or ``SYSTEM_SUSPEND`` call. It performs the platform-specific 2365setup required to restore the saved state for this CPU to resume execution 2366in the normal world and also provide secure runtime firmware services. 2367 2368The ``target_state`` (first argument) has a similar meaning as described in 2369the ``pwr_domain_on_finish()`` operation. The generic code expects the platform 2370to succeed. 2371 2372If the Distributor, Redistributors or ITS have been powered off as part of a 2373suspend, their context must be restored in this function in the reverse order 2374to how they were saved during suspend sequence. 2375 2376plat\_psci\_ops.system\_off() 2377............................. 2378 2379This function is called by PSCI implementation in response to a ``SYSTEM_OFF`` 2380call. It performs the platform-specific system poweroff sequence after 2381notifying the Secure Payload Dispatcher. 2382 2383plat\_psci\_ops.system\_reset() 2384............................... 2385 2386This function is called by PSCI implementation in response to a ``SYSTEM_RESET`` 2387call. It performs the platform-specific system reset sequence after 2388notifying the Secure Payload Dispatcher. 2389 2390plat\_psci\_ops.validate\_power\_state() 2391........................................ 2392 2393This function is called by the PSCI implementation during the ``CPU_SUSPEND`` 2394call to validate the ``power_state`` parameter of the PSCI API and if valid, 2395populate it in ``req_state`` (second argument) array as power domain level 2396specific local states. If the ``power_state`` is invalid, the platform must 2397return PSCI\_E\_INVALID\_PARAMS as error, which is propagated back to the 2398normal world PSCI client. 2399 2400plat\_psci\_ops.validate\_ns\_entrypoint() 2401.......................................... 2402 2403This function is called by the PSCI implementation during the ``CPU_SUSPEND``, 2404``SYSTEM_SUSPEND`` and ``CPU_ON`` calls to validate the non-secure ``entry_point`` 2405parameter passed by the normal world. If the ``entry_point`` is invalid, 2406the platform must return PSCI\_E\_INVALID\_ADDRESS as error, which is 2407propagated back to the normal world PSCI client. 2408 2409plat\_psci\_ops.get\_sys\_suspend\_power\_state() 2410................................................. 2411 2412This function is called by the PSCI implementation during the ``SYSTEM_SUSPEND`` 2413call to get the ``req_state`` parameter from platform which encodes the power 2414domain level specific local states to suspend to system affinity level. The 2415``req_state`` will be utilized to do the PSCI state coordination and 2416``pwr_domain_suspend()`` will be invoked with the coordinated target state to 2417enter system suspend. 2418 2419plat\_psci\_ops.get\_pwr\_lvl\_state\_idx() 2420........................................... 2421 2422This is an optional function and, if implemented, is invoked by the PSCI 2423implementation to convert the ``local_state`` (first argument) at a specified 2424``pwr_lvl`` (second argument) to an index between 0 and 2425``PLAT_MAX_PWR_LVL_STATES`` - 1. This function is only needed if the platform 2426supports more than two local power states at each power domain level, that is 2427``PLAT_MAX_PWR_LVL_STATES`` is greater than 2, and needs to account for these 2428local power states. 2429 2430plat\_psci\_ops.translate\_power\_state\_by\_mpidr() 2431.................................................... 2432 2433This is an optional function and, if implemented, verifies the ``power_state`` 2434(second argument) parameter of the PSCI API corresponding to a target power 2435domain. The target power domain is identified by using both ``MPIDR`` (first 2436argument) and the power domain level encoded in ``power_state``. The power domain 2437level specific local states are to be extracted from ``power_state`` and be 2438populated in the ``output_state`` (third argument) array. The functionality 2439is similar to the ``validate_power_state`` function described above and is 2440envisaged to be used in case the validity of ``power_state`` depend on the 2441targeted power domain. If the ``power_state`` is invalid for the targeted power 2442domain, the platform must return PSCI\_E\_INVALID\_PARAMS as error. If this 2443function is not implemented, then the generic implementation relies on 2444``validate_power_state`` function to translate the ``power_state``. 2445 2446This function can also be used in case the platform wants to support local 2447power state encoding for ``power_state`` parameter of PSCI\_STAT\_COUNT/RESIDENCY 2448APIs as described in Section 5.18 of `PSCI`_. 2449 2450plat\_psci\_ops.get\_node\_hw\_state() 2451...................................... 2452 2453This is an optional function. If implemented this function is intended to return 2454the power state of a node (identified by the first parameter, the ``MPIDR``) in 2455the power domain topology (identified by the second parameter, ``power_level``), 2456as retrieved from a power controller or equivalent component on the platform. 2457Upon successful completion, the implementation must map and return the final 2458status among ``HW_ON``, ``HW_OFF`` or ``HW_STANDBY``. Upon encountering failures, it 2459must return either ``PSCI_E_INVALID_PARAMS`` or ``PSCI_E_NOT_SUPPORTED`` as 2460appropriate. 2461 2462Implementations are not expected to handle ``power_levels`` greater than 2463``PLAT_MAX_PWR_LVL``. 2464 2465plat\_psci\_ops.system\_reset2() 2466................................ 2467 2468This is an optional function. If implemented this function is 2469called during the ``SYSTEM_RESET2`` call to perform a reset 2470based on the first parameter ``reset_type`` as specified in 2471`PSCI`_. The parameter ``cookie`` can be used to pass additional 2472reset information. If the ``reset_type`` is not supported, the 2473function must return ``PSCI_E_NOT_SUPPORTED``. For architectural 2474resets, all failures must return ``PSCI_E_INVALID_PARAMETERS`` 2475and vendor reset can return other PSCI error codes as defined 2476in `PSCI`_. On success this function will not return. 2477 2478plat\_psci\_ops.write\_mem\_protect() 2479.................................... 2480 2481This is an optional function. If implemented it enables or disables the 2482``MEM_PROTECT`` functionality based on the value of ``val``. 2483A non-zero value enables ``MEM_PROTECT`` and a value of zero 2484disables it. Upon encountering failures it must return a negative value 2485and on success it must return 0. 2486 2487plat\_psci\_ops.read\_mem\_protect() 2488..................................... 2489 2490This is an optional function. If implemented it returns the current 2491state of ``MEM_PROTECT`` via the ``val`` parameter. Upon encountering 2492failures it must return a negative value and on success it must 2493return 0. 2494 2495plat\_psci\_ops.mem\_protect\_chk() 2496................................... 2497 2498This is an optional function. If implemented it checks if a memory 2499region defined by a base address ``base`` and with a size of ``length`` 2500bytes is protected by ``MEM_PROTECT``. If the region is protected 2501then it must return 0, otherwise it must return a negative number. 2502 2503Interrupt Management framework (in BL31) 2504---------------------------------------- 2505 2506BL31 implements an Interrupt Management Framework (IMF) to manage interrupts 2507generated in either security state and targeted to EL1 or EL2 in the non-secure 2508state or EL3/S-EL1 in the secure state. The design of this framework is 2509described in the `IMF Design Guide`_ 2510 2511A platform should export the following APIs to support the IMF. The following 2512text briefly describes each api and its implementation in Arm standard 2513platforms. The API implementation depends upon the type of interrupt controller 2514present in the platform. Arm standard platform layer supports both 2515`Arm Generic Interrupt Controller version 2.0 (GICv2)`_ 2516and `3.0 (GICv3)`_. Juno builds the Arm platform layer to use GICv2 and the 2517FVP can be configured to use either GICv2 or GICv3 depending on the build flag 2518``FVP_USE_GIC_DRIVER`` (See FVP platform specific build options in 2519`User Guide`_ for more details). 2520 2521See also: `Interrupt Controller Abstraction APIs`__. 2522 2523.. __: platform-interrupt-controller-API.rst 2524 2525Function : plat\_interrupt\_type\_to\_line() [mandatory] 2526~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2527 2528:: 2529 2530 Argument : uint32_t, uint32_t 2531 Return : uint32_t 2532 2533The Arm processor signals an interrupt exception either through the IRQ or FIQ 2534interrupt line. The specific line that is signaled depends on how the interrupt 2535controller (IC) reports different interrupt types from an execution context in 2536either security state. The IMF uses this API to determine which interrupt line 2537the platform IC uses to signal each type of interrupt supported by the framework 2538from a given security state. This API must be invoked at EL3. 2539 2540The first parameter will be one of the ``INTR_TYPE_*`` values (see 2541`IMF Design Guide`_) indicating the target type of the interrupt, the second parameter is the 2542security state of the originating execution context. The return result is the 2543bit position in the ``SCR_EL3`` register of the respective interrupt trap: IRQ=1, 2544FIQ=2. 2545 2546In the case of Arm standard platforms using GICv2, S-EL1 interrupts are 2547configured as FIQs and Non-secure interrupts as IRQs from either security 2548state. 2549 2550In the case of Arm standard platforms using GICv3, the interrupt line to be 2551configured depends on the security state of the execution context when the 2552interrupt is signalled and are as follows: 2553 2554- The S-EL1 interrupts are signaled as IRQ in S-EL0/1 context and as FIQ in 2555 NS-EL0/1/2 context. 2556- The Non secure interrupts are signaled as FIQ in S-EL0/1 context and as IRQ 2557 in the NS-EL0/1/2 context. 2558- The EL3 interrupts are signaled as FIQ in both S-EL0/1 and NS-EL0/1/2 2559 context. 2560 2561Function : plat\_ic\_get\_pending\_interrupt\_type() [mandatory] 2562~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2563 2564:: 2565 2566 Argument : void 2567 Return : uint32_t 2568 2569This API returns the type of the highest priority pending interrupt at the 2570platform IC. The IMF uses the interrupt type to retrieve the corresponding 2571handler function. ``INTR_TYPE_INVAL`` is returned when there is no interrupt 2572pending. The valid interrupt types that can be returned are ``INTR_TYPE_EL3``, 2573``INTR_TYPE_S_EL1`` and ``INTR_TYPE_NS``. This API must be invoked at EL3. 2574 2575In the case of Arm standard platforms using GICv2, the *Highest Priority 2576Pending Interrupt Register* (``GICC_HPPIR``) is read to determine the id of 2577the pending interrupt. The type of interrupt depends upon the id value as 2578follows. 2579 2580#. id < 1022 is reported as a S-EL1 interrupt 2581#. id = 1022 is reported as a Non-secure interrupt. 2582#. id = 1023 is reported as an invalid interrupt type. 2583 2584In the case of Arm standard platforms using GICv3, the system register 2585``ICC_HPPIR0_EL1``, *Highest Priority Pending group 0 Interrupt Register*, 2586is read to determine the id of the pending interrupt. The type of interrupt 2587depends upon the id value as follows. 2588 2589#. id = ``PENDING_G1S_INTID`` (1020) is reported as a S-EL1 interrupt 2590#. id = ``PENDING_G1NS_INTID`` (1021) is reported as a Non-secure interrupt. 2591#. id = ``GIC_SPURIOUS_INTERRUPT`` (1023) is reported as an invalid interrupt type. 2592#. All other interrupt id's are reported as EL3 interrupt. 2593 2594Function : plat\_ic\_get\_pending\_interrupt\_id() [mandatory] 2595~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2596 2597:: 2598 2599 Argument : void 2600 Return : uint32_t 2601 2602This API returns the id of the highest priority pending interrupt at the 2603platform IC. ``INTR_ID_UNAVAILABLE`` is returned when there is no interrupt 2604pending. 2605 2606In the case of Arm standard platforms using GICv2, the *Highest Priority 2607Pending Interrupt Register* (``GICC_HPPIR``) is read to determine the id of the 2608pending interrupt. The id that is returned by API depends upon the value of 2609the id read from the interrupt controller as follows. 2610 2611#. id < 1022. id is returned as is. 2612#. id = 1022. The *Aliased Highest Priority Pending Interrupt Register* 2613 (``GICC_AHPPIR``) is read to determine the id of the non-secure interrupt. 2614 This id is returned by the API. 2615#. id = 1023. ``INTR_ID_UNAVAILABLE`` is returned. 2616 2617In the case of Arm standard platforms using GICv3, if the API is invoked from 2618EL3, the system register ``ICC_HPPIR0_EL1``, *Highest Priority Pending Interrupt 2619group 0 Register*, is read to determine the id of the pending interrupt. The id 2620that is returned by API depends upon the value of the id read from the 2621interrupt controller as follows. 2622 2623#. id < ``PENDING_G1S_INTID`` (1020). id is returned as is. 2624#. id = ``PENDING_G1S_INTID`` (1020) or ``PENDING_G1NS_INTID`` (1021). The system 2625 register ``ICC_HPPIR1_EL1``, *Highest Priority Pending Interrupt group 1 2626 Register* is read to determine the id of the group 1 interrupt. This id 2627 is returned by the API as long as it is a valid interrupt id 2628#. If the id is any of the special interrupt identifiers, 2629 ``INTR_ID_UNAVAILABLE`` is returned. 2630 2631When the API invoked from S-EL1 for GICv3 systems, the id read from system 2632register ``ICC_HPPIR1_EL1``, *Highest Priority Pending group 1 Interrupt 2633Register*, is returned if is not equal to GIC\_SPURIOUS\_INTERRUPT (1023) else 2634``INTR_ID_UNAVAILABLE`` is returned. 2635 2636Function : plat\_ic\_acknowledge\_interrupt() [mandatory] 2637~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2638 2639:: 2640 2641 Argument : void 2642 Return : uint32_t 2643 2644This API is used by the CPU to indicate to the platform IC that processing of 2645the highest pending interrupt has begun. It should return the raw, unmodified 2646value obtained from the interrupt controller when acknowledging an interrupt. 2647The actual interrupt number shall be extracted from this raw value using the API 2648`plat_ic_get_interrupt_id()`__. 2649 2650.. __: platform-interrupt-controller-API.rst#function-unsigned-int-plat-ic-get-interrupt-id-unsigned-int-raw-optional 2651 2652This function in Arm standard platforms using GICv2, reads the *Interrupt 2653Acknowledge Register* (``GICC_IAR``). This changes the state of the highest 2654priority pending interrupt from pending to active in the interrupt controller. 2655It returns the value read from the ``GICC_IAR``, unmodified. 2656 2657In the case of Arm standard platforms using GICv3, if the API is invoked 2658from EL3, the function reads the system register ``ICC_IAR0_EL1``, *Interrupt 2659Acknowledge Register group 0*. If the API is invoked from S-EL1, the function 2660reads the system register ``ICC_IAR1_EL1``, *Interrupt Acknowledge Register 2661group 1*. The read changes the state of the highest pending interrupt from 2662pending to active in the interrupt controller. The value read is returned 2663unmodified. 2664 2665The TSP uses this API to start processing of the secure physical timer 2666interrupt. 2667 2668Function : plat\_ic\_end\_of\_interrupt() [mandatory] 2669~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2670 2671:: 2672 2673 Argument : uint32_t 2674 Return : void 2675 2676This API is used by the CPU to indicate to the platform IC that processing of 2677the interrupt corresponding to the id (passed as the parameter) has 2678finished. The id should be the same as the id returned by the 2679``plat_ic_acknowledge_interrupt()`` API. 2680 2681Arm standard platforms write the id to the *End of Interrupt Register* 2682(``GICC_EOIR``) in case of GICv2, and to ``ICC_EOIR0_EL1`` or ``ICC_EOIR1_EL1`` 2683system register in case of GICv3 depending on where the API is invoked from, 2684EL3 or S-EL1. This deactivates the corresponding interrupt in the interrupt 2685controller. 2686 2687The TSP uses this API to finish processing of the secure physical timer 2688interrupt. 2689 2690Function : plat\_ic\_get\_interrupt\_type() [mandatory] 2691~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2692 2693:: 2694 2695 Argument : uint32_t 2696 Return : uint32_t 2697 2698This API returns the type of the interrupt id passed as the parameter. 2699``INTR_TYPE_INVAL`` is returned if the id is invalid. If the id is valid, a valid 2700interrupt type (one of ``INTR_TYPE_EL3``, ``INTR_TYPE_S_EL1`` and ``INTR_TYPE_NS``) is 2701returned depending upon how the interrupt has been configured by the platform 2702IC. This API must be invoked at EL3. 2703 2704Arm standard platforms using GICv2 configures S-EL1 interrupts as Group0 interrupts 2705and Non-secure interrupts as Group1 interrupts. It reads the group value 2706corresponding to the interrupt id from the relevant *Interrupt Group Register* 2707(``GICD_IGROUPRn``). It uses the group value to determine the type of interrupt. 2708 2709In the case of Arm standard platforms using GICv3, both the *Interrupt Group 2710Register* (``GICD_IGROUPRn``) and *Interrupt Group Modifier Register* 2711(``GICD_IGRPMODRn``) is read to figure out whether the interrupt is configured 2712as Group 0 secure interrupt, Group 1 secure interrupt or Group 1 NS interrupt. 2713 2714Crash Reporting mechanism (in BL31) 2715----------------------------------- 2716 2717NOTE: This section assumes that your platform is enabling the MULTI_CONSOLE_API 2718flag in its platform.mk. Not using this flag is deprecated for new platforms. 2719 2720BL31 implements a crash reporting mechanism which prints the various registers 2721of the CPU to enable quick crash analysis and debugging. By default, the 2722definitions in ``plat/common/aarch64/platform\_helpers.S`` will cause the crash 2723output to be routed over the normal console infrastructure and get printed on 2724consoles configured to output in crash state. ``console_set_scope()`` can be 2725used to control whether a console is used for crash output. 2726 2727In some cases (such as debugging very early crashes that happen before the 2728normal boot console can be set up), platforms may want to control crash output 2729more explicitly. For these, the following functions can be overridden by 2730platform code. They are executed outside of a C environment and without a stack. 2731 2732Function : plat\_crash\_console\_init 2733~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2734 2735:: 2736 2737 Argument : void 2738 Return : int 2739 2740This API is used by the crash reporting mechanism to initialize the crash 2741console. It must only use the general purpose registers x0 through x7 to do the 2742initialization and returns 1 on success. 2743 2744If you are trying to debug crashes before the console driver would normally get 2745registered, you can use this to register a driver from assembly with hardcoded 2746parameters. For example, you could register the 16550 driver like this: 2747 2748:: 2749 2750 .section .data.crash_console /* Reserve space for console structure */ 2751 crash_console: 2752 .zero 6 * 8 /* console_16550_t has 6 8-byte words */ 2753 func plat_crash_console_init 2754 ldr x0, =YOUR_16550_BASE_ADDR 2755 ldr x1, =YOUR_16550_SRCCLK_IN_HZ 2756 ldr x2, =YOUR_16550_TARGET_BAUD_RATE 2757 adrp x3, crash_console 2758 add x3, x3, :lo12:crash_console 2759 b console_16550_register /* tail call, returns 1 on success */ 2760 endfunc plat_crash_console_init 2761 2762If you're trying to debug crashes in BL1, you can call the console_xxx_core_init 2763function exported by some console drivers from here. 2764 2765Function : plat\_crash\_console\_putc 2766~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2767 2768:: 2769 2770 Argument : int 2771 Return : int 2772 2773This API is used by the crash reporting mechanism to print a character on the 2774designated crash console. It must only use general purpose registers x1 and 2775x2 to do its work. The parameter and the return value are in general purpose 2776register x0. 2777 2778If you have registered a normal console driver in ``plat_crash_console_init``, 2779you can keep the default implementation here (which calls ``console_putc()``). 2780 2781If you're trying to debug crashes in BL1, you can call the console_xxx_core_putc 2782function exported by some console drivers from here. 2783 2784Function : plat\_crash\_console\_flush 2785~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2786 2787:: 2788 2789 Argument : void 2790 Return : int 2791 2792This API is used by the crash reporting mechanism to force write of all buffered 2793data on the designated crash console. It should only use general purpose 2794registers x0 through x5 to do its work. The return value is 0 on successful 2795completion; otherwise the return value is -1. 2796 2797If you have registered a normal console driver in ``plat_crash_console_init``, 2798you can keep the default implementation here (which calls ``console_flush()``). 2799 2800If you're trying to debug crashes in BL1, you can call the console_xx_core_flush 2801function exported by some console drivers from here. 2802 2803Build flags 2804----------- 2805 2806- **ENABLE\_PLAT\_COMPAT** 2807 All the platforms ports conforming to this API specification should define 2808 the build flag ``ENABLE_PLAT_COMPAT`` to 0 as the compatibility layer should 2809 be disabled. For more details on compatibility layer, refer 2810 `Migration Guide`_. 2811 2812There are some build flags which can be defined by the platform to control 2813inclusion or exclusion of certain BL stages from the FIP image. These flags 2814need to be defined in the platform makefile which will get included by the 2815build system. 2816 2817- **NEED\_BL33** 2818 By default, this flag is defined ``yes`` by the build system and ``BL33`` 2819 build option should be supplied as a build option. The platform has the 2820 option of excluding the BL33 image in the ``fip`` image by defining this flag 2821 to ``no``. If any of the options ``EL3_PAYLOAD_BASE`` or ``PRELOADED_BL33_BASE`` 2822 are used, this flag will be set to ``no`` automatically. 2823 2824C Library 2825--------- 2826 2827To avoid subtle toolchain behavioral dependencies, the header files provided 2828by the compiler are not used. The software is built with the ``-nostdinc`` flag 2829to ensure no headers are included from the toolchain inadvertently. Instead the 2830required headers are included in the TF-A source tree. The library only 2831contains those C library definitions required by the local implementation. If 2832more functionality is required, the needed library functions will need to be 2833added to the local implementation. 2834 2835Versions of `FreeBSD`_ headers can be found in ``include/lib/stdlib``. Some of 2836these headers have been cut down in order to simplify the implementation. In 2837order to minimize changes to the header files, the `FreeBSD`_ layout has been 2838maintained. The generic C library definitions can be found in 2839``include/lib/stdlib`` with more system and machine specific declarations in 2840``include/lib/stdlib/sys`` and ``include/lib/stdlib/machine``. 2841 2842The local C library implementations can be found in ``lib/stdlib``. In order to 2843extend the C library these files may need to be modified. It is recommended to 2844use a release version of `FreeBSD`_ as a starting point. 2845 2846The C library header files in the `FreeBSD`_ source tree are located in the 2847``include`` and ``sys/sys`` directories. `FreeBSD`_ machine specific definitions 2848can be found in the ``sys/<machine-type>`` directories. These files define things 2849like 'the size of a pointer' and 'the range of an integer'. Since an AArch64 2850port for `FreeBSD`_ does not yet exist, the machine specific definitions are 2851based on existing machine types with similar properties (for example SPARC64). 2852 2853Where possible, C library function implementations were taken from `FreeBSD`_ 2854as found in the ``lib/libc`` directory. 2855 2856A copy of the `FreeBSD`_ sources can be downloaded with ``git``. 2857 2858:: 2859 2860 git clone git://github.com/freebsd/freebsd.git -b origin/release/9.2.0 2861 2862Storage abstraction layer 2863------------------------- 2864 2865In order to improve platform independence and portability an storage abstraction 2866layer is used to load data from non-volatile platform storage. 2867 2868Each platform should register devices and their drivers via the Storage layer. 2869These drivers then need to be initialized by bootloader phases as 2870required in their respective ``blx_platform_setup()`` functions. Currently 2871storage access is only required by BL1 and BL2 phases. The ``load_image()`` 2872function uses the storage layer to access non-volatile platform storage. 2873 2874It is mandatory to implement at least one storage driver. For the Arm 2875development platforms the Firmware Image Package (FIP) driver is provided as 2876the default means to load data from storage (see the "Firmware Image Package" 2877section in the `User Guide`_). The storage layer is described in the header file 2878``include/drivers/io/io_storage.h``. The implementation of the common library 2879is in ``drivers/io/io_storage.c`` and the driver files are located in 2880``drivers/io/``. 2881 2882Each IO driver must provide ``io_dev_*`` structures, as described in 2883``drivers/io/io_driver.h``. These are returned via a mandatory registration 2884function that is called on platform initialization. The semi-hosting driver 2885implementation in ``io_semihosting.c`` can be used as an example. 2886 2887The Storage layer provides mechanisms to initialize storage devices before 2888IO operations are called. The basic operations supported by the layer 2889include ``open()``, ``close()``, ``read()``, ``write()``, ``size()`` and ``seek()``. 2890Drivers do not have to implement all operations, but each platform must 2891provide at least one driver for a device capable of supporting generic 2892operations such as loading a bootloader image. 2893 2894The current implementation only allows for known images to be loaded by the 2895firmware. These images are specified by using their identifiers, as defined in 2896[include/plat/common/platform\_def.h] (or a separate header file included from 2897there). The platform layer (``plat_get_image_source()``) then returns a reference 2898to a device and a driver-specific ``spec`` which will be understood by the driver 2899to allow access to the image data. 2900 2901The layer is designed in such a way that is it possible to chain drivers with 2902other drivers. For example, file-system drivers may be implemented on top of 2903physical block devices, both represented by IO devices with corresponding 2904drivers. In such a case, the file-system "binding" with the block device may 2905be deferred until the file-system device is initialised. 2906 2907The abstraction currently depends on structures being statically allocated 2908by the drivers and callers, as the system does not yet provide a means of 2909dynamically allocating memory. This may also have the affect of limiting the 2910amount of open resources per driver. 2911 2912-------------- 2913 2914*Copyright (c) 2013-2018, Arm Limited and Contributors. All rights reserved.* 2915 2916.. _Migration Guide: platform-migration-guide.rst 2917.. _include/plat/common/platform.h: ../include/plat/common/platform.h 2918.. _include/plat/arm/common/plat\_arm.h: ../include/plat/arm/common/plat_arm.h%5D 2919.. _User Guide: user-guide.rst 2920.. _include/plat/common/common\_def.h: ../include/plat/common/common_def.h 2921.. _include/plat/arm/common/arm\_def.h: ../include/plat/arm/common/arm_def.h 2922.. _plat/common/aarch64/platform\_mp\_stack.S: ../plat/common/aarch64/platform_mp_stack.S 2923.. _plat/common/aarch64/platform\_up\_stack.S: ../plat/common/aarch64/platform_up_stack.S 2924.. _For example, define the build flag in platform.mk: PLAT_PL061_MAX_GPIOS%20:=%20160 2925.. _Power Domain Topology Design: psci-pd-tree.rst 2926.. _include/common/bl\_common.h: ../include/common/bl_common.h 2927.. _include/lib/aarch32/arch.h: ../include/lib/aarch32/arch.h 2928.. _Firmware Design: firmware-design.rst 2929.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf 2930.. _plat/arm/board/fvp/fvp\_pm.c: ../plat/arm/board/fvp/fvp_pm.c 2931.. _IMF Design Guide: interrupt-framework-design.rst 2932.. _Arm Generic Interrupt Controller version 2.0 (GICv2): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0048b/index.html 2933.. _3.0 (GICv3): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0069b/index.html 2934.. _FreeBSD: http://www.freebsd.org 2935