1 /* 2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 /* 8 * ZynqMP system level PM-API functions for clock control. 9 */ 10 11 #ifndef _PM_API_CLOCK_H_ 12 #define _PM_API_CLOCK_H_ 13 14 #include "pm_common.h" 15 16 #define CLK_NAME_LEN 15 17 18 enum pm_ret_status pm_api_clock_get_name(unsigned int clock_id, char *name); 19 enum pm_ret_status pm_api_clock_get_topology(unsigned int clock_id, 20 unsigned int index, 21 uint32_t *topology); 22 enum pm_ret_status pm_api_clock_get_fixedfactor_params(unsigned int clock_id, 23 uint32_t *mul, 24 uint32_t *div); 25 enum pm_ret_status pm_api_clock_get_parents(unsigned int clock_id, 26 unsigned int index, 27 uint32_t *parents); 28 enum pm_ret_status pm_api_clock_get_attributes(unsigned int clock_id, 29 uint32_t *attr); 30 enum pm_ret_status pm_api_clock_enable(unsigned int clock_id); 31 enum pm_ret_status pm_api_clock_disable(unsigned int clock_id); 32 enum pm_ret_status pm_api_clock_getstate(unsigned int clock_id, 33 unsigned int *state); 34 enum pm_ret_status pm_api_clock_setdivider(unsigned int clock_id, 35 unsigned int divider); 36 enum pm_ret_status pm_api_clock_getdivider(unsigned int clock_id, 37 unsigned int *divider); 38 enum pm_ret_status pm_api_clock_setrate(unsigned int clock_id, 39 uint64_t rate); 40 enum pm_ret_status pm_api_clock_getrate(unsigned int clock_id, 41 uint64_t *rate); 42 enum pm_ret_status pm_api_clock_setparent(unsigned int clock_id, 43 unsigned int parent_idx); 44 enum pm_ret_status pm_api_clock_getparent(unsigned int clock_id, 45 unsigned int *parent_idx); 46 enum pm_ret_status pm_api_clk_set_pll_mode(unsigned int pll, 47 unsigned int mode); 48 enum pm_ret_status pm_api_clk_get_pll_mode(unsigned int pll, 49 unsigned int *mode); 50 enum pm_ret_status pm_api_clk_set_pll_frac_data(unsigned int pll, 51 unsigned int data); 52 enum pm_ret_status pm_api_clk_get_pll_frac_data(unsigned int pll, 53 unsigned int *data); 54 #endif /* _PM_API_CLOCK_H_ */ 55