1/* 2 * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6#include <arch.h> 7#include <asm_macros.S> 8#include <assert_macros.S> 9#include <bl_common.h> 10#include <cortex_a57.h> 11#include <cpu_macros.S> 12#include <debug.h> 13#include <plat_macros.S> 14 15 /* --------------------------------------------- 16 * Disable L1 data cache and unified L2 cache 17 * --------------------------------------------- 18 */ 19func cortex_a57_disable_dcache 20 mrs x1, sctlr_el3 21 bic x1, x1, #SCTLR_C_BIT 22 msr sctlr_el3, x1 23 isb 24 ret 25endfunc cortex_a57_disable_dcache 26 27 /* --------------------------------------------- 28 * Disable all types of L2 prefetches. 29 * --------------------------------------------- 30 */ 31func cortex_a57_disable_l2_prefetch 32 mrs x0, CORTEX_A57_ECTLR_EL1 33 orr x0, x0, #CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT 34 mov x1, #CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK 35 orr x1, x1, #CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK 36 bic x0, x0, x1 37 msr CORTEX_A57_ECTLR_EL1, x0 38 isb 39 dsb ish 40 ret 41endfunc cortex_a57_disable_l2_prefetch 42 43 /* --------------------------------------------- 44 * Disable intra-cluster coherency 45 * --------------------------------------------- 46 */ 47func cortex_a57_disable_smp 48 mrs x0, CORTEX_A57_ECTLR_EL1 49 bic x0, x0, #CORTEX_A57_ECTLR_SMP_BIT 50 msr CORTEX_A57_ECTLR_EL1, x0 51 ret 52endfunc cortex_a57_disable_smp 53 54 /* --------------------------------------------- 55 * Disable debug interfaces 56 * --------------------------------------------- 57 */ 58func cortex_a57_disable_ext_debug 59 mov x0, #1 60 msr osdlr_el1, x0 61 isb 62 dsb sy 63 ret 64endfunc cortex_a57_disable_ext_debug 65 66 /* -------------------------------------------------- 67 * Errata Workaround for Cortex A57 Errata #806969. 68 * This applies only to revision r0p0 of Cortex A57. 69 * Inputs: 70 * x0: variant[4:7] and revision[0:3] of current cpu. 71 * Shall clobber: x0-x17 72 * -------------------------------------------------- 73 */ 74func errata_a57_806969_wa 75 /* 76 * Compare x0 against revision r0p0 77 */ 78 mov x17, x30 79 bl check_errata_806969 80 cbz x0, 1f 81 mrs x1, CORTEX_A57_CPUACTLR_EL1 82 orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA 83 msr CORTEX_A57_CPUACTLR_EL1, x1 841: 85 ret x17 86endfunc errata_a57_806969_wa 87 88func check_errata_806969 89 mov x1, #0x00 90 b cpu_rev_var_ls 91endfunc check_errata_806969 92 93 /* --------------------------------------------------- 94 * Errata Workaround for Cortex A57 Errata #813419. 95 * This applies only to revision r0p0 of Cortex A57. 96 * --------------------------------------------------- 97 */ 98func check_errata_813419 99 /* 100 * Even though this is only needed for revision r0p0, it 101 * is always applied due to limitations of the current 102 * errata framework. 103 */ 104 mov x0, #ERRATA_APPLIES 105 ret 106endfunc check_errata_813419 107 108 /* --------------------------------------------------- 109 * Errata Workaround for Cortex A57 Errata #813420. 110 * This applies only to revision r0p0 of Cortex A57. 111 * Inputs: 112 * x0: variant[4:7] and revision[0:3] of current cpu. 113 * Shall clobber: x0-x17 114 * --------------------------------------------------- 115 */ 116func errata_a57_813420_wa 117 /* 118 * Compare x0 against revision r0p0 119 */ 120 mov x17, x30 121 bl check_errata_813420 122 cbz x0, 1f 123 mrs x1, CORTEX_A57_CPUACTLR_EL1 124 orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DCC_AS_DCCI 125 msr CORTEX_A57_CPUACTLR_EL1, x1 1261: 127 ret x17 128endfunc errata_a57_813420_wa 129 130func check_errata_813420 131 mov x1, #0x00 132 b cpu_rev_var_ls 133endfunc check_errata_813420 134 135 /* -------------------------------------------------------------------- 136 * Disable the over-read from the LDNP instruction. 137 * 138 * This applies to all revisions <= r1p2. The performance degradation 139 * observed with LDNP/STNP has been fixed on r1p3 and onwards. 140 * 141 * Inputs: 142 * x0: variant[4:7] and revision[0:3] of current cpu. 143 * Shall clobber: x0-x17 144 * --------------------------------------------------------------------- 145 */ 146func a57_disable_ldnp_overread 147 /* 148 * Compare x0 against revision r1p2 149 */ 150 mov x17, x30 151 bl check_errata_disable_ldnp_overread 152 cbz x0, 1f 153 mrs x1, CORTEX_A57_CPUACTLR_EL1 154 orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_OVERREAD 155 msr CORTEX_A57_CPUACTLR_EL1, x1 1561: 157 ret x17 158endfunc a57_disable_ldnp_overread 159 160func check_errata_disable_ldnp_overread 161 mov x1, #0x12 162 b cpu_rev_var_ls 163endfunc check_errata_disable_ldnp_overread 164 165 /* --------------------------------------------------- 166 * Errata Workaround for Cortex A57 Errata #826974. 167 * This applies only to revision <= r1p1 of Cortex A57. 168 * Inputs: 169 * x0: variant[4:7] and revision[0:3] of current cpu. 170 * Shall clobber: x0-x17 171 * --------------------------------------------------- 172 */ 173func errata_a57_826974_wa 174 /* 175 * Compare x0 against revision r1p1 176 */ 177 mov x17, x30 178 bl check_errata_826974 179 cbz x0, 1f 180 mrs x1, CORTEX_A57_CPUACTLR_EL1 181 orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_DMB 182 msr CORTEX_A57_CPUACTLR_EL1, x1 1831: 184 ret x17 185endfunc errata_a57_826974_wa 186 187func check_errata_826974 188 mov x1, #0x11 189 b cpu_rev_var_ls 190endfunc check_errata_826974 191 192 /* --------------------------------------------------- 193 * Errata Workaround for Cortex A57 Errata #826977. 194 * This applies only to revision <= r1p1 of Cortex A57. 195 * Inputs: 196 * x0: variant[4:7] and revision[0:3] of current cpu. 197 * Shall clobber: x0-x17 198 * --------------------------------------------------- 199 */ 200func errata_a57_826977_wa 201 /* 202 * Compare x0 against revision r1p1 203 */ 204 mov x17, x30 205 bl check_errata_826977 206 cbz x0, 1f 207 mrs x1, CORTEX_A57_CPUACTLR_EL1 208 orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_GRE_NGRE_AS_NGNRE 209 msr CORTEX_A57_CPUACTLR_EL1, x1 2101: 211 ret x17 212endfunc errata_a57_826977_wa 213 214func check_errata_826977 215 mov x1, #0x11 216 b cpu_rev_var_ls 217endfunc check_errata_826977 218 219 /* --------------------------------------------------- 220 * Errata Workaround for Cortex A57 Errata #828024. 221 * This applies only to revision <= r1p1 of Cortex A57. 222 * Inputs: 223 * x0: variant[4:7] and revision[0:3] of current cpu. 224 * Shall clobber: x0-x17 225 * --------------------------------------------------- 226 */ 227func errata_a57_828024_wa 228 /* 229 * Compare x0 against revision r1p1 230 */ 231 mov x17, x30 232 bl check_errata_828024 233 cbz x0, 1f 234 mrs x1, CORTEX_A57_CPUACTLR_EL1 235 /* 236 * Setting the relevant bits in CPUACTLR_EL1 has to be done in 2 237 * instructions here because the resulting bitmask doesn't fit in a 238 * 16-bit value so it cannot be encoded in a single instruction. 239 */ 240 orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA 241 orr x1, x1, #(CORTEX_A57_CPUACTLR_EL1_DIS_L1_STREAMING | \ 242 CORTEX_A57_CPUACTLR_EL1_DIS_STREAMING) 243 msr CORTEX_A57_CPUACTLR_EL1, x1 2441: 245 ret x17 246endfunc errata_a57_828024_wa 247 248func check_errata_828024 249 mov x1, #0x11 250 b cpu_rev_var_ls 251endfunc check_errata_828024 252 253 /* --------------------------------------------------- 254 * Errata Workaround for Cortex A57 Errata #829520. 255 * This applies only to revision <= r1p2 of Cortex A57. 256 * Inputs: 257 * x0: variant[4:7] and revision[0:3] of current cpu. 258 * Shall clobber: x0-x17 259 * --------------------------------------------------- 260 */ 261func errata_a57_829520_wa 262 /* 263 * Compare x0 against revision r1p2 264 */ 265 mov x17, x30 266 bl check_errata_829520 267 cbz x0, 1f 268 mrs x1, CORTEX_A57_CPUACTLR_EL1 269 orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_INDIRECT_PREDICTOR 270 msr CORTEX_A57_CPUACTLR_EL1, x1 2711: 272 ret x17 273endfunc errata_a57_829520_wa 274 275func check_errata_829520 276 mov x1, #0x12 277 b cpu_rev_var_ls 278endfunc check_errata_829520 279 280 /* --------------------------------------------------- 281 * Errata Workaround for Cortex A57 Errata #833471. 282 * This applies only to revision <= r1p2 of Cortex A57. 283 * Inputs: 284 * x0: variant[4:7] and revision[0:3] of current cpu. 285 * Shall clobber: x0-x17 286 * --------------------------------------------------- 287 */ 288func errata_a57_833471_wa 289 /* 290 * Compare x0 against revision r1p2 291 */ 292 mov x17, x30 293 bl check_errata_833471 294 cbz x0, 1f 295 mrs x1, CORTEX_A57_CPUACTLR_EL1 296 orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_FORCE_FPSCR_FLUSH 297 msr CORTEX_A57_CPUACTLR_EL1, x1 2981: 299 ret x17 300endfunc errata_a57_833471_wa 301 302func check_errata_833471 303 mov x1, #0x12 304 b cpu_rev_var_ls 305endfunc check_errata_833471 306 307 /* -------------------------------------------------- 308 * Errata Workaround for Cortex A57 Errata #859972. 309 * This applies only to revision <= r1p3 of Cortex A57. 310 * Inputs: 311 * x0: variant[4:7] and revision[0:3] of current cpu. 312 * Shall clobber: 313 * -------------------------------------------------- 314 */ 315func errata_a57_859972_wa 316 mov x17, x30 317 bl check_errata_859972 318 cbz x0, 1f 319 mrs x1, CORTEX_A57_CPUACTLR_EL1 320 orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_INSTR_PREFETCH 321 msr CORTEX_A57_CPUACTLR_EL1, x1 3221: 323 ret x17 324endfunc errata_a57_859972_wa 325 326func check_errata_859972 327 mov x1, #0x13 328 b cpu_rev_var_ls 329endfunc check_errata_859972 330 331func check_errata_cve_2017_5715 332#if WORKAROUND_CVE_2017_5715 333 mov x0, #ERRATA_APPLIES 334#else 335 mov x0, #ERRATA_MISSING 336#endif 337 ret 338endfunc check_errata_cve_2017_5715 339 340 /* ------------------------------------------------- 341 * The CPU Ops reset function for Cortex-A57. 342 * Shall clobber: x0-x19 343 * ------------------------------------------------- 344 */ 345func cortex_a57_reset_func 346 mov x19, x30 347 bl cpu_get_rev_var 348 mov x18, x0 349 350#if ERRATA_A57_806969 351 mov x0, x18 352 bl errata_a57_806969_wa 353#endif 354 355#if ERRATA_A57_813420 356 mov x0, x18 357 bl errata_a57_813420_wa 358#endif 359 360#if A57_DISABLE_NON_TEMPORAL_HINT 361 mov x0, x18 362 bl a57_disable_ldnp_overread 363#endif 364 365#if ERRATA_A57_826974 366 mov x0, x18 367 bl errata_a57_826974_wa 368#endif 369 370#if ERRATA_A57_826977 371 mov x0, x18 372 bl errata_a57_826977_wa 373#endif 374 375#if ERRATA_A57_828024 376 mov x0, x18 377 bl errata_a57_828024_wa 378#endif 379 380#if ERRATA_A57_829520 381 mov x0, x18 382 bl errata_a57_829520_wa 383#endif 384 385#if ERRATA_A57_833471 386 mov x0, x18 387 bl errata_a57_833471_wa 388#endif 389 390#if ERRATA_A57_859972 391 mov x0, x18 392 bl errata_a57_859972_wa 393#endif 394 395#if IMAGE_BL31 && WORKAROUND_CVE_2017_5715 396 adr x0, workaround_mmu_runtime_exceptions 397 msr vbar_el3, x0 398#endif 399 400 /* --------------------------------------------- 401 * Enable the SMP bit. 402 * --------------------------------------------- 403 */ 404 mrs x0, CORTEX_A57_ECTLR_EL1 405 orr x0, x0, #CORTEX_A57_ECTLR_SMP_BIT 406 msr CORTEX_A57_ECTLR_EL1, x0 407 isb 408 ret x19 409endfunc cortex_a57_reset_func 410 411 /* ---------------------------------------------------- 412 * The CPU Ops core power down function for Cortex-A57. 413 * ---------------------------------------------------- 414 */ 415func cortex_a57_core_pwr_dwn 416 mov x18, x30 417 418 /* --------------------------------------------- 419 * Turn off caches. 420 * --------------------------------------------- 421 */ 422 bl cortex_a57_disable_dcache 423 424 /* --------------------------------------------- 425 * Disable the L2 prefetches. 426 * --------------------------------------------- 427 */ 428 bl cortex_a57_disable_l2_prefetch 429 430 /* --------------------------------------------- 431 * Flush L1 caches. 432 * --------------------------------------------- 433 */ 434 mov x0, #DCCISW 435 bl dcsw_op_level1 436 437 /* --------------------------------------------- 438 * Come out of intra cluster coherency 439 * --------------------------------------------- 440 */ 441 bl cortex_a57_disable_smp 442 443 /* --------------------------------------------- 444 * Force the debug interfaces to be quiescent 445 * --------------------------------------------- 446 */ 447 mov x30, x18 448 b cortex_a57_disable_ext_debug 449endfunc cortex_a57_core_pwr_dwn 450 451 /* ------------------------------------------------------- 452 * The CPU Ops cluster power down function for Cortex-A57. 453 * ------------------------------------------------------- 454 */ 455func cortex_a57_cluster_pwr_dwn 456 mov x18, x30 457 458 /* --------------------------------------------- 459 * Turn off caches. 460 * --------------------------------------------- 461 */ 462 bl cortex_a57_disable_dcache 463 464 /* --------------------------------------------- 465 * Disable the L2 prefetches. 466 * --------------------------------------------- 467 */ 468 bl cortex_a57_disable_l2_prefetch 469 470#if !SKIP_A57_L1_FLUSH_PWR_DWN 471 /* ------------------------------------------------- 472 * Flush the L1 caches. 473 * ------------------------------------------------- 474 */ 475 mov x0, #DCCISW 476 bl dcsw_op_level1 477#endif 478 /* --------------------------------------------- 479 * Disable the optional ACP. 480 * --------------------------------------------- 481 */ 482 bl plat_disable_acp 483 484 /* ------------------------------------------------- 485 * Flush the L2 caches. 486 * ------------------------------------------------- 487 */ 488 mov x0, #DCCISW 489 bl dcsw_op_level2 490 491 /* --------------------------------------------- 492 * Come out of intra cluster coherency 493 * --------------------------------------------- 494 */ 495 bl cortex_a57_disable_smp 496 497 /* --------------------------------------------- 498 * Force the debug interfaces to be quiescent 499 * --------------------------------------------- 500 */ 501 mov x30, x18 502 b cortex_a57_disable_ext_debug 503endfunc cortex_a57_cluster_pwr_dwn 504 505#if REPORT_ERRATA 506/* 507 * Errata printing function for Cortex A57. Must follow AAPCS. 508 */ 509func cortex_a57_errata_report 510 stp x8, x30, [sp, #-16]! 511 512 bl cpu_get_rev_var 513 mov x8, x0 514 515 /* 516 * Report all errata. The revision-variant information is passed to 517 * checking functions of each errata. 518 */ 519 report_errata ERRATA_A57_806969, cortex_a57, 806969 520 report_errata ERRATA_A57_813419, cortex_a57, 813419 521 report_errata ERRATA_A57_813420, cortex_a57, 813420 522 report_errata A57_DISABLE_NON_TEMPORAL_HINT, cortex_a57, \ 523 disable_ldnp_overread 524 report_errata ERRATA_A57_826974, cortex_a57, 826974 525 report_errata ERRATA_A57_826977, cortex_a57, 826977 526 report_errata ERRATA_A57_828024, cortex_a57, 828024 527 report_errata ERRATA_A57_829520, cortex_a57, 829520 528 report_errata ERRATA_A57_833471, cortex_a57, 833471 529 report_errata ERRATA_A57_859972, cortex_a57, 859972 530 report_errata WORKAROUND_CVE_2017_5715, cortex_a57, cve_2017_5715 531 532 ldp x8, x30, [sp], #16 533 ret 534endfunc cortex_a57_errata_report 535#endif 536 537 /* --------------------------------------------- 538 * This function provides cortex_a57 specific 539 * register information for crash reporting. 540 * It needs to return with x6 pointing to 541 * a list of register names in ascii and 542 * x8 - x15 having values of registers to be 543 * reported. 544 * --------------------------------------------- 545 */ 546.section .rodata.cortex_a57_regs, "aS" 547cortex_a57_regs: /* The ascii list of register names to be reported */ 548 .asciz "cpuectlr_el1", "cpumerrsr_el1", "l2merrsr_el1", "" 549 550func cortex_a57_cpu_reg_dump 551 adr x6, cortex_a57_regs 552 mrs x8, CORTEX_A57_ECTLR_EL1 553 mrs x9, CORTEX_A57_MERRSR_EL1 554 mrs x10, CORTEX_A57_L2MERRSR_EL1 555 ret 556endfunc cortex_a57_cpu_reg_dump 557 558declare_cpu_ops_workaround_cve_2017_5715 cortex_a57, CORTEX_A57_MIDR, \ 559 cortex_a57_reset_func, \ 560 check_errata_cve_2017_5715, \ 561 cortex_a57_core_pwr_dwn, \ 562 cortex_a57_cluster_pwr_dwn 563