1 /* 2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 /* 8 * ZynqMP system level PM-API functions for pin control. 9 */ 10 11 #include <arch_helpers.h> 12 #include <platform.h> 13 #include "pm_api_pinctrl.h" 14 #include "pm_api_sys.h" 15 #include "pm_client.h" 16 #include "pm_common.h" 17 #include "pm_ipi.h" 18 19 #define PINCTRL_FUNCTION_MASK 0xFE 20 #define PINCTRL_VOLTAGE_STATUS_MASK 0x01 21 #define NFUNCS_PER_PIN 13 22 #define PINCTRL_NUM_MIOS 78 23 #define MAX_PIN_PER_REG 26 24 #define PINCTRL_BANK_ADDR_STEP 28 25 26 #define PINCTRL_DRVSTRN0_REG_OFFSET 0 27 #define PINCTRL_DRVSTRN1_REG_OFFSET 4 28 #define PINCTRL_SCHCMOS_REG_OFFSET 8 29 #define PINCTRL_PULLCTRL_REG_OFFSET 12 30 #define PINCTRL_PULLSTAT_REG_OFFSET 16 31 #define PINCTRL_SLEWCTRL_REG_OFFSET 20 32 #define PINCTRL_VOLTAGE_STAT_REG_OFFSET 24 33 34 #define IOU_SLCR_BANK1_CTRL5 0XFF180164 35 36 #define PINCTRL_CFG_ADDR_OFFSET(addr, reg, pin) \ 37 ((addr) + 4 * PINCTRL_NUM_MIOS + PINCTRL_BANK_ADDR_STEP * \ 38 ((pin) / MAX_PIN_PER_REG) + (reg)) 39 40 #define PINCTRL_PIN_OFFSET(pin) \ 41 ((pin) - (MAX_PIN_PER_REG * ((pin) / MAX_PIN_PER_REG))) 42 43 #define PINCTRL_REGVAL_TO_PIN_CONFIG(pin, value) \ 44 (((value) >> PINCTRL_PIN_OFFSET(pin)) & 0x1) 45 46 #define PINMUX_MAP(pin, f0, f1, f2, f3, f4, f5, f6, \ 47 f7, f8, f9, f10, f11, f12) \ 48 [pin] = { \ 49 .funcs = { \ 50 f0, \ 51 f1, \ 52 f2, \ 53 f3, \ 54 f4, \ 55 f5, \ 56 f6, \ 57 f7, \ 58 f8, \ 59 f9, \ 60 f10, \ 61 f11, \ 62 f12, \ 63 }, \ 64 } 65 66 struct pm_pinctrl_pinmux_map { 67 uint8_t funcs[NFUNCS_PER_PIN]; 68 }; 69 70 static uint8_t pm_pinctrl_mux[NFUNCS_PER_PIN] = { 71 0x02, 0x04, 0x08, 0x10, 0x18, 72 0x00, 0x20, 0x40, 0x60, 0x80, 73 0xA0, 0xC0, 0xE0 74 }; 75 76 struct pm_pinctrl_pinmux_map pinmux_maps[] = { 77 PINMUX_MAP(0, NODE_QSPI, NODE_UNKNOWN, NODE_UNKNOWN, NODE_TESTSCAN, 78 NODE_UNKNOWN, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_PJTAG, 79 NODE_SPI_0, NODE_TTC_3, NODE_UART_1, NODE_TRACE), 80 PINMUX_MAP(1, NODE_QSPI, NODE_UNKNOWN, NODE_UNKNOWN, NODE_TESTSCAN, 81 NODE_UNKNOWN, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_PJTAG, 82 NODE_SPI_0, NODE_TTC_3, NODE_UART_1, NODE_TRACE), 83 PINMUX_MAP(2, NODE_QSPI, NODE_UNKNOWN, NODE_UNKNOWN, NODE_TESTSCAN, 84 NODE_UNKNOWN, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_PJTAG, 85 NODE_SPI_0, NODE_TTC_2, NODE_UART_0, NODE_TRACE), 86 PINMUX_MAP(3, NODE_QSPI, NODE_UNKNOWN, NODE_UNKNOWN, NODE_TESTSCAN, 87 NODE_UNKNOWN, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_PJTAG, 88 NODE_SPI_0, NODE_TTC_2, NODE_UART_0, NODE_TRACE), 89 PINMUX_MAP(4, NODE_QSPI, NODE_UNKNOWN, NODE_UNKNOWN, NODE_TESTSCAN, 90 NODE_UNKNOWN, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_SWDT_1, 91 NODE_SPI_0, NODE_TTC_1, NODE_UART_1, NODE_TRACE), 92 PINMUX_MAP(5, NODE_QSPI, NODE_UNKNOWN, NODE_UNKNOWN, NODE_TESTSCAN, 93 NODE_UNKNOWN, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_SWDT_1, 94 NODE_SPI_0, NODE_TTC_1, NODE_UART_1, NODE_TRACE), 95 PINMUX_MAP(6, NODE_QSPI, NODE_UNKNOWN, NODE_UNKNOWN, NODE_TESTSCAN, 96 NODE_UNKNOWN, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_SWDT_0, 97 NODE_SPI_1, NODE_TTC_0, NODE_UART_0, NODE_TRACE), 98 PINMUX_MAP(7, NODE_QSPI, NODE_UNKNOWN, NODE_UNKNOWN, NODE_TESTSCAN, 99 NODE_UNKNOWN, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_SWDT_0, 100 NODE_SPI_1, NODE_TTC_0, NODE_UART_0, NODE_TRACE), 101 PINMUX_MAP(8, NODE_QSPI, NODE_UNKNOWN, NODE_UNKNOWN, NODE_TESTSCAN, 102 NODE_UNKNOWN, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_SWDT_1, 103 NODE_SPI_1, NODE_TTC_3, NODE_UART_1, NODE_TRACE), 104 PINMUX_MAP(9, NODE_QSPI, NODE_NAND, NODE_UNKNOWN, NODE_TESTSCAN, 105 NODE_UNKNOWN, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_SWDT_1, 106 NODE_SPI_1, NODE_TTC_3, NODE_UART_1, NODE_TRACE), 107 PINMUX_MAP(10, NODE_QSPI, NODE_NAND, NODE_UNKNOWN, NODE_TESTSCAN, 108 NODE_UNKNOWN, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_SWDT_0, 109 NODE_SPI_1, NODE_TTC_2, NODE_UART_0, NODE_TRACE), 110 PINMUX_MAP(11, NODE_QSPI, NODE_NAND, NODE_UNKNOWN, NODE_TESTSCAN, 111 NODE_UNKNOWN, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_SWDT_0, 112 NODE_SPI_1, NODE_TTC_2, NODE_UART_0, NODE_TRACE), 113 PINMUX_MAP(12, NODE_QSPI, NODE_NAND, NODE_UNKNOWN, NODE_TESTSCAN, 114 NODE_UNKNOWN, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_PJTAG, 115 NODE_SPI_0, NODE_TTC_1, NODE_UART_1, NODE_TRACE), 116 PINMUX_MAP(13, NODE_UNKNOWN, NODE_NAND, NODE_SD_0, NODE_TESTSCAN, 117 NODE_UNKNOWN, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_PJTAG, 118 NODE_SPI_0, NODE_TTC_1, NODE_UART_1, NODE_TRACE), 119 PINMUX_MAP(14, NODE_UNKNOWN, NODE_NAND, NODE_SD_0, NODE_TESTSCAN, 120 NODE_UNKNOWN, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_PJTAG, 121 NODE_SPI_0, NODE_TTC_0, NODE_UART_0, NODE_TRACE), 122 PINMUX_MAP(15, NODE_UNKNOWN, NODE_NAND, NODE_SD_0, NODE_TESTSCAN, 123 NODE_UNKNOWN, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_PJTAG, 124 NODE_SPI_0, NODE_TTC_0, NODE_UART_0, NODE_TRACE), 125 PINMUX_MAP(16, NODE_UNKNOWN, NODE_NAND, NODE_SD_0, NODE_TESTSCAN, 126 NODE_UNKNOWN, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_SWDT_1, 127 NODE_SPI_0, NODE_TTC_3, NODE_UART_1, NODE_TRACE), 128 PINMUX_MAP(17, NODE_UNKNOWN, NODE_NAND, NODE_SD_0, NODE_TESTSCAN, 129 NODE_UNKNOWN, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_SWDT_1, 130 NODE_SPI_0, NODE_TTC_3, NODE_UART_1, NODE_TRACE), 131 PINMUX_MAP(18, NODE_UNKNOWN, NODE_NAND, NODE_SD_0, NODE_TESTSCAN, 132 NODE_UNKNOWN, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_SWDT_0, 133 NODE_SPI_1, NODE_TTC_2, NODE_UART_0, NODE_UNKNOWN), 134 PINMUX_MAP(19, NODE_UNKNOWN, NODE_NAND, NODE_SD_0, NODE_TESTSCAN, 135 NODE_CSU, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_SWDT_0, 136 NODE_SPI_1, NODE_TTC_2, NODE_UART_0, NODE_UNKNOWN), 137 PINMUX_MAP(20, NODE_UNKNOWN, NODE_NAND, NODE_SD_0, NODE_TESTSCAN, 138 NODE_CSU, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_SWDT_1, 139 NODE_SPI_1, NODE_TTC_1, NODE_UART_1, NODE_UNKNOWN), 140 PINMUX_MAP(21, NODE_UNKNOWN, NODE_NAND, NODE_SD_0, NODE_TESTSCAN, 141 NODE_CSU, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_SWDT_1, 142 NODE_SPI_1, NODE_TTC_1, NODE_UART_1, NODE_UNKNOWN), 143 PINMUX_MAP(22, NODE_UNKNOWN, NODE_NAND, NODE_SD_0, NODE_TESTSCAN, 144 NODE_CSU, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_SWDT_0, 145 NODE_SPI_1, NODE_TTC_0, NODE_UART_0, NODE_UNKNOWN), 146 PINMUX_MAP(23, NODE_UNKNOWN, NODE_NAND, NODE_SD_0, NODE_TESTSCAN, 147 NODE_CSU, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_SWDT_0, 148 NODE_SPI_1, NODE_TTC_0, NODE_UART_0, NODE_UNKNOWN), 149 PINMUX_MAP(24, NODE_UNKNOWN, NODE_NAND, NODE_SD_0, NODE_TESTSCAN, 150 NODE_CSU, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_SWDT_1, 151 NODE_UNKNOWN, NODE_TTC_3, NODE_UART_1, NODE_UNKNOWN), 152 PINMUX_MAP(25, NODE_UNKNOWN, NODE_NAND, NODE_SD_0, NODE_TESTSCAN, 153 NODE_CSU, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_SWDT_1, 154 NODE_UNKNOWN, NODE_TTC_3, NODE_UART_1, NODE_UNKNOWN), 155 PINMUX_MAP(26, NODE_ETH_0, NODE_NAND, NODE_PMU, NODE_TESTSCAN, 156 NODE_CSU, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_PJTAG, 157 NODE_SPI_0, NODE_TTC_2, NODE_UART_0, NODE_TRACE), 158 PINMUX_MAP(27, NODE_ETH_0, NODE_NAND, NODE_PMU, NODE_TESTSCAN, 159 NODE_DP, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_PJTAG, 160 NODE_SPI_0, NODE_TTC_2, NODE_UART_0, NODE_TRACE), 161 PINMUX_MAP(28, NODE_ETH_0, NODE_NAND, NODE_PMU, NODE_TESTSCAN, 162 NODE_DP, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_PJTAG, 163 NODE_SPI_0, NODE_TTC_1, NODE_UART_1, NODE_TRACE), 164 PINMUX_MAP(29, NODE_ETH_0, NODE_PCIE, NODE_PMU, NODE_TESTSCAN, 165 NODE_DP, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_PJTAG, 166 NODE_SPI_0, NODE_TTC_1, NODE_UART_1, NODE_TRACE), 167 PINMUX_MAP(30, NODE_ETH_0, NODE_PCIE, NODE_PMU, NODE_TESTSCAN, 168 NODE_DP, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_SWDT_0, 169 NODE_SPI_0, NODE_TTC_0, NODE_UART_0, NODE_TRACE), 170 PINMUX_MAP(31, NODE_ETH_0, NODE_PCIE, NODE_PMU, NODE_TESTSCAN, 171 NODE_CSU, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_SWDT_0, 172 NODE_SPI_0, NODE_TTC_0, NODE_UART_0, NODE_TRACE), 173 PINMUX_MAP(32, NODE_ETH_0, NODE_NAND, NODE_PMU, NODE_TESTSCAN, 174 NODE_CSU, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_SWDT_1, 175 NODE_SPI_1, NODE_TTC_3, NODE_UART_1, NODE_TRACE), 176 PINMUX_MAP(33, NODE_ETH_0, NODE_PCIE, NODE_PMU, NODE_TESTSCAN, 177 NODE_CSU, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_SWDT_1, 178 NODE_SPI_1, NODE_TTC_3, NODE_UART_1, NODE_TRACE), 179 PINMUX_MAP(34, NODE_ETH_0, NODE_PCIE, NODE_PMU, NODE_TESTSCAN, 180 NODE_DP, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_SWDT_0, 181 NODE_SPI_1, NODE_TTC_2, NODE_UART_0, NODE_TRACE), 182 PINMUX_MAP(35, NODE_ETH_0, NODE_PCIE, NODE_PMU, NODE_TESTSCAN, 183 NODE_DP, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_SWDT_0, 184 NODE_SPI_1, NODE_TTC_2, NODE_UART_0, NODE_TRACE), 185 PINMUX_MAP(36, NODE_ETH_0, NODE_PCIE, NODE_PMU, NODE_TESTSCAN, 186 NODE_DP, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_SWDT_1, 187 NODE_SPI_1, NODE_TTC_1, NODE_UART_1, NODE_TRACE), 188 PINMUX_MAP(37, NODE_ETH_0, NODE_PCIE, NODE_PMU, NODE_TESTSCAN, 189 NODE_DP, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_SWDT_1, 190 NODE_SPI_1, NODE_TTC_1, NODE_UART_1, NODE_TRACE), 191 PINMUX_MAP(38, NODE_ETH_1, NODE_UNKNOWN, NODE_SD_0, NODE_UNKNOWN, 192 NODE_UNKNOWN, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_PJTAG, 193 NODE_SPI_0, NODE_TTC_0, NODE_UART_0, NODE_TRACE), 194 PINMUX_MAP(39, NODE_ETH_1, NODE_UNKNOWN, NODE_SD_0, NODE_SD_1, 195 NODE_UNKNOWN, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_PJTAG, 196 NODE_SPI_0, NODE_TTC_0, NODE_UART_0, NODE_TRACE), 197 PINMUX_MAP(40, NODE_ETH_1, NODE_UNKNOWN, NODE_SD_0, NODE_SD_1, 198 NODE_UNKNOWN, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_PJTAG, 199 NODE_SPI_0, NODE_TTC_3, NODE_UART_1, NODE_TRACE), 200 PINMUX_MAP(41, NODE_ETH_1, NODE_UNKNOWN, NODE_SD_0, NODE_SD_1, 201 NODE_UNKNOWN, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_PJTAG, 202 NODE_SPI_0, NODE_TTC_3, NODE_UART_1, NODE_TRACE), 203 PINMUX_MAP(42, NODE_ETH_1, NODE_UNKNOWN, NODE_SD_0, NODE_SD_1, 204 NODE_UNKNOWN, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_SWDT_0, 205 NODE_SPI_0, NODE_TTC_2, NODE_UART_0, NODE_TRACE), 206 PINMUX_MAP(43, NODE_ETH_1, NODE_UNKNOWN, NODE_SD_0, NODE_SD_1, 207 NODE_UNKNOWN, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_SWDT_0, 208 NODE_SPI_0, NODE_TTC_2, NODE_UART_0, NODE_TRACE), 209 PINMUX_MAP(44, NODE_ETH_1, NODE_UNKNOWN, NODE_SD_0, NODE_SD_1, 210 NODE_UNKNOWN, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_SWDT_1, 211 NODE_SPI_1, NODE_TTC_1, NODE_UART_1, NODE_UNKNOWN), 212 PINMUX_MAP(45, NODE_ETH_1, NODE_UNKNOWN, NODE_SD_0, NODE_SD_1, 213 NODE_UNKNOWN, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_SWDT_1, 214 NODE_SPI_1, NODE_TTC_1, NODE_UART_1, NODE_UNKNOWN), 215 PINMUX_MAP(46, NODE_ETH_1, NODE_UNKNOWN, NODE_SD_0, NODE_SD_1, 216 NODE_UNKNOWN, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_SWDT_0, 217 NODE_SPI_1, NODE_TTC_0, NODE_UART_0, NODE_UNKNOWN), 218 PINMUX_MAP(47, NODE_ETH_1, NODE_UNKNOWN, NODE_SD_0, NODE_SD_1, 219 NODE_UNKNOWN, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_SWDT_0, 220 NODE_SPI_1, NODE_TTC_0, NODE_UART_0, NODE_UNKNOWN), 221 PINMUX_MAP(48, NODE_ETH_1, NODE_UNKNOWN, NODE_SD_0, NODE_SD_1, 222 NODE_UNKNOWN, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_SWDT_1, 223 NODE_SPI_1, NODE_TTC_3, NODE_UART_1, NODE_UNKNOWN), 224 PINMUX_MAP(49, NODE_ETH_1, NODE_UNKNOWN, NODE_SD_0, NODE_SD_1, 225 NODE_UNKNOWN, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_SWDT_1, 226 NODE_SPI_1, NODE_TTC_3, NODE_UART_1, NODE_UNKNOWN), 227 PINMUX_MAP(50, NODE_GEM_TSU, NODE_UNKNOWN, NODE_SD_0, NODE_SD_1, 228 NODE_UNKNOWN, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_SWDT_0, 229 NODE_ETH_1, NODE_TTC_2, NODE_UART_0, NODE_UNKNOWN), 230 PINMUX_MAP(51, NODE_GEM_TSU, NODE_UNKNOWN, NODE_UNKNOWN, NODE_SD_1, 231 NODE_UNKNOWN, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_SWDT_0, 232 NODE_ETH_1, NODE_TTC_2, NODE_UART_0, NODE_UNKNOWN), 233 PINMUX_MAP(52, NODE_ETH_2, NODE_USB_0, NODE_UNKNOWN, NODE_UNKNOWN, 234 NODE_UNKNOWN, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_PJTAG, 235 NODE_SPI_0, NODE_TTC_1, NODE_UART_1, NODE_TRACE), 236 PINMUX_MAP(53, NODE_ETH_2, NODE_USB_0, NODE_UNKNOWN, NODE_UNKNOWN, 237 NODE_UNKNOWN, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_PJTAG, 238 NODE_SPI_0, NODE_TTC_1, NODE_UART_1, NODE_TRACE), 239 PINMUX_MAP(54, NODE_ETH_2, NODE_USB_0, NODE_UNKNOWN, NODE_UNKNOWN, 240 NODE_UNKNOWN, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_PJTAG, 241 NODE_SPI_0, NODE_TTC_0, NODE_UART_0, NODE_TRACE), 242 PINMUX_MAP(55, NODE_ETH_2, NODE_USB_0, NODE_UNKNOWN, NODE_UNKNOWN, 243 NODE_UNKNOWN, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_PJTAG, 244 NODE_SPI_0, NODE_TTC_0, NODE_UART_0, NODE_TRACE), 245 PINMUX_MAP(56, NODE_ETH_2, NODE_USB_0, NODE_UNKNOWN, NODE_UNKNOWN, 246 NODE_UNKNOWN, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_SWDT_1, 247 NODE_SPI_0, NODE_TTC_3, NODE_UART_1, NODE_TRACE), 248 PINMUX_MAP(57, NODE_ETH_2, NODE_USB_0, NODE_UNKNOWN, NODE_UNKNOWN, 249 NODE_UNKNOWN, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_SWDT_1, 250 NODE_SPI_0, NODE_TTC_3, NODE_UART_1, NODE_TRACE), 251 PINMUX_MAP(58, NODE_ETH_2, NODE_USB_0, NODE_UNKNOWN, NODE_UNKNOWN, 252 NODE_UNKNOWN, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_PJTAG, 253 NODE_SPI_1, NODE_TTC_2, NODE_UART_0, NODE_TRACE), 254 PINMUX_MAP(59, NODE_ETH_2, NODE_USB_0, NODE_UNKNOWN, NODE_UNKNOWN, 255 NODE_UNKNOWN, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_PJTAG, 256 NODE_SPI_1, NODE_TTC_2, NODE_UART_0, NODE_TRACE), 257 PINMUX_MAP(60, NODE_ETH_2, NODE_USB_0, NODE_UNKNOWN, NODE_UNKNOWN, 258 NODE_UNKNOWN, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_PJTAG, 259 NODE_SPI_1, NODE_TTC_1, NODE_UART_1, NODE_TRACE), 260 PINMUX_MAP(61, NODE_ETH_2, NODE_USB_0, NODE_UNKNOWN, NODE_UNKNOWN, 261 NODE_UNKNOWN, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_PJTAG, 262 NODE_SPI_1, NODE_TTC_1, NODE_UART_1, NODE_TRACE), 263 PINMUX_MAP(62, NODE_ETH_2, NODE_USB_0, NODE_UNKNOWN, NODE_UNKNOWN, 264 NODE_UNKNOWN, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_SWDT_0, 265 NODE_SPI_1, NODE_TTC_0, NODE_UART_0, NODE_TRACE), 266 PINMUX_MAP(63, NODE_ETH_2, NODE_USB_0, NODE_UNKNOWN, NODE_UNKNOWN, 267 NODE_UNKNOWN, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_SWDT_0, 268 NODE_SPI_1, NODE_TTC_0, NODE_UART_0, NODE_TRACE), 269 PINMUX_MAP(64, NODE_ETH_3, NODE_USB_1, NODE_SD_0, NODE_UNKNOWN, 270 NODE_UNKNOWN, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_SWDT_1, 271 NODE_SPI_0, NODE_TTC_3, NODE_UART_1, NODE_TRACE), 272 PINMUX_MAP(65, NODE_ETH_3, NODE_USB_1, NODE_SD_0, NODE_UNKNOWN, 273 NODE_UNKNOWN, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_SWDT_1, 274 NODE_SPI_0, NODE_TTC_3, NODE_UART_1, NODE_TRACE), 275 PINMUX_MAP(66, NODE_ETH_3, NODE_USB_1, NODE_SD_0, NODE_UNKNOWN, 276 NODE_UNKNOWN, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_SWDT_0, 277 NODE_SPI_0, NODE_TTC_2, NODE_UART_0, NODE_TRACE), 278 PINMUX_MAP(67, NODE_ETH_3, NODE_USB_1, NODE_SD_0, NODE_UNKNOWN, 279 NODE_UNKNOWN, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_SWDT_0, 280 NODE_SPI_0, NODE_TTC_2, NODE_UART_0, NODE_TRACE), 281 PINMUX_MAP(68, NODE_ETH_3, NODE_USB_1, NODE_SD_0, NODE_UNKNOWN, 282 NODE_UNKNOWN, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_SWDT_1, 283 NODE_SPI_0, NODE_TTC_1, NODE_UART_1, NODE_TRACE), 284 PINMUX_MAP(69, NODE_ETH_3, NODE_USB_1, NODE_SD_0, NODE_SD_1, 285 NODE_UNKNOWN, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_SWDT_1, 286 NODE_SPI_0, NODE_TTC_1, NODE_UART_1, NODE_TRACE), 287 PINMUX_MAP(70, NODE_ETH_3, NODE_USB_1, NODE_SD_0, NODE_SD_1, 288 NODE_UNKNOWN, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_SWDT_0, 289 NODE_SPI_1, NODE_TTC_0, NODE_UART_0, NODE_UNKNOWN), 290 PINMUX_MAP(71, NODE_ETH_3, NODE_USB_1, NODE_SD_0, NODE_SD_1, 291 NODE_UNKNOWN, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_SWDT_0, 292 NODE_SPI_1, NODE_TTC_0, NODE_UART_0, NODE_UNKNOWN), 293 PINMUX_MAP(72, NODE_ETH_3, NODE_USB_1, NODE_SD_0, NODE_SD_1, 294 NODE_UNKNOWN, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_SWDT_1, 295 NODE_SPI_1, NODE_UNKNOWN, NODE_UART_1, NODE_UNKNOWN), 296 PINMUX_MAP(73, NODE_ETH_3, NODE_USB_1, NODE_SD_0, NODE_SD_1, 297 NODE_UNKNOWN, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_SWDT_1, 298 NODE_SPI_1, NODE_UNKNOWN, NODE_UART_1, NODE_UNKNOWN), 299 PINMUX_MAP(74, NODE_ETH_3, NODE_USB_1, NODE_SD_0, NODE_SD_1, 300 NODE_UNKNOWN, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_SWDT_0, 301 NODE_SPI_1, NODE_UNKNOWN, NODE_UART_0, NODE_UNKNOWN), 302 PINMUX_MAP(75, NODE_ETH_3, NODE_USB_1, NODE_SD_0, NODE_SD_1, 303 NODE_UNKNOWN, NODE_GPIO, NODE_CAN_0, NODE_I2C_0, NODE_SWDT_0, 304 NODE_SPI_1, NODE_UNKNOWN, NODE_UART_0, NODE_UNKNOWN), 305 PINMUX_MAP(76, NODE_UNKNOWN, NODE_UNKNOWN, NODE_SD_0, NODE_SD_1, 306 NODE_UNKNOWN, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_ETH_0, 307 NODE_ETH_1, NODE_ETH_2, NODE_ETH_3, NODE_UNKNOWN), 308 PINMUX_MAP(77, NODE_UNKNOWN, NODE_UNKNOWN, NODE_UNKNOWN, NODE_SD_1, 309 NODE_UNKNOWN, NODE_GPIO, NODE_CAN_1, NODE_I2C_1, NODE_ETH_0, 310 NODE_ETH_1, NODE_ETH_2, NODE_ETH_3, NODE_UNKNOWN), 311 }; 312 313 /** 314 * pm_api_pinctrl_get_function() - Read function id set for the given pin 315 * @pin Pin number 316 * @nid Node ID of function currently set for given pin 317 * 318 * This function provides the function currently set for the given pin. 319 * 320 * @return Returns status, either success or error+reason 321 */ 322 enum pm_ret_status pm_api_pinctrl_get_function(unsigned int pin, 323 enum pm_node_id *nid) 324 { 325 struct pm_pinctrl_pinmux_map *pinmux_map = &pinmux_maps[pin]; 326 int i, ret = PM_RET_SUCCESS; 327 unsigned int reg, val; 328 329 reg = IOU_SLCR_BASEADDR + 4 * pin; 330 ret = pm_mmio_read(reg, &val); 331 if (ret) 332 return ret; 333 334 val &= PINCTRL_FUNCTION_MASK; 335 336 for (i = 0; i < NFUNCS_PER_PIN; i++) 337 if (val == pm_pinctrl_mux[i]) 338 break; 339 340 if (i == NFUNCS_PER_PIN) 341 return PM_RET_ERROR_NOTSUPPORTED; 342 343 *nid = pinmux_map->funcs[i]; 344 345 return ret; 346 } 347 348 /** 349 * pm_api_pinctrl_set_function() - Set function id set for the given pin 350 * @pin Pin number 351 * @nid Node ID of function to set for given pin 352 * 353 * This function provides the function currently set for the given pin. 354 * 355 * @return Returns status, either success or error+reason 356 */ 357 enum pm_ret_status pm_api_pinctrl_set_function(unsigned int pin, 358 enum pm_node_id nid) 359 { 360 struct pm_pinctrl_pinmux_map *pinmux_map = &pinmux_maps[pin]; 361 int i; 362 unsigned int reg, val; 363 364 for (i = 0; i < NFUNCS_PER_PIN; i++) 365 if (nid == pinmux_map->funcs[i]) 366 break; 367 368 if (i == NFUNCS_PER_PIN) 369 return PM_RET_ERROR_NOTSUPPORTED; 370 371 reg = IOU_SLCR_BASEADDR + 4 * pin; 372 val = pm_pinctrl_mux[i]; 373 374 return pm_mmio_write(reg, PINCTRL_FUNCTION_MASK, val); 375 } 376 377 /** 378 * pm_api_pinctrl_set_config() - Set configuration parameter for given pin 379 * @pin: Pin for which configuration is to be set 380 * @param: Configuration parameter to be set 381 * @value: Value to be set for configuration parameter 382 * 383 * This function sets value of requested configuration parameter for given pin. 384 * 385 * @return Returns status, either success or error+reason 386 */ 387 enum pm_ret_status pm_api_pinctrl_set_config(unsigned int pin, 388 unsigned int param, 389 unsigned int value) 390 { 391 int ret; 392 unsigned int reg, mask, val, offset; 393 394 if (param >= PINCTRL_CONFIG_MAX) 395 return PM_RET_ERROR_NOTSUPPORTED; 396 397 if (pin >= PINCTRL_NUM_MIOS) 398 return PM_RET_ERROR_ARGS; 399 400 mask = 1 << PINCTRL_PIN_OFFSET(pin); 401 402 switch (param) { 403 case PINCTRL_CONFIG_SLEW_RATE: 404 if (value != PINCTRL_SLEW_RATE_FAST && 405 value != PINCTRL_SLEW_RATE_SLOW) 406 return PM_RET_ERROR_ARGS; 407 408 reg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR, 409 PINCTRL_SLEWCTRL_REG_OFFSET, 410 pin); 411 val = value << PINCTRL_PIN_OFFSET(pin); 412 ret = pm_mmio_write(reg, mask, val); 413 break; 414 case PINCTRL_CONFIG_BIAS_STATUS: 415 if (value != PINCTRL_BIAS_ENABLE && 416 value != PINCTRL_BIAS_DISABLE) 417 return PM_RET_ERROR_ARGS; 418 419 reg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR, 420 PINCTRL_PULLSTAT_REG_OFFSET, 421 pin); 422 423 offset = PINCTRL_PIN_OFFSET(pin); 424 if (reg == IOU_SLCR_BANK1_CTRL5) 425 offset = (offset < 12) ? (offset + 14) : (offset - 12); 426 427 val = value << offset; 428 mask = 1 << offset; 429 ret = pm_mmio_write(reg, mask, val); 430 break; 431 case PINCTRL_CONFIG_PULL_CTRL: 432 433 if (value != PINCTRL_BIAS_PULL_DOWN && 434 value != PINCTRL_BIAS_PULL_UP) 435 return PM_RET_ERROR_ARGS; 436 437 reg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR, 438 PINCTRL_PULLSTAT_REG_OFFSET, 439 pin); 440 441 offset = PINCTRL_PIN_OFFSET(pin); 442 if (reg == IOU_SLCR_BANK1_CTRL5) 443 offset = (offset < 12) ? (offset + 14) : (offset - 12); 444 445 val = PINCTRL_BIAS_ENABLE << offset; 446 ret = pm_mmio_write(reg, 1 << offset, val); 447 if (ret) 448 return ret; 449 450 reg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR, 451 PINCTRL_PULLCTRL_REG_OFFSET, 452 pin); 453 val = value << PINCTRL_PIN_OFFSET(pin); 454 ret = pm_mmio_write(reg, mask, val); 455 break; 456 case PINCTRL_CONFIG_SCHMITT_CMOS: 457 if (value != PINCTRL_INPUT_TYPE_CMOS && 458 value != PINCTRL_INPUT_TYPE_SCHMITT) 459 return PM_RET_ERROR_ARGS; 460 461 reg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR, 462 PINCTRL_SCHCMOS_REG_OFFSET, 463 pin); 464 465 val = value << PINCTRL_PIN_OFFSET(pin); 466 ret = pm_mmio_write(reg, mask, val); 467 break; 468 case PINCTRL_CONFIG_DRIVE_STRENGTH: 469 if (value > PINCTRL_DRIVE_STRENGTH_12MA) 470 return PM_RET_ERROR_ARGS; 471 472 reg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR, 473 PINCTRL_DRVSTRN0_REG_OFFSET, 474 pin); 475 val = (value >> 1) << PINCTRL_PIN_OFFSET(pin); 476 ret = pm_mmio_write(reg, mask, val); 477 if (ret) 478 return ret; 479 480 reg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR, 481 PINCTRL_DRVSTRN1_REG_OFFSET, 482 pin); 483 val = (value & 0x01) << PINCTRL_PIN_OFFSET(pin); 484 ret = pm_mmio_write(reg, mask, val); 485 break; 486 default: 487 ERROR("Invalid parameter %u\n", param); 488 ret = PM_RET_ERROR_NOTSUPPORTED; 489 break; 490 } 491 492 return ret; 493 } 494 495 /** 496 * pm_api_pinctrl_get_config() - Get configuration parameter value for given pin 497 * @pin: Pin for which configuration is to be read 498 * @param: Configuration parameter to be read 499 * @value: buffer to store value of configuration parameter 500 * 501 * This function reads value of requested configuration parameter for given pin. 502 * 503 * @return Returns status, either success or error+reason 504 */ 505 enum pm_ret_status pm_api_pinctrl_get_config(unsigned int pin, 506 unsigned int param, 507 unsigned int *value) 508 { 509 int ret; 510 unsigned int reg, val; 511 512 if (param >= PINCTRL_CONFIG_MAX) 513 return PM_RET_ERROR_NOTSUPPORTED; 514 515 if (pin >= PINCTRL_NUM_MIOS) 516 return PM_RET_ERROR_ARGS; 517 518 switch (param) { 519 case PINCTRL_CONFIG_SLEW_RATE: 520 reg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR, 521 PINCTRL_SLEWCTRL_REG_OFFSET, 522 pin); 523 524 ret = pm_mmio_read(reg, &val); 525 if (ret) 526 return ret; 527 528 *value = PINCTRL_REGVAL_TO_PIN_CONFIG(pin, val); 529 break; 530 case PINCTRL_CONFIG_BIAS_STATUS: 531 reg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR, 532 PINCTRL_PULLSTAT_REG_OFFSET, 533 pin); 534 535 ret = pm_mmio_read(reg, &val); 536 if (ret) 537 return ret; 538 539 if (reg == IOU_SLCR_BANK1_CTRL5) 540 val = ((val & 0x3FFF) << 12) | ((val >> 14) & 0xFFF); 541 542 *value = PINCTRL_REGVAL_TO_PIN_CONFIG(pin, val); 543 break; 544 case PINCTRL_CONFIG_PULL_CTRL: 545 546 reg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR, 547 PINCTRL_PULLCTRL_REG_OFFSET, 548 pin); 549 550 ret = pm_mmio_read(reg, &val); 551 if (ret) 552 return ret; 553 554 *value = PINCTRL_REGVAL_TO_PIN_CONFIG(pin, val); 555 break; 556 case PINCTRL_CONFIG_SCHMITT_CMOS: 557 reg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR, 558 PINCTRL_SCHCMOS_REG_OFFSET, 559 pin); 560 561 ret = pm_mmio_read(reg, &val); 562 if (ret) 563 return ret; 564 565 *value = PINCTRL_REGVAL_TO_PIN_CONFIG(pin, val); 566 break; 567 case PINCTRL_CONFIG_DRIVE_STRENGTH: 568 reg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR, 569 PINCTRL_DRVSTRN0_REG_OFFSET, 570 pin); 571 ret = pm_mmio_read(reg, &val); 572 if (ret) 573 return ret; 574 575 *value = PINCTRL_REGVAL_TO_PIN_CONFIG(pin, val) << 1; 576 577 reg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR, 578 PINCTRL_DRVSTRN1_REG_OFFSET, 579 pin); 580 ret = pm_mmio_read(reg, &val); 581 if (ret) 582 return ret; 583 584 *value |= PINCTRL_REGVAL_TO_PIN_CONFIG(pin, val); 585 break; 586 case PINCTRL_CONFIG_VOLTAGE_STATUS: 587 reg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR, 588 PINCTRL_VOLTAGE_STAT_REG_OFFSET, 589 pin); 590 591 ret = pm_mmio_read(reg, &val); 592 if (ret) 593 return ret; 594 595 *value = val & PINCTRL_VOLTAGE_STATUS_MASK; 596 break; 597 default: 598 return PM_RET_ERROR_NOTSUPPORTED; 599 } 600 601 return 0; 602 } 603