1/* 2 * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6#include <arch.h> 7#include <asm_macros.S> 8#include <bl_common.h> 9#include <cortex_a73.h> 10#include <cpu_macros.S> 11#include <plat_macros.S> 12 13 /* --------------------------------------------- 14 * Disable L1 data cache 15 * --------------------------------------------- 16 */ 17func cortex_a73_disable_dcache 18 mrs x1, sctlr_el3 19 bic x1, x1, #SCTLR_C_BIT 20 msr sctlr_el3, x1 21 isb 22 ret 23endfunc cortex_a73_disable_dcache 24 25 /* --------------------------------------------- 26 * Disable intra-cluster coherency 27 * --------------------------------------------- 28 */ 29func cortex_a73_disable_smp 30 mrs x0, CORTEX_A73_CPUECTLR_EL1 31 bic x0, x0, #CORTEX_A73_CPUECTLR_SMP_BIT 32 msr CORTEX_A73_CPUECTLR_EL1, x0 33 isb 34 dsb sy 35 ret 36endfunc cortex_a73_disable_smp 37 38func cortex_a73_reset_func 39#if IMAGE_BL31 && WORKAROUND_CVE_2017_5715 40 cpu_check_csv2 x0, 1f 41 adr x0, workaround_bpiall_vbar0_runtime_exceptions 42 msr vbar_el3, x0 431: 44#endif 45 46 /* --------------------------------------------- 47 * Enable the SMP bit. 48 * Clobbers : x0 49 * --------------------------------------------- 50 */ 51 mrs x0, CORTEX_A73_CPUECTLR_EL1 52 orr x0, x0, #CORTEX_A73_CPUECTLR_SMP_BIT 53 msr CORTEX_A73_CPUECTLR_EL1, x0 54 isb 55 ret 56endfunc cortex_a73_reset_func 57 58func cortex_a73_core_pwr_dwn 59 mov x18, x30 60 61 /* --------------------------------------------- 62 * Turn off caches. 63 * --------------------------------------------- 64 */ 65 bl cortex_a73_disable_dcache 66 67 /* --------------------------------------------- 68 * Flush L1 caches. 69 * --------------------------------------------- 70 */ 71 mov x0, #DCCISW 72 bl dcsw_op_level1 73 74 /* --------------------------------------------- 75 * Come out of intra cluster coherency 76 * --------------------------------------------- 77 */ 78 mov x30, x18 79 b cortex_a73_disable_smp 80endfunc cortex_a73_core_pwr_dwn 81 82func cortex_a73_cluster_pwr_dwn 83 mov x18, x30 84 85 /* --------------------------------------------- 86 * Turn off caches. 87 * --------------------------------------------- 88 */ 89 bl cortex_a73_disable_dcache 90 91 /* --------------------------------------------- 92 * Flush L1 caches. 93 * --------------------------------------------- 94 */ 95 mov x0, #DCCISW 96 bl dcsw_op_level1 97 98 /* --------------------------------------------- 99 * Disable the optional ACP. 100 * --------------------------------------------- 101 */ 102 bl plat_disable_acp 103 104 /* --------------------------------------------- 105 * Flush L2 caches. 106 * --------------------------------------------- 107 */ 108 mov x0, #DCCISW 109 bl dcsw_op_level2 110 111 /* --------------------------------------------- 112 * Come out of intra cluster coherency 113 * --------------------------------------------- 114 */ 115 mov x30, x18 116 b cortex_a73_disable_smp 117endfunc cortex_a73_cluster_pwr_dwn 118 119func check_errata_cve_2017_5715 120 cpu_check_csv2 x0, 1f 121#if WORKAROUND_CVE_2017_5715 122 mov x0, #ERRATA_APPLIES 123#else 124 mov x0, #ERRATA_MISSING 125#endif 126 ret 1271: 128 mov x0, #ERRATA_NOT_APPLIES 129 ret 130endfunc check_errata_cve_2017_5715 131 132#if REPORT_ERRATA 133/* 134 * Errata printing function for Cortex A75. Must follow AAPCS. 135 */ 136func cortex_a73_errata_report 137 stp x8, x30, [sp, #-16]! 138 139 bl cpu_get_rev_var 140 mov x8, x0 141 142 /* 143 * Report all errata. The revision-variant information is passed to 144 * checking functions of each errata. 145 */ 146 report_errata WORKAROUND_CVE_2017_5715, cortex_a73, cve_2017_5715 147 148 ldp x8, x30, [sp], #16 149 ret 150endfunc cortex_a73_errata_report 151#endif 152 153 /* --------------------------------------------- 154 * This function provides cortex_a73 specific 155 * register information for crash reporting. 156 * It needs to return with x6 pointing to 157 * a list of register names in ascii and 158 * x8 - x15 having values of registers to be 159 * reported. 160 * --------------------------------------------- 161 */ 162.section .rodata.cortex_a73_regs, "aS" 163cortex_a73_regs: /* The ascii list of register names to be reported */ 164 .asciz "cpuectlr_el1", "l2merrsr_el1", "" 165 166func cortex_a73_cpu_reg_dump 167 adr x6, cortex_a73_regs 168 mrs x8, CORTEX_A73_CPUECTLR_EL1 169 mrs x9, CORTEX_A73_L2MERRSR_EL1 170 ret 171endfunc cortex_a73_cpu_reg_dump 172 173declare_cpu_ops_workaround_cve_2017_5715 cortex_a73, CORTEX_A73_MIDR, \ 174 cortex_a73_reset_func, \ 175 check_errata_cve_2017_5715, \ 176 cortex_a73_core_pwr_dwn, \ 177 cortex_a73_cluster_pwr_dwn 178