ti: k3: drivers: sec_proxy: Allow clearing a Secure Proxy receive thread

It can be needed to discard all messages in a receive queue. This
can be used during some error recovery situations.

Signed-

ti: k3: drivers: sec_proxy: Allow clearing a Secure Proxy receive thread

It can be needed to discard all messages in a receive queue. This
can be used during some error recovery situations.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>

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ti: k3: common: Use shutdown API for PSCI core poweroff

To ensure WFI is reached before the PSC is trigger to power-down
a processor, the shutdonw API must be used.

Signed-off-by: Andrew F. Davis <

ti: k3: common: Use shutdown API for PSCI core poweroff

To ensure WFI is reached before the PSC is trigger to power-down
a processor, the shutdonw API must be used.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>

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ti: k3: drivers: ti_sci: Add processor shutdown API

This is a pseudo-API command consisting of a wait processor status
command and a set device state command queued back-to-back without
waiting for

ti: k3: drivers: ti_sci: Add processor shutdown API

This is a pseudo-API command consisting of a wait processor status
command and a set device state command queued back-to-back without
waiting for the System Firmware to ACK either message.

This is needed as the K3 power down specification states the System
Firmware must wait for a processor to be in WFI/WFE before powering
it down. The current implementation of System Firmware does not provide
such a command. Also given that with PSCI the core to be shutdown is the
core that is processing the shutdown request, the core cannot itself wait
for its own WFI/WFE status. To workaround this limitation, we submit
a wait processor status command followed by the actual shutdown command.
The shutdown command will not be processed until the wait command has
finished. In this way we can continue to WFI before the wait command
status has been met or timed-out and the shutdown command is processed.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>

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ti: k3: drivers: ti_sci: Add processor status wait API

This TI-SCI API can be used wait for a set of processor status flags to
be set or cleared. The flags are processor type specific. This command

ti: k3: drivers: ti_sci: Add processor status wait API

This TI-SCI API can be used wait for a set of processor status flags to
be set or cleared. The flags are processor type specific. This command
will not return ACK until the specified status is met. NACK will be
returned after the timeout elapses or on error.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>

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ti: k3: drivers: sec_proxy: Switch error messages

The logic is correct here, but the error messages are
reversed, switch them.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Acked-by: Nishanth Menon <

ti: k3: drivers: sec_proxy: Switch error messages

The logic is correct here, but the error messages are
reversed, switch them.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>

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Merge pull request #1764 from vwadekar/tf2.0-tegra-downstream-rebase-1.7.19

Tf2.0 tegra downstream rebase 1.7.19

Tegra: memctrl: clean MC INT status before exit to bootloader

This patch cleans the Memory controller's interrupt status
register, before exiting to the non-secure world during
cold boot. This is re

Tegra: memctrl: clean MC INT status before exit to bootloader

This patch cleans the Memory controller's interrupt status
register, before exiting to the non-secure world during
cold boot. This is required as we observed that the MC's
arbitration bit is set before exiting the secure world.

Change-Id: Iacd01994d03b3b9cbd7b8a57fe7ab5b04e607a9f
Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>

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Tegra: use 'PLATFORM_MAX_CPUS_PER_CLUSTER' to calculate core position

This patch updates the plat_my_core_pos() and platform_get_core_pos() helper
functions to use the `PLATFORM_MAX_CPUS_PER_CLUSTER

Tegra: use 'PLATFORM_MAX_CPUS_PER_CLUSTER' to calculate core position

This patch updates the plat_my_core_pos() and platform_get_core_pos() helper
functions to use the `PLATFORM_MAX_CPUS_PER_CLUSTER` macro to calculate the
core position.

core_pos = CoreId + (ClusterId * PLATFORM_MAX_CPUS_PER_CLUSTER)

Change-Id: Ic49f2fc7ded23bf9484c8fe104025df8884b9faf
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: memctrl_v2: pack TZDRAM base into SCRATCH54_LO

This patch moves the TZDRAM base address to SCRATCH55_LO due
to security concerns. The HI and LO address bits are packed
into SCRATCH55_LO for t

Tegra: memctrl_v2: pack TZDRAM base into SCRATCH54_LO

This patch moves the TZDRAM base address to SCRATCH55_LO due
to security concerns. The HI and LO address bits are packed
into SCRATCH55_LO for the warmboot firmware to restore.
SCRATCH54_HI is still being used for backward compatibility,
but would be removed eventually.

The scratch registers are populated as:
* RSV55_0 = CFG1[12:0] | CFG0[31:20]
* RSV55_1 = CFG3[1:0]
* RSV54_1 = CFG1[12:0]

Change-Id: Idc20d165d8117488010fcc8dfd946f7ad475da58
Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>

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Tegra: bpmp: Increase timeout to 2ms

To deal with upcoming EMC periodic compensation, increase the BPMP timeout
to 2ms.

Change-Id: I8572c031168defd15504d905c4d625f44dd7fa3d
Signed-off-by: Peter De

Tegra: bpmp: Increase timeout to 2ms

To deal with upcoming EMC periodic compensation, increase the BPMP timeout
to 2ms.

Change-Id: I8572c031168defd15504d905c4d625f44dd7fa3d
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>

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Tegra: remove duplicate code from CPU's power on path

This patch removes duplicate code from the CPU's power on path. The removed
code is already present as part of PSCI's power on logic.

Change-Id

Tegra: remove duplicate code from CPU's power on path

This patch removes duplicate code from the CPU's power on path. The removed
code is already present as part of PSCI's power on logic.

Change-Id: I4d18a605b219570c6bf997b9e6be6e7853ebf5cd
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: enable 'WARMBOOT_ENABLE_DCACHE_EARLY' flag

This patch enables the 'WARMBOOT_ENABLE_DCACHE_EARLY' flag to enable
D-cache early, during the CPU warmboot sequence. This flag is applicable
for pl

Tegra: enable 'WARMBOOT_ENABLE_DCACHE_EARLY' flag

This patch enables the 'WARMBOOT_ENABLE_DCACHE_EARLY' flag to enable
D-cache early, during the CPU warmboot sequence. This flag is applicable
for platforms like Tegra, which do not require interconnect programming to
enable cache coherency.

Change-Id: Id39471cf0922799960d8f1de6e5e0d605a53f7ca
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra210_B01: SC7: Select RNG mode based on ECID

If ECID is valid, we can use force instantiation
otherwise, we should use reseed for random data
generation for RNG operations in SE context save
DNI

Tegra210_B01: SC7: Select RNG mode based on ECID

If ECID is valid, we can use force instantiation
otherwise, we should use reseed for random data
generation for RNG operations in SE context save
DNI because we are not keeping software save
sequence in main.

Change-Id: I73d650e6f45db17b780834b8de4c10501e05c8f3
Signed-off-by: Samuel Payne <spayne@nvidia.com>

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Tegra: trusty: pass profiling base to Trusted OS

* Previous boot loader passes Shared DRAM address
to be used by Trusted OS to dump its boot timing records
* This patch adds support to pass the pa

Tegra: trusty: pass profiling base to Trusted OS

* Previous boot loader passes Shared DRAM address
to be used by Trusted OS to dump its boot timing records
* This patch adds support to pass the parameter
to Trusted OS during cold boot

Change-Id: I9f95bb6de80b1bbd2d2d6ec42619f895d911b8ed
Signed-off-by: Akshay Sharan <asharan@nvidia.com>

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Tegra210B01: SE/SE2 and PKA1 context save (SW)

This change ports the software based SE context save routines.
The software implements the context save sequence for SE/SE2 and
PKA1. The context save

Tegra210B01: SE/SE2 and PKA1 context save (SW)

This change ports the software based SE context save routines.
The software implements the context save sequence for SE/SE2 and
PKA1. The context save routine is intended to be invoked from
the ATF SC7 entry.

Change-Id: I9aa156d6e7e22a394bb10cb0c3b05fc303f08807
Signed-off-by: Marvin Hsu <marvinh@nvidia.com>

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Tegra: memctrl: assert if dynamic memmap fails

This patch adds an assert in case the dynamic memmap routine fails.

Change-Id: Idd20debbb8944340f5928c6f2cfea973a63a7b1c
Signed-off-by: Varun Wadekar

Tegra: memctrl: assert if dynamic memmap fails

This patch adds an assert in case the dynamic memmap routine fails.

Change-Id: Idd20debbb8944340f5928c6f2cfea973a63a7b1c
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: set PLAT_LOG_LEVEL_ASSERT macro to LOG_LEVEL_INFO

This patch enables prints from asserts() for release/debug builds
on all Tegra platforms.

Change-Id: Ie256437a325a7c5015a10f55aba2287a91b57b

Tegra: set PLAT_LOG_LEVEL_ASSERT macro to LOG_LEVEL_INFO

This patch enables prints from asserts() for release/debug builds
on all Tegra platforms.

Change-Id: Ie256437a325a7c5015a10f55aba2287a91b57bca
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra210: increase number of dynamic memory mappings

This patch increases the MAX_MMAP_REGIONS build flag to allow
Tegra210 platforms to dynamically map multiple memory apertures
at the same time. T

Tegra210: increase number of dynamic memory mappings

This patch increases the MAX_MMAP_REGIONS build flag to allow
Tegra210 platforms to dynamically map multiple memory apertures
at the same time. This takes care of scenarios when we get multiple
requests to memmap memory apertures at the same time.

Change-Id: If4fe23b454e7d588e35acfbf024b9ccbb3daccc7
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: lib: library for profiling the cold boot path

The non secure world would like to profile the boot path for
the EL3 and S-EL1 firmwares. To allow it to do that, a non-secure
DRAM region (4K) i

Tegra: lib: library for profiling the cold boot path

The non secure world would like to profile the boot path for
the EL3 and S-EL1 firmwares. To allow it to do that, a non-secure
DRAM region (4K) is allocated and the base address is passed to
the EL3 firmware.

This patch adds a library to allow the platform code to store the
tag:timestamp pair to the shared memory. The tegra platform code
then uses the `record` method to add timestamps.

Original change by Akshay Sharan <asharan@nvidia.com>

Change-Id: Idbbef9c83ed84a508b04d85a6637775960dc94ba
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: sanity check non-secure DRAM address

This patch fixes the logic to validate if a non-secure memory address
overlaps the TZDRAM memory aperture.

Change-Id: I68af7dc6acc705d7b0ee9161c400237607

Tegra: sanity check non-secure DRAM address

This patch fixes the logic to validate if a non-secure memory address
overlaps the TZDRAM memory aperture.

Change-Id: I68af7dc6acc705d7b0ee9161c4002376077b46b1
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: fix defects flagged by MISRA Rule 10.3

MISRA Rule 10.3, the value of an expression shall not be assigned to
an object with a narrower essential type or of a different essential
type category.

Tegra: fix defects flagged by MISRA Rule 10.3

MISRA Rule 10.3, the value of an expression shall not be assigned to
an object with a narrower essential type or of a different essential
type category.

The essential type of a enum member is anonymous enum, the enum member
should be casted to the right type when using it.

Both UL and ULL suffix equal to uint64_t constant in compiler
aarch64-linux-gnu-gcc, to avoid confusing, only keep U and ULL suffix
in platform code. So in some case, cast a constant to uint32_t is
necessary.

Change-Id: I1aae8cba81ef47481736e7f95f53570de7013187
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>

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Tegra210: save TZSRAM context from the "_wfi" handler

This patch saves the TZSRAM context and takes the SoC into System Suspend
from the "_wfi" handler. This helps us save the entire CPU context fro

Tegra210: save TZSRAM context from the "_wfi" handler

This patch saves the TZSRAM context and takes the SoC into System Suspend
from the "_wfi" handler. This helps us save the entire CPU context from
the TZSRAM, before entering System Suspend. In the previous implementation
we missed saving some part of the state machine context leading to an assert
on System Suspend exit.

Change-Id: I4895a8b4a5e3c3e983c245746ea388e42da8229c
Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>

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Tegra210: se: enable entropy/SE clocks before system suspend

This patch enables clocks to the SE and Entropy block and gets them
out of reset, before starting the context save operation.

Change-Id:

Tegra210: se: enable entropy/SE clocks before system suspend

This patch enables clocks to the SE and Entropy block and gets them
out of reset, before starting the context save operation.

Change-Id: Ic196be8fb833dfd04c0e8d460c07058429999613
Signed-off-by: Samuel Payne <spayne@nvidia.com>

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Tegra: smmu: add a hook to get number of devices

This patch adds a hook to get the number of smmu devices and
removes the NUM_SMMU_DEVICES macro.

Change-Id: Ia8dba7e9304224976b5da688b9e4b5438f11cc4

Tegra: smmu: add a hook to get number of devices

This patch adds a hook to get the number of smmu devices and
removes the NUM_SMMU_DEVICES macro.

Change-Id: Ia8dba7e9304224976b5da688b9e4b5438f11cc41
Signed-off-by: Steven Kao <skao@nvidia.com>

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Tegra: common: fix defects flagged by MISRA scan

Macro assert(e) request 'e' is a bool type, if useing other
type, MISRA report a "The Essential Type Model" violation,
Add a judgement to fix the def

Tegra: common: fix defects flagged by MISRA scan

Macro assert(e) request 'e' is a bool type, if useing other
type, MISRA report a "The Essential Type Model" violation,
Add a judgement to fix the defects, if 'e' is not bool type.

Remove unused code [Rule 2.5]
Fix the essential type model violation [Rule 10.6, 10.7]
Use local parameter to raplace function parameter [Rule 17.8]

Change-Id: Ifce932addbb0a4b063ef6b38349d886c051d81c0
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>

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