xref: /rk3399_ARM-atf/plat/nvidia/tegra/include/drivers/flowctrl.h (revision 2ed09b1ee2a3c9d6e19f067e0bdf5af1d4f59114)
1 /*
2  * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef FLOWCTRL_H
8 #define FLOWCTRL_H
9 
10 #include <lib/mmio.h>
11 
12 #include <tegra_def.h>
13 
14 #define FLOWCTRL_HALT_CPU0_EVENTS	0x0U
15 #define  FLOWCTRL_WAITEVENT		(2U << 29)
16 #define  FLOWCTRL_WAIT_FOR_INTERRUPT	(4U << 29)
17 #define  FLOWCTRL_JTAG_RESUME		(1U << 28)
18 #define  FLOWCTRL_HALT_SCLK		(1U << 27)
19 #define  FLOWCTRL_HALT_LIC_IRQ		(1U << 11)
20 #define  FLOWCTRL_HALT_LIC_FIQ		(1U << 10)
21 #define  FLOWCTRL_HALT_GIC_IRQ		(1U << 9)
22 #define  FLOWCTRL_HALT_GIC_FIQ		(1U << 8)
23 #define FLOWCTRL_HALT_BPMP_EVENTS	0x4U
24 #define FLOWCTRL_CPU0_CSR		0x8U
25 #define  FLOW_CTRL_CSR_PWR_OFF_STS	(1U << 16)
26 #define  FLOWCTRL_CSR_INTR_FLAG		(1U << 15)
27 #define  FLOWCTRL_CSR_EVENT_FLAG	(1U << 14)
28 #define  FLOWCTRL_CSR_IMMEDIATE_WAKE	(1U << 3)
29 #define  FLOWCTRL_CSR_ENABLE		(1U << 0)
30 #define FLOWCTRL_HALT_CPU1_EVENTS	0x14U
31 #define FLOWCTRL_CPU1_CSR		0x18U
32 #define FLOW_CTLR_FLOW_DBG_QUAL		0x50U
33 #define  FLOWCTRL_FIQ2CCPLEX_ENABLE	(1U << 28)
34 #define FLOWCTRL_CC4_CORE0_CTRL		0x6cU
35 #define FLOWCTRL_WAIT_WFI_BITMAP	0x100U
36 #define FLOWCTRL_L2_FLUSH_CONTROL	0x94U
37 #define FLOWCTRL_BPMP_CLUSTER_CONTROL	0x98U
38 #define  FLOWCTRL_BPMP_CLUSTER_PWRON_LOCK	(1U << 2)
39 
40 #define FLOWCTRL_ENABLE_EXT		12U
41 #define FLOWCTRL_ENABLE_EXT_MASK	3U
42 #define FLOWCTRL_PG_CPU_NONCPU		0x1U
43 #define FLOWCTRL_TURNOFF_CPURAIL	0x2U
44 
45 static inline uint32_t tegra_fc_read_32(uint32_t off)
46 {
47 	return mmio_read_32(TEGRA_FLOWCTRL_BASE + off);
48 }
49 
50 static inline void tegra_fc_write_32(uint32_t off, uint32_t val)
51 {
52 	mmio_write_32(TEGRA_FLOWCTRL_BASE + off, val);
53 }
54 
55 void tegra_fc_cluster_idle(uint32_t midr);
56 void tegra_fc_cpu_powerdn(uint32_t mpidr);
57 void tegra_fc_cluster_powerdn(uint32_t midr);
58 void tegra_fc_cpu_on(int cpu);
59 void tegra_fc_cpu_off(int cpu);
60 void tegra_fc_disable_fiq_to_ccplex_routing(void);
61 void tegra_fc_enable_fiq_to_ccplex_routing(void);
62 void tegra_fc_lock_active_cluster(void);
63 void tegra_fc_reset_bpmp(void);
64 void tegra_fc_soc_powerdn(uint32_t midr);
65 
66 #endif /* FLOWCTRL_H */
67