1 /* 2 * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <arch_helpers.h> 10 #include <bl31/interrupt_mgmt.h> 11 #include <common/bl_common.h> 12 #include <common/debug.h> 13 #include <context.h> 14 #include <denver.h> 15 #include <lib/bakery_lock.h> 16 #include <lib/el3_runtime/context_mgmt.h> 17 #include <plat/common/platform.h> 18 19 #include <tegra_def.h> 20 #include <tegra_private.h> 21 22 static DEFINE_BAKERY_LOCK(tegra_fiq_lock); 23 24 /******************************************************************************* 25 * Static variables 26 ******************************************************************************/ 27 static uint64_t ns_fiq_handler_addr; 28 static uint32_t fiq_handler_active; 29 static pcpu_fiq_state_t fiq_state[PLATFORM_CORE_COUNT]; 30 31 /******************************************************************************* 32 * Handler for FIQ interrupts 33 ******************************************************************************/ 34 static uint64_t tegra_fiq_interrupt_handler(uint32_t id, 35 uint32_t flags, 36 void *handle, 37 void *cookie) 38 { 39 cpu_context_t *ctx = cm_get_context(NON_SECURE); 40 el3_state_t *el3state_ctx = get_el3state_ctx(ctx); 41 uint32_t cpu = plat_my_core_pos(); 42 uint32_t irq; 43 44 (void)id; 45 (void)flags; 46 (void)handle; 47 (void)cookie; 48 49 /* 50 * Read the pending interrupt ID 51 */ 52 irq = plat_ic_get_pending_interrupt_id(); 53 54 bakery_lock_get(&tegra_fiq_lock); 55 56 /* 57 * Jump to NS world only if the NS world's FIQ handler has 58 * been registered 59 */ 60 if (ns_fiq_handler_addr != 0U) { 61 62 /* 63 * The FIQ was generated when the execution was in the non-secure 64 * world. Save the context registers to start with. 65 */ 66 cm_el1_sysregs_context_save(NON_SECURE); 67 68 /* 69 * Save elr_el3 and spsr_el3 from the saved context, and overwrite 70 * the context with the NS fiq_handler_addr and SPSR value. 71 */ 72 fiq_state[cpu].elr_el3 = read_ctx_reg((el3state_ctx), (uint32_t)(CTX_ELR_EL3)); 73 fiq_state[cpu].spsr_el3 = read_ctx_reg((el3state_ctx), (uint32_t)(CTX_SPSR_EL3)); 74 75 /* 76 * Set the new ELR to continue execution in the NS world using the 77 * FIQ handler registered earlier. 78 */ 79 cm_set_elr_el3(NON_SECURE, ns_fiq_handler_addr); 80 } 81 82 /* 83 * Mark this interrupt as complete to avoid a FIQ storm. 84 */ 85 if (irq < 1022U) { 86 (void)plat_ic_acknowledge_interrupt(); 87 plat_ic_end_of_interrupt(irq); 88 } 89 90 bakery_lock_release(&tegra_fiq_lock); 91 92 return 0; 93 } 94 95 /******************************************************************************* 96 * Setup handler for FIQ interrupts 97 ******************************************************************************/ 98 void tegra_fiq_handler_setup(void) 99 { 100 uint32_t flags; 101 int32_t rc; 102 103 /* return if already registered */ 104 if (fiq_handler_active == 0U) { 105 /* 106 * Register an interrupt handler for FIQ interrupts generated for 107 * NS interrupt sources 108 */ 109 flags = 0U; 110 set_interrupt_rm_flag((flags), (NON_SECURE)); 111 rc = register_interrupt_type_handler(INTR_TYPE_EL3, 112 tegra_fiq_interrupt_handler, 113 flags); 114 if (rc != 0) { 115 panic(); 116 } 117 118 /* handler is now active */ 119 fiq_handler_active = 1; 120 } 121 } 122 123 /******************************************************************************* 124 * Validate and store NS world's entrypoint for FIQ interrupts 125 ******************************************************************************/ 126 void tegra_fiq_set_ns_entrypoint(uint64_t entrypoint) 127 { 128 ns_fiq_handler_addr = entrypoint; 129 } 130 131 /******************************************************************************* 132 * Handler to return the NS EL1/EL0 CPU context 133 ******************************************************************************/ 134 int32_t tegra_fiq_get_intr_context(void) 135 { 136 cpu_context_t *ctx = cm_get_context(NON_SECURE); 137 gp_regs_t *gpregs_ctx = get_gpregs_ctx(ctx); 138 const el1_sys_regs_t *el1state_ctx = get_sysregs_ctx(ctx); 139 uint32_t cpu = plat_my_core_pos(); 140 uint64_t val; 141 142 /* 143 * We store the ELR_EL3, SPSR_EL3, SP_EL0 and SP_EL1 registers so 144 * that el3_exit() sends these values back to the NS world. 145 */ 146 write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X0), (fiq_state[cpu].elr_el3)); 147 write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X1), (fiq_state[cpu].spsr_el3)); 148 149 val = read_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_SP_EL0)); 150 write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X2), (val)); 151 152 val = read_ctx_reg((el1state_ctx), (uint32_t)(CTX_SP_EL1)); 153 write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X3), (val)); 154 155 return 0; 156 } 157