fix(plat/rcar3): fix eMMC boot support for R-Car D3

Fix to support of booting from eMMC (50MHz x 8) on
Draak board for R-Car D3.

Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com>
Signed

fix(plat/rcar3): fix eMMC boot support for R-Car D3

Fix to support of booting from eMMC (50MHz x 8) on
Draak board for R-Car D3.

Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I0ab2b5c7f8075acbf5f4a69694fb535dddc1a4c8

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fix(plat/rcar3): fix version judgment for R-Car D3

Added the process of judgment and logging for R-Car D3 Ver.1.1 and Ver.1.0.

Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com>
Signed-o

fix(plat/rcar3): fix version judgment for R-Car D3

Added the process of judgment and logging for R-Car D3 Ver.1.1 and Ver.1.0.

Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I326aa42374b70b6a4a71893561a7eaa0b6eddef0

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fix(plat/rcar3): fix source file to make about GICv2

Changed the plat/renesas/common/common.mk to change the source files
about GICv2 by include gicv2.mk, because gic_common.c has deprecated.

Signe

fix(plat/rcar3): fix source file to make about GICv2

Changed the plat/renesas/common/common.mk to change the source files
about GICv2 by include gicv2.mk, because gic_common.c has deprecated.

Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: Iaa7eae6b2c1dd79a05339325e6bc422d87bce49e

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Merge changes from topic "gic-700-auto" into integration

* changes:
feat(arm_fpga): support GICv4 images
feat(gicv3): detect GICv4 feature at runtime
feat(gicv3): multichip: detect GIC-700 at

Merge changes from topic "gic-700-auto" into integration

* changes:
feat(arm_fpga): support GICv4 images
feat(gicv3): detect GICv4 feature at runtime
feat(gicv3): multichip: detect GIC-700 at runtime
refactor(gic): move GIC IIDR numbers
refactor(gicv3): rename GIC Clayton to GIC-700

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Merge "fix(plat/marvell/a3k): enable workaround for erratum 1530924" into integration

Merge "feat(plat/st): add a new DDR firewall management" into integration

Merge changes from topic "st_fip_fconf" into integration

* changes:
refactor(plat/st): use TZC400 bindings
feat(dt-bindings): add STM32MP1 TZC400 bindings

Merge changes from topic "st_fip_fconf" into integration

* changes:
feat(plat/st): manage io_policies with FCONF
feat(fdts): add IO policies for STM32MP1

Merge changes from topic "st_fip_fconf" into integration

* changes:
feat(plat/st): use FCONF to configure platform
feat(fdts): add STM32MP1 fw-config DT files

Merge "feat(plat/st): improve FIP image loading from MMC" into integration

Merge changes from topic "st_fip_fconf" into integration

* changes:
feat(plat/st): use FIP to load images
refactor(plat/st): updates for OP-TEE
feat(lib/optee): introduce optee_header_is_valid

Merge changes from topic "st_fip_fconf" into integration

* changes:
feat(plat/st): use FIP to load images
refactor(plat/st): updates for OP-TEE
feat(lib/optee): introduce optee_header_is_valid()

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fix(plat/marvell/a3k): enable workaround for erratum 1530924

Erratum 1530924 affects Armada 37xx CPU, since it affects all Cortex-A53
revisions from r0p0 to r0p4.

Enable the workaround for this err

fix(plat/marvell/a3k): enable workaround for erratum 1530924

Erratum 1530924 affects Armada 37xx CPU, since it affects all Cortex-A53
revisions from r0p0 to r0p4.

Enable the workaround for this erratum.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: I753225040e49e956788d5617cd7ce76d5e6ea8e8

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feat(plat/st): add a new DDR firewall management

Based on FCONF framework, define DDR firewall regions
from firmware config file instead of static defines.

Change-Id: I471e15410ca286d9079a86e3dc347

feat(plat/st): add a new DDR firewall management

Based on FCONF framework, define DDR firewall regions
from firmware config file instead of static defines.

Change-Id: I471e15410ca286d9079a86e3dc3474f66d37b5ab
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>

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Merge changes from topic "advk-serror" into integration

* changes:
fix(plat/marvell/a3k): disable HANDLE_EA_EL3_FIRST by default
fix(plat/marvell/a3k): update information about PCIe abort hack

fix(plat/qti/sc7180): qti smc addition

Adding QTI SIP SMC CALL to detect qti platform supporting ARM 64 SMC
calls or not.

Signed-off-by: Saurabh Gorecha <sgorecha@codeaurora.org>
Change-Id: I323132

fix(plat/qti/sc7180): qti smc addition

Adding QTI SIP SMC CALL to detect qti platform supporting ARM 64 SMC
calls or not.

Signed-off-by: Saurabh Gorecha <sgorecha@codeaurora.org>
Change-Id: I3231325a6ffe5aa69856dd25ac2c0a2004484e4b

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Merge changes I0ae8a6ea,I0b4fc83e into integration

* changes:
feat(tc): Enable SVE for both secure and non-secure world
feat(tc): populate HW_CONFIG in BL31

feat(tc): Enable SVE for both secure and non-secure world

Signed-off-by: Usama Arif <usama.arif@arm.com>
Change-Id: I0ae8a6ea3245373a17af76c9b7dc3f38f3711091

feat(tc): populate HW_CONFIG in BL31

BL2 passes FW_CONFIG to BL31 which contains information
about different DTBs present. BL31 then uses FW_CONFIG
to get the base address of HW_CONFIG and populate

feat(tc): populate HW_CONFIG in BL31

BL2 passes FW_CONFIG to BL31 which contains information
about different DTBs present. BL31 then uses FW_CONFIG
to get the base address of HW_CONFIG and populate fconf.

Signed-off-by: Usama Arif <usama.arif@arm.com>
Change-Id: I0b4fc83e6e0a0b9401f692516654eb9a3b037616

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refactor(plat/st): use TZC400 bindings

This avoids duplicate define of TZC_REGION_NSEC_ALL_ACCESS_RDWR.
And remove the previous TZC400 definitions from stm32mp1_def.h.

Change-Id: I6c72c2a18731f69d8

refactor(plat/st): use TZC400 bindings

This avoids duplicate define of TZC_REGION_NSEC_ALL_ACCESS_RDWR.
And remove the previous TZC400 definitions from stm32mp1_def.h.

Change-Id: I6c72c2a18731f69d855fbce8ce822a21da9364fa
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>

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feat(plat/st): manage io_policies with FCONF

Introduced IO policies management through the trusted
boot firmware config device tree for UUID references.

Change-Id: Ibeeabede51b0514ebba26dbbdae58736

feat(plat/st): manage io_policies with FCONF

Introduced IO policies management through the trusted
boot firmware config device tree for UUID references.

Change-Id: Ibeeabede51b0514ebba26dbbdae587363b2aa0a7
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>

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feat(plat/st): use FCONF to configure platform

Add required code to support FCONF on STM32MP1 platform.
The new FW_CONFIG DT file will be inside the FIP, and loaded by BL2.
It will be used to config

feat(plat/st): use FCONF to configure platform

Add required code to support FCONF on STM32MP1 platform.
The new FW_CONFIG DT file will be inside the FIP, and loaded by BL2.
It will be used to configure the addresses where to load other binaries.
BL2 should be agnostic of which BL32 is in the FIP (OP-TEE or SP_min),
so optee_utils.c is always compiled, and some OP-TEE flags are removed.

Change-Id: Id957b49b0117864136250bfc416664f815043ada
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>

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feat(plat/st): improve FIP image loading from MMC

Instead of using a scratch buffer of 512 bytes, we can directly use the
image address and max size. The mmc_block_dev_spec struct info is then
overw

feat(plat/st): improve FIP image loading from MMC

Instead of using a scratch buffer of 512 bytes, we can directly use the
image address and max size. The mmc_block_dev_spec struct info is then
overwritten for each image with this info, except FW_CONFIG and GPT
table which will still use the scratch buffer.
This allows using multiple blocks read on MMC, and so improves the boot
time.
A cache invalidate is required for the remaining data not used from the
first and last blocks read. It is not required for FW_CONFIG_ID,
as it is in scratch buffer in SYSRAM, and also because bl_mem_params
struct is overwritten in this case. This should also not be done if
the image is not found (OP-TEE extra binaries when using SP_min).

Change-Id: If3ecfdfe35bb9db66284036ca49c4bd1be4fd121
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>

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feat(plat/st): use FIP to load images

BL2 still uses the STM32 header binary format to be loaded from ROM code.
BL32 and BL33 and their respective device tree files are now put together
in a FIP fil

feat(plat/st): use FIP to load images

BL2 still uses the STM32 header binary format to be loaded from ROM code.
BL32 and BL33 and their respective device tree files are now put together
in a FIP file.
One DTB is created for each BL. To reduce their sizes, 2 new dtsi file are
in charge of removing useless nodes for a given BL. This is done because
BL2 and BL32 share the same device tree files base.

The previous way of booting is still available, the compilation flag
STM32MP_USE_STM32IMAGE has to be set to 1 in the make command. Some files
are duplicated and their names modified with _stm32_ to avoid too much
switches in the code.

Change-Id: I1ffada0af58486d4cf6044511b51e56b52269817
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>

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Merge "feat(fvp): enable external SP images in BL2 config" into integration

refactor(plat/st): updates for OP-TEE

Protect BL32 (SP_min) with MMU if OP-TEE is not used.
Validate OP-TEE header with optee_header_is_valid().
Use default values in bl2_mem_params_descs[]. They wi

refactor(plat/st): updates for OP-TEE

Protect BL32 (SP_min) with MMU if OP-TEE is not used.
Validate OP-TEE header with optee_header_is_valid().
Use default values in bl2_mem_params_descs[]. They will be overwritten
in bl2_plat_handle_post_image_load() if OP-TEE is used.

Change-Id: I8614f3a17caa827561614d0f25f30ee90c4ec3fe
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>

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