Merge changes Ic7579b60,I05414ca1 into integration

* changes:
fix(plat/ea_handler): print newline before fatal abort error message
feat(common/debug): add new macro ERROR_NL() to print just a ne

Merge changes Ic7579b60,I05414ca1 into integration

* changes:
fix(plat/ea_handler): print newline before fatal abort error message
feat(common/debug): add new macro ERROR_NL() to print just a newline

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fix(plat/ea_handler): print newline before fatal abort error message

External Abort may happen also during printing of some messages by
U-Boot or kernel. So print newline before fatal abort error me

fix(plat/ea_handler): print newline before fatal abort error message

External Abort may happen also during printing of some messages by
U-Boot or kernel. So print newline before fatal abort error message.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Ic7579b605e695c2e4cb9a4f5cdc2d0b3e5083e49

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fix(plat/fvp): provide boot files via semihosting

These files are needed during boot, but they were missing
for semihosting.
With this patch, the list of files is complete enough to
boot on ATF plat

fix(plat/fvp): provide boot files via semihosting

These files are needed during boot, but they were missing
for semihosting.
With this patch, the list of files is complete enough to
boot on ATF platform via semihosting.

Change-Id: I2f0ca25983a6e18096f040780776f19f8040ea79
Signed-off-by: stsp@users.sourceforge.net

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Merge "rpi4: enable RPi4 PCI SMC conduit" into integration

rpi4: SMCCC PCI implementation

The rpi4 has a single nonstandard ECAM. It is broken
into two pieces, the root port registers, and a window
to a single device's config space which can be moved
betwee

rpi4: SMCCC PCI implementation

The rpi4 has a single nonstandard ECAM. It is broken
into two pieces, the root port registers, and a window
to a single device's config space which can be moved
between devices. Now that we have widened the page
tables/MMIO window, we can create a read/write acces
functions that are called by the SMCCC/PCI API.

As an example platform, the rpi4 single device ECAM
region quirk is pretty straightforward. The assumption
here is that a lower level (uefi) has configured and
initialized the PCI root to match the values we are
using here.

Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
Change-Id: Ie1ffa8fe9aa1d3c62e6aa84746a949c1009162e0

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rpi4: enable RPi4 PCI SMC conduit

Now that we have adjusted the address map, added the
SMC conduit code, and the RPi4 PCI callbacks, lets
add the flags to enable everything in the build.

By default

rpi4: enable RPi4 PCI SMC conduit

Now that we have adjusted the address map, added the
SMC conduit code, and the RPi4 PCI callbacks, lets
add the flags to enable everything in the build.

By default this service is disabled because the
expectation is that its only useful in a UEFI+ACPI
environment.

Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
Change-Id: I2a3cac6d63ba8119d3b711db121185816b89f8a2

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Merge "plat/sgi: tag dmc620 MM communicate messages with a guid" into integration

Merge "fix(rk3399/suspend): correct LPDDR4 resume sequence" into integration

Merge "fix(plat/imx): do not keep mmc_device_info in stack" into integration

Merge changes from topic "allwinner_mmap" into integration

* changes:
refactor(plat/allwinner): clean up platform definitions
refactor(plat/allwinner): do not map BL32 DRAM at EL3
refactor(pla

Merge changes from topic "allwinner_mmap" into integration

* changes:
refactor(plat/allwinner): clean up platform definitions
refactor(plat/allwinner): do not map BL32 DRAM at EL3
refactor(plat/allwinner): map SRAM as device memory by default
refactor(plat/allwinner): rename static mmap region constant
feat(bl_common): import BL_NOBITS_{BASE,END} when defined

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Merge changes from topic "sve+amu" into integration

* changes:
fix(plat/tc0): enable AMU extension
fix(el3_runtime): fix SVE and AMU extension enablement flags

fix(plat/tc0): enable AMU extension

Recent changes to enable SVE for the secure world have disabled AMU
extension by default in the reset value of CPTR_EL3 register. So the
platform has to enable th

fix(plat/tc0): enable AMU extension

Recent changes to enable SVE for the secure world have disabled AMU
extension by default in the reset value of CPTR_EL3 register. So the
platform has to enable this extension explicitly.

Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: I7d930d96ec22d7c3db961411370564bece0ce272

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refactor(plat/allwinner): clean up platform definitions

Group the SCP base/size definitions in a more logical location.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Id43f9b468d7d8

refactor(plat/allwinner): clean up platform definitions

Group the SCP base/size definitions in a more logical location.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Id43f9b468d7d855a2413173d674a5ee666527808

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refactor(plat/allwinner): do not map BL32 DRAM at EL3

BL31 does not appear to ever access the DRAM allocated to BL32,
so there is no need to map it at EL3.

Signed-off-by: Samuel Holland <samuel@sho

refactor(plat/allwinner): do not map BL32 DRAM at EL3

BL31 does not appear to ever access the DRAM allocated to BL32,
so there is no need to map it at EL3.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Ie8727b793e53ea14517894942266f6da0333eb74

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refactor(plat/allwinner): map SRAM as device memory by default

The SRAM on Allwinner platforms is shared between BL31 and coprocessor
firmware. Previously, SRAM was mapped as normal memory by defaul

refactor(plat/allwinner): map SRAM as device memory by default

The SRAM on Allwinner platforms is shared between BL31 and coprocessor
firmware. Previously, SRAM was mapped as normal memory by default.
This scheme requires carveouts and cache maintenance code for proper
synchronization with the coprocessor.

A better scheme is to only map pages owned by BL31 as normal memory,
and leave everything else as device memory. This removes the need for
cache maintenance, and it makes the mapping for BL31 RW data explicit
instead of magic.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I820ddeba2dfa2396361c2322308c0db51b55c348

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refactor(plat/allwinner): rename static mmap region constant

This constant specifically refers to the number of static mmap regions.
Rename it to make that clear.

Signed-off-by: Samuel Holland <sam

refactor(plat/allwinner): rename static mmap region constant

This constant specifically refers to the number of static mmap regions.
Rename it to make that clear.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I475c037777ce2a10db2631ec0e7446bb73590a36

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feat: disabling non volatile counters in diphda

At this stage of development Non Volatile counters are not implemented
in the Diphda platform.

This commit disables their use during the Trusted Boar

feat: disabling non volatile counters in diphda

At this stage of development Non Volatile counters are not implemented
in the Diphda platform.

This commit disables their use during the Trusted Board Boot by
overriding the NV counters get/set functions.

Change-Id: I8dcbebe0281cc4d0837c283ff637e20b850988ef
Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>

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feat: adding the diphda platform

This commit enables trusted-firmware-a with Trusted Board Boot support
for the Diphda 64-bit platform.

Diphda uses a FIP image located in the flash. The FIP contain

feat: adding the diphda platform

This commit enables trusted-firmware-a with Trusted Board Boot support
for the Diphda 64-bit platform.

Diphda uses a FIP image located in the flash. The FIP contains the
following components:

- BL2
- BL31
- BL32
- BL32 SPMC manifest
- BL33
- The TBB certificates

The board boot relies on CoT (chain of trust). The trusted-firmware-a
BL2 is extracted from the FIP and verified by the Secure Enclave
processor. BL2 verification relies on the signature area at the
beginning of the BL2 image. This area is needed by the SecureEnclave
bootloader.

Then, the application processor is released from reset and starts by
executing BL2.

BL2 performs the actions described in the trusted-firmware-a TBB design
document.

Signed-off-by: Rui Miguel Silva <rui.silva@arm.com>
Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
Change-Id: Iddb1cb9c2a0324a9635e23821c210ac81dfc305d

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feat(ff-a): change manifest messaging method

Align documentation with changes of messaging method for partition
manifest:
- Bit[0]: support for receiving direct message requests
- Bit[1]

feat(ff-a): change manifest messaging method

Align documentation with changes of messaging method for partition
manifest:
- Bit[0]: support for receiving direct message requests
- Bit[1]: support for sending direct messages
- Bit[2]: support for indirect messaging
- Bit[3]: support for managed exit
Change the optee_sp_manifest to align with the new messaging method
description.

Signed-off-by: Maksims Svecovs <maksims.svecovs@arm.com>
Change-Id: I333e82c546c03698c95f0c77293018f8dca5ba9c

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feat(plat/versal): add support for SLS mitigation

This patch adds the option HARDEN_SLS_ALL that can be used to enable
the -mharden-sls=all, which mitigates the straight-line speculation
vulnerabili

feat(plat/versal): add support for SLS mitigation

This patch adds the option HARDEN_SLS_ALL that can be used to enable
the -mharden-sls=all, which mitigates the straight-line speculation
vulnerability. Enable this by adding the option HARDEN_SLS_ALL=1,
default this will be disabled.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I0d498d9e96903fcb879993ad491949f6f17769b2

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fix(mediatek/mt8192/spm): add missing bit define for debug purpose

Signed-off-by: Roger Lu <roger.lu@mediatek.com>
Change-Id: I6dbf6d4ea6310c3371ca15d1e7cce249a05af2fb

feat(plat/imx/imx8m/imx8mm): enlarge BL33 (U-boot) size in FIP

When enabling U-boot with UEFI and secure boot, the size of U-boot
becomes more than 1MB. So we enlarge BL33 to 2MB.

Signed-off-by: Yi

feat(plat/imx/imx8m/imx8mm): enlarge BL33 (U-boot) size in FIP

When enabling U-boot with UEFI and secure boot, the size of U-boot
becomes more than 1MB. So we enlarge BL33 to 2MB.

Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
Change-Id: I9d9d24132bb1ec17ef6080dc72e93c7f531c97b5

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Merge "fix(plat/mediatek/me8195): fix error setting for SPM" into integration

Merge changes from topic "fwu-refactor" into integration

* changes:
refactor(plat/arm): use mmio* functions to read/write NVFLAGS registers
refactor(plat/arm): mark the flash region as read-only

Merge changes from topic "fwu-refactor" into integration

* changes:
refactor(plat/arm): use mmio* functions to read/write NVFLAGS registers
refactor(plat/arm): mark the flash region as read-only
refactor(plat/arm): update NV flags on image load/authentication failure

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Merge changes from topic "marvell-a3k-a8k-updates" into integration

* changes:
fix(plat/marvell/a3k): Fix building uart-images.tgz.bin archive
refactor(plat/marvell/a3k): Rename *_CFG and *_SIG

Merge changes from topic "marvell-a3k-a8k-updates" into integration

* changes:
fix(plat/marvell/a3k): Fix building uart-images.tgz.bin archive
refactor(plat/marvell/a3k): Rename *_CFG and *_SIG variables
refactor(plat/marvell/a3k): Rename DOIMAGETOOL to TBB
refactor(plat/marvell/a3k): Remove useless DOIMAGEPATH variable
fix(plat/marvell/a3k): Fix check for external dependences
fix(plat/marvell/a8k): Add missing build dependency for BLE target
fix(plat/marvell/a8k): Correctly set include directories for individual targets
fix(plat/marvell/a8k): Require that MV_DDR_PATH is correctly set

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