1 /* 2 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <string.h> 9 10 #include <arch_helpers.h> 11 #include <common/debug.h> 12 #include <drivers/io/io_block.h> 13 #include <drivers/io/io_driver.h> 14 #include <drivers/io/io_fip.h> 15 #include <drivers/io/io_mtd.h> 16 #include <drivers/io/io_storage.h> 17 #include <drivers/mmc.h> 18 #include <drivers/partition/partition.h> 19 #include <drivers/raw_nand.h> 20 #include <drivers/spi_nand.h> 21 #include <drivers/spi_nor.h> 22 #include <drivers/st/io_mmc.h> 23 #include <drivers/st/stm32_fmc2_nand.h> 24 #include <drivers/st/stm32_qspi.h> 25 #include <drivers/st/stm32_sdmmc2.h> 26 #include <lib/mmio.h> 27 #include <lib/utils.h> 28 #include <plat/common/platform.h> 29 #include <tools_share/firmware_image_package.h> 30 31 #include <platform_def.h> 32 33 /* IO devices */ 34 uintptr_t fip_dev_handle; 35 uintptr_t storage_dev_handle; 36 37 static const io_dev_connector_t *fip_dev_con; 38 39 #if STM32MP_SDMMC || STM32MP_EMMC 40 static struct mmc_device_info mmc_info; 41 static io_block_spec_t gpt_block_spec = { 42 .offset = 0U, 43 .length = 34U * MMC_BLOCK_SIZE, /* Size of GPT table */ 44 }; 45 46 static uint32_t block_buffer[MMC_BLOCK_SIZE] __aligned(MMC_BLOCK_SIZE); 47 48 static const io_block_dev_spec_t mmc_block_dev_spec = { 49 /* It's used as temp buffer in block driver */ 50 .buffer = { 51 .offset = (size_t)&block_buffer, 52 .length = MMC_BLOCK_SIZE, 53 }, 54 .ops = { 55 .read = mmc_read_blocks, 56 .write = NULL, 57 }, 58 .block_size = MMC_BLOCK_SIZE, 59 }; 60 61 static const io_dev_connector_t *mmc_dev_con; 62 #endif /* STM32MP_SDMMC || STM32MP_EMMC */ 63 64 #if STM32MP_SPI_NOR 65 static io_mtd_dev_spec_t spi_nor_dev_spec = { 66 .ops = { 67 .init = spi_nor_init, 68 .read = spi_nor_read, 69 }, 70 }; 71 #endif 72 73 #if STM32MP_RAW_NAND 74 static io_mtd_dev_spec_t nand_dev_spec = { 75 .ops = { 76 .init = nand_raw_init, 77 .read = nand_read, 78 .seek = nand_seek_bb 79 }, 80 }; 81 82 static const io_dev_connector_t *nand_dev_con; 83 #endif 84 85 #if STM32MP_SPI_NAND 86 static io_mtd_dev_spec_t spi_nand_dev_spec = { 87 .ops = { 88 .init = spi_nand_init, 89 .read = nand_read, 90 .seek = nand_seek_bb 91 }, 92 }; 93 #endif 94 95 #if STM32MP_SPI_NAND || STM32MP_SPI_NOR 96 static const io_dev_connector_t *spi_dev_con; 97 #endif 98 99 static const io_uuid_spec_t bl33_partition_spec = { 100 .uuid = UUID_NON_TRUSTED_FIRMWARE_BL33 101 }; 102 103 static const io_uuid_spec_t tos_fw_config_uuid_spec = { 104 .uuid = UUID_TOS_FW_CONFIG, 105 }; 106 107 static const io_uuid_spec_t hw_config_uuid_spec = { 108 .uuid = UUID_HW_CONFIG, 109 }; 110 111 #ifdef AARCH32_SP_OPTEE 112 static const io_uuid_spec_t optee_header_partition_spec = { 113 .uuid = UUID_SECURE_PAYLOAD_BL32 114 }; 115 116 static const io_uuid_spec_t optee_core_partition_spec = { 117 .uuid = UUID_SECURE_PAYLOAD_BL32_EXTRA1 118 }; 119 120 static const io_uuid_spec_t optee_paged_partition_spec = { 121 .uuid = UUID_SECURE_PAYLOAD_BL32_EXTRA2 122 }; 123 #else 124 static const io_uuid_spec_t bl32_partition_spec = { 125 .uuid = UUID_SECURE_PAYLOAD_BL32 126 }; 127 #endif 128 129 static io_block_spec_t image_block_spec = { 130 .offset = 0U, 131 .length = 0U, 132 }; 133 134 static int open_fip(const uintptr_t spec); 135 static int open_storage(const uintptr_t spec); 136 137 struct plat_io_policy { 138 uintptr_t *dev_handle; 139 uintptr_t image_spec; 140 int (*check)(const uintptr_t spec); 141 }; 142 143 static const struct plat_io_policy policies[] = { 144 [FIP_IMAGE_ID] = { 145 .dev_handle = &storage_dev_handle, 146 .image_spec = (uintptr_t)&image_block_spec, 147 .check = open_storage 148 }, 149 #ifdef AARCH32_SP_OPTEE 150 [BL32_IMAGE_ID] = { 151 .dev_handle = &fip_dev_handle, 152 .image_spec = (uintptr_t)&optee_header_partition_spec, 153 .check = open_fip 154 }, 155 [BL32_EXTRA1_IMAGE_ID] = { 156 .dev_handle = &fip_dev_handle, 157 .image_spec = (uintptr_t)&optee_core_partition_spec, 158 .check = open_fip 159 }, 160 [BL32_EXTRA2_IMAGE_ID] = { 161 .dev_handle = &fip_dev_handle, 162 .image_spec = (uintptr_t)&optee_paged_partition_spec, 163 .check = open_fip 164 }, 165 #else 166 [BL32_IMAGE_ID] = { 167 .dev_handle = &fip_dev_handle, 168 .image_spec = (uintptr_t)&bl32_partition_spec, 169 .check = open_fip 170 }, 171 #endif 172 [BL33_IMAGE_ID] = { 173 .dev_handle = &fip_dev_handle, 174 .image_spec = (uintptr_t)&bl33_partition_spec, 175 .check = open_fip 176 }, 177 [TOS_FW_CONFIG_ID] = { 178 .dev_handle = &fip_dev_handle, 179 .image_spec = (uintptr_t)&tos_fw_config_uuid_spec, 180 .check = open_fip 181 }, 182 [HW_CONFIG_ID] = { 183 .dev_handle = &fip_dev_handle, 184 .image_spec = (uintptr_t)&hw_config_uuid_spec, 185 .check = open_fip 186 }, 187 #if STM32MP_SDMMC || STM32MP_EMMC 188 [GPT_IMAGE_ID] = { 189 .dev_handle = &storage_dev_handle, 190 .image_spec = (uintptr_t)&gpt_block_spec, 191 .check = open_storage 192 }, 193 #endif 194 }; 195 196 static int open_fip(const uintptr_t spec) 197 { 198 return io_dev_init(fip_dev_handle, (uintptr_t)FIP_IMAGE_ID); 199 } 200 201 static int open_storage(const uintptr_t spec) 202 { 203 return io_dev_init(storage_dev_handle, 0); 204 } 205 206 static void print_boot_device(boot_api_context_t *boot_context) 207 { 208 switch (boot_context->boot_interface_selected) { 209 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD: 210 INFO("Using SDMMC\n"); 211 break; 212 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC: 213 INFO("Using EMMC\n"); 214 break; 215 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI: 216 INFO("Using QSPI NOR\n"); 217 break; 218 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC: 219 INFO("Using FMC NAND\n"); 220 break; 221 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_QSPI: 222 INFO("Using SPI NAND\n"); 223 break; 224 default: 225 ERROR("Boot interface %u not found\n", 226 boot_context->boot_interface_selected); 227 panic(); 228 break; 229 } 230 231 if (boot_context->boot_interface_instance != 0U) { 232 INFO(" Instance %d\n", boot_context->boot_interface_instance); 233 } 234 } 235 236 #if STM32MP_SDMMC || STM32MP_EMMC 237 static void boot_mmc(enum mmc_device_type mmc_dev_type, 238 uint16_t boot_interface_instance) 239 { 240 int io_result __unused; 241 struct stm32_sdmmc2_params params; 242 243 zeromem(¶ms, sizeof(struct stm32_sdmmc2_params)); 244 245 mmc_info.mmc_dev_type = mmc_dev_type; 246 247 switch (boot_interface_instance) { 248 case 1: 249 params.reg_base = STM32MP_SDMMC1_BASE; 250 break; 251 case 2: 252 params.reg_base = STM32MP_SDMMC2_BASE; 253 break; 254 case 3: 255 params.reg_base = STM32MP_SDMMC3_BASE; 256 break; 257 default: 258 WARN("SDMMC instance not found, using default\n"); 259 if (mmc_dev_type == MMC_IS_SD) { 260 params.reg_base = STM32MP_SDMMC1_BASE; 261 } else { 262 params.reg_base = STM32MP_SDMMC2_BASE; 263 } 264 break; 265 } 266 267 params.device_info = &mmc_info; 268 if (stm32_sdmmc2_mmc_init(¶ms) != 0) { 269 ERROR("SDMMC%u init failed\n", boot_interface_instance); 270 panic(); 271 } 272 273 /* Open MMC as a block device to read GPT table */ 274 io_result = register_io_dev_block(&mmc_dev_con); 275 if (io_result != 0) { 276 panic(); 277 } 278 279 io_result = io_dev_open(mmc_dev_con, (uintptr_t)&mmc_block_dev_spec, 280 &storage_dev_handle); 281 assert(io_result == 0); 282 } 283 #endif /* STM32MP_SDMMC || STM32MP_EMMC */ 284 285 #if STM32MP_SPI_NOR 286 static void boot_spi_nor(boot_api_context_t *boot_context) 287 { 288 int io_result __unused; 289 290 io_result = stm32_qspi_init(); 291 assert(io_result == 0); 292 293 io_result = register_io_dev_mtd(&spi_dev_con); 294 assert(io_result == 0); 295 296 /* Open connections to device */ 297 io_result = io_dev_open(spi_dev_con, 298 (uintptr_t)&spi_nor_dev_spec, 299 &storage_dev_handle); 300 assert(io_result == 0); 301 } 302 #endif /* STM32MP_SPI_NOR */ 303 304 #if STM32MP_RAW_NAND 305 static void boot_fmc2_nand(boot_api_context_t *boot_context) 306 { 307 int io_result __unused; 308 309 io_result = stm32_fmc2_init(); 310 assert(io_result == 0); 311 312 /* Register the IO device on this platform */ 313 io_result = register_io_dev_mtd(&nand_dev_con); 314 assert(io_result == 0); 315 316 /* Open connections to device */ 317 io_result = io_dev_open(nand_dev_con, (uintptr_t)&nand_dev_spec, 318 &storage_dev_handle); 319 assert(io_result == 0); 320 } 321 #endif /* STM32MP_RAW_NAND */ 322 323 #if STM32MP_SPI_NAND 324 static void boot_spi_nand(boot_api_context_t *boot_context) 325 { 326 int io_result __unused; 327 328 io_result = stm32_qspi_init(); 329 assert(io_result == 0); 330 331 io_result = register_io_dev_mtd(&spi_dev_con); 332 assert(io_result == 0); 333 334 /* Open connections to device */ 335 io_result = io_dev_open(spi_dev_con, 336 (uintptr_t)&spi_nand_dev_spec, 337 &storage_dev_handle); 338 assert(io_result == 0); 339 } 340 #endif /* STM32MP_SPI_NAND */ 341 342 void stm32mp_io_setup(void) 343 { 344 int io_result __unused; 345 boot_api_context_t *boot_context = 346 (boot_api_context_t *)stm32mp_get_boot_ctx_address(); 347 348 print_boot_device(boot_context); 349 350 if ((boot_context->boot_partition_used_toboot == 1U) || 351 (boot_context->boot_partition_used_toboot == 2U)) { 352 INFO("Boot used partition fsbl%u\n", 353 boot_context->boot_partition_used_toboot); 354 } 355 356 io_result = register_io_dev_fip(&fip_dev_con); 357 assert(io_result == 0); 358 359 io_result = io_dev_open(fip_dev_con, (uintptr_t)NULL, 360 &fip_dev_handle); 361 362 switch (boot_context->boot_interface_selected) { 363 #if STM32MP_SDMMC 364 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD: 365 dmbsy(); 366 boot_mmc(MMC_IS_SD, boot_context->boot_interface_instance); 367 break; 368 #endif 369 #if STM32MP_EMMC 370 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC: 371 dmbsy(); 372 boot_mmc(MMC_IS_EMMC, boot_context->boot_interface_instance); 373 break; 374 #endif 375 #if STM32MP_SPI_NOR 376 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI: 377 dmbsy(); 378 boot_spi_nor(boot_context); 379 break; 380 #endif 381 #if STM32MP_RAW_NAND 382 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC: 383 dmbsy(); 384 boot_fmc2_nand(boot_context); 385 break; 386 #endif 387 #if STM32MP_SPI_NAND 388 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_QSPI: 389 dmbsy(); 390 boot_spi_nand(boot_context); 391 break; 392 #endif 393 394 default: 395 ERROR("Boot interface %d not supported\n", 396 boot_context->boot_interface_selected); 397 panic(); 398 break; 399 } 400 } 401 402 int bl2_plat_handle_pre_image_load(unsigned int image_id) 403 { 404 static bool gpt_init_done __unused; 405 uint16_t boot_itf = stm32mp_get_boot_itf_selected(); 406 407 switch (boot_itf) { 408 #if STM32MP_SDMMC || STM32MP_EMMC 409 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD: 410 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC: 411 if (!gpt_init_done) { 412 const partition_entry_t *entry; 413 414 partition_init(GPT_IMAGE_ID); 415 entry = get_partition_entry(FIP_IMAGE_NAME); 416 if (entry == NULL) { 417 ERROR("Could NOT find the %s partition!\n", 418 FIP_IMAGE_NAME); 419 return -ENOENT; 420 } 421 422 image_block_spec.offset = entry->start; 423 image_block_spec.length = entry->length; 424 425 gpt_init_done = true; 426 } 427 428 break; 429 #endif 430 431 #if STM32MP_RAW_NAND || STM32MP_SPI_NAND 432 #if STM32MP_RAW_NAND 433 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC: 434 #endif 435 #if STM32MP_SPI_NAND 436 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_QSPI: 437 #endif 438 image_block_spec.offset = STM32MP_NAND_FIP_OFFSET; 439 break; 440 #endif 441 442 #if STM32MP_SPI_NOR 443 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI: 444 image_block_spec.offset = STM32MP_NOR_FIP_OFFSET; 445 break; 446 #endif 447 448 default: 449 ERROR("FIP Not found\n"); 450 panic(); 451 } 452 453 return 0; 454 } 455 456 /* 457 * Return an IO device handle and specification which can be used to access 458 * an image. Use this to enforce platform load policy. 459 */ 460 int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle, 461 uintptr_t *image_spec) 462 { 463 int rc; 464 const struct plat_io_policy *policy; 465 466 assert(image_id < ARRAY_SIZE(policies)); 467 468 policy = &policies[image_id]; 469 rc = policy->check(policy->image_spec); 470 if (rc == 0) { 471 *image_spec = policy->image_spec; 472 *dev_handle = *(policy->dev_handle); 473 } 474 475 return rc; 476 } 477