1 /* 2 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <string.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <common/desc_image_load.h> 16 #include <drivers/delay_timer.h> 17 #include <drivers/generic_delay_timer.h> 18 #include <drivers/st/bsec.h> 19 #include <drivers/st/stm32_console.h> 20 #include <drivers/st/stm32_iwdg.h> 21 #include <drivers/st/stm32mp_pmic.h> 22 #include <drivers/st/stm32mp_reset.h> 23 #include <drivers/st/stm32mp1_clk.h> 24 #include <drivers/st/stm32mp1_pwr.h> 25 #include <drivers/st/stm32mp1_ram.h> 26 #include <lib/mmio.h> 27 #include <lib/optee_utils.h> 28 #include <lib/xlat_tables/xlat_tables_v2.h> 29 #include <plat/common/platform.h> 30 31 #include <stm32mp1_context.h> 32 #include <stm32mp1_dbgmcu.h> 33 34 #define RESET_TIMEOUT_US_1MS 1000U 35 36 static console_t console; 37 static struct stm32mp_auth_ops stm32mp1_auth_ops; 38 39 static void print_reset_reason(void) 40 { 41 uint32_t rstsr = mmio_read_32(stm32mp_rcc_base() + RCC_MP_RSTSCLRR); 42 43 if (rstsr == 0U) { 44 WARN("Reset reason unknown\n"); 45 return; 46 } 47 48 INFO("Reset reason (0x%x):\n", rstsr); 49 50 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) == 0U) { 51 if ((rstsr & RCC_MP_RSTSCLRR_STDBYRSTF) != 0U) { 52 INFO("System exits from STANDBY\n"); 53 return; 54 } 55 56 if ((rstsr & RCC_MP_RSTSCLRR_CSTDBYRSTF) != 0U) { 57 INFO("MPU exits from CSTANDBY\n"); 58 return; 59 } 60 } 61 62 if ((rstsr & RCC_MP_RSTSCLRR_PORRSTF) != 0U) { 63 INFO(" Power-on Reset (rst_por)\n"); 64 return; 65 } 66 67 if ((rstsr & RCC_MP_RSTSCLRR_BORRSTF) != 0U) { 68 INFO(" Brownout Reset (rst_bor)\n"); 69 return; 70 } 71 72 if ((rstsr & RCC_MP_RSTSCLRR_MCSYSRSTF) != 0U) { 73 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) { 74 INFO(" System reset generated by MCU (MCSYSRST)\n"); 75 } else { 76 INFO(" Local reset generated by MCU (MCSYSRST)\n"); 77 } 78 return; 79 } 80 81 if ((rstsr & RCC_MP_RSTSCLRR_MPSYSRSTF) != 0U) { 82 INFO(" System reset generated by MPU (MPSYSRST)\n"); 83 return; 84 } 85 86 if ((rstsr & RCC_MP_RSTSCLRR_HCSSRSTF) != 0U) { 87 INFO(" Reset due to a clock failure on HSE\n"); 88 return; 89 } 90 91 if ((rstsr & RCC_MP_RSTSCLRR_IWDG1RSTF) != 0U) { 92 INFO(" IWDG1 Reset (rst_iwdg1)\n"); 93 return; 94 } 95 96 if ((rstsr & RCC_MP_RSTSCLRR_IWDG2RSTF) != 0U) { 97 INFO(" IWDG2 Reset (rst_iwdg2)\n"); 98 return; 99 } 100 101 if ((rstsr & RCC_MP_RSTSCLRR_MPUP0RSTF) != 0U) { 102 INFO(" MPU Processor 0 Reset\n"); 103 return; 104 } 105 106 if ((rstsr & RCC_MP_RSTSCLRR_MPUP1RSTF) != 0U) { 107 INFO(" MPU Processor 1 Reset\n"); 108 return; 109 } 110 111 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) { 112 INFO(" Pad Reset from NRST\n"); 113 return; 114 } 115 116 if ((rstsr & RCC_MP_RSTSCLRR_VCORERSTF) != 0U) { 117 INFO(" Reset due to a failure of VDD_CORE\n"); 118 return; 119 } 120 121 ERROR(" Unidentified reset reason\n"); 122 } 123 124 void bl2_el3_early_platform_setup(u_register_t arg0, 125 u_register_t arg1 __unused, 126 u_register_t arg2 __unused, 127 u_register_t arg3 __unused) 128 { 129 stm32mp_save_boot_ctx_address(arg0); 130 } 131 132 void bl2_platform_setup(void) 133 { 134 int ret; 135 136 if (dt_pmic_status() > 0) { 137 initialize_pmic(); 138 } 139 140 ret = stm32mp1_ddr_probe(); 141 if (ret < 0) { 142 ERROR("Invalid DDR init: error %d\n", ret); 143 panic(); 144 } 145 146 /* Map DDR for binary load, now with cacheable attribute */ 147 ret = mmap_add_dynamic_region(STM32MP_DDR_BASE, STM32MP_DDR_BASE, 148 STM32MP_DDR_MAX_SIZE, MT_MEMORY | MT_RW | MT_SECURE); 149 if (ret < 0) { 150 ERROR("DDR mapping: error %d\n", ret); 151 panic(); 152 } 153 154 #ifdef AARCH32_SP_OPTEE 155 INFO("BL2 runs OP-TEE setup\n"); 156 #else 157 INFO("BL2 runs SP_MIN setup\n"); 158 #endif 159 } 160 161 void bl2_el3_plat_arch_setup(void) 162 { 163 int32_t result; 164 struct dt_node_info dt_uart_info; 165 const char *board_model; 166 boot_api_context_t *boot_context = 167 (boot_api_context_t *)stm32mp_get_boot_ctx_address(); 168 uint32_t clk_rate; 169 uintptr_t pwr_base; 170 uintptr_t rcc_base; 171 172 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, 173 BL_CODE_END - BL_CODE_BASE, 174 MT_CODE | MT_SECURE); 175 176 #ifdef AARCH32_SP_OPTEE 177 mmap_add_region(STM32MP_OPTEE_BASE, STM32MP_OPTEE_BASE, 178 STM32MP_OPTEE_SIZE, 179 MT_MEMORY | MT_RW | MT_SECURE); 180 #else 181 /* Prevent corruption of preloaded BL32 */ 182 mmap_add_region(BL32_BASE, BL32_BASE, 183 BL32_LIMIT - BL32_BASE, 184 MT_RO_DATA | MT_SECURE); 185 #endif 186 /* Prevent corruption of preloaded Device Tree */ 187 mmap_add_region(DTB_BASE, DTB_BASE, 188 DTB_LIMIT - DTB_BASE, 189 MT_RO_DATA | MT_SECURE); 190 191 configure_mmu(); 192 193 if (dt_open_and_check(STM32MP_DTB_BASE) < 0) { 194 panic(); 195 } 196 197 pwr_base = stm32mp_pwr_base(); 198 rcc_base = stm32mp_rcc_base(); 199 200 /* 201 * Disable the backup domain write protection. 202 * The protection is enable at each reset by hardware 203 * and must be disabled by software. 204 */ 205 mmio_setbits_32(pwr_base + PWR_CR1, PWR_CR1_DBP); 206 207 while ((mmio_read_32(pwr_base + PWR_CR1) & PWR_CR1_DBP) == 0U) { 208 ; 209 } 210 211 if (bsec_probe() != 0) { 212 panic(); 213 } 214 215 /* Reset backup domain on cold boot cases */ 216 if ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_RTCSRC_MASK) == 0U) { 217 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST); 218 219 while ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_VSWRST) == 220 0U) { 221 ; 222 } 223 224 mmio_clrbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST); 225 } 226 227 /* Disable MCKPROT */ 228 mmio_clrbits_32(rcc_base + RCC_TZCR, RCC_TZCR_MCKPROT); 229 230 generic_delay_timer_init(); 231 232 if (stm32mp1_clk_probe() < 0) { 233 panic(); 234 } 235 236 if (stm32mp1_clk_init() < 0) { 237 panic(); 238 } 239 240 stm32mp1_syscfg_init(); 241 242 result = dt_get_stdout_uart_info(&dt_uart_info); 243 244 if ((result <= 0) || 245 (dt_uart_info.status == 0U) || 246 (dt_uart_info.clock < 0) || 247 (dt_uart_info.reset < 0)) { 248 goto skip_console_init; 249 } 250 251 if (dt_set_stdout_pinctrl() != 0) { 252 goto skip_console_init; 253 } 254 255 stm32mp_clk_enable((unsigned long)dt_uart_info.clock); 256 257 if (stm32mp_reset_assert((uint32_t)dt_uart_info.reset, 258 RESET_TIMEOUT_US_1MS) != 0) { 259 panic(); 260 } 261 262 udelay(2); 263 264 if (stm32mp_reset_deassert((uint32_t)dt_uart_info.reset, 265 RESET_TIMEOUT_US_1MS) != 0) { 266 panic(); 267 } 268 269 mdelay(1); 270 271 clk_rate = stm32mp_clk_get_rate((unsigned long)dt_uart_info.clock); 272 273 if (console_stm32_register(dt_uart_info.base, clk_rate, 274 STM32MP_UART_BAUDRATE, &console) == 0) { 275 panic(); 276 } 277 278 console_set_scope(&console, CONSOLE_FLAG_BOOT | 279 CONSOLE_FLAG_CRASH | CONSOLE_FLAG_TRANSLATE_CRLF); 280 281 stm32mp_print_cpuinfo(); 282 283 board_model = dt_get_board_model(); 284 if (board_model != NULL) { 285 NOTICE("Model: %s\n", board_model); 286 } 287 288 stm32mp_print_boardinfo(); 289 290 if (boot_context->auth_status != BOOT_API_CTX_AUTH_NO) { 291 NOTICE("Bootrom authentication %s\n", 292 (boot_context->auth_status == BOOT_API_CTX_AUTH_FAILED) ? 293 "failed" : "succeeded"); 294 } 295 296 skip_console_init: 297 if (stm32_iwdg_init() < 0) { 298 panic(); 299 } 300 301 stm32_iwdg_refresh(); 302 303 result = stm32mp1_dbgmcu_freeze_iwdg2(); 304 if (result != 0) { 305 INFO("IWDG2 freeze error : %i\n", result); 306 } 307 308 if (stm32_save_boot_interface(boot_context->boot_interface_selected, 309 boot_context->boot_interface_instance) != 310 0) { 311 ERROR("Cannot save boot interface\n"); 312 } 313 314 stm32mp1_auth_ops.check_key = boot_context->bootrom_ecdsa_check_key; 315 stm32mp1_auth_ops.verify_signature = 316 boot_context->bootrom_ecdsa_verify_signature; 317 318 stm32mp_init_auth(&stm32mp1_auth_ops); 319 320 stm32mp1_arch_security_setup(); 321 322 print_reset_reason(); 323 324 stm32mp_io_setup(); 325 } 326 327 #if defined(AARCH32_SP_OPTEE) 328 /******************************************************************************* 329 * This function can be used by the platforms to update/use image 330 * information for given `image_id`. 331 ******************************************************************************/ 332 int bl2_plat_handle_post_image_load(unsigned int image_id) 333 { 334 int err = 0; 335 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 336 bl_mem_params_node_t *bl32_mem_params; 337 bl_mem_params_node_t *pager_mem_params; 338 bl_mem_params_node_t *paged_mem_params; 339 340 assert(bl_mem_params != NULL); 341 342 switch (image_id) { 343 case BL32_IMAGE_ID: 344 if (optee_header_is_valid(bl_mem_params->image_info.image_base)) { 345 /* BL32 is OP-TEE header */ 346 bl_mem_params->ep_info.pc = bl_mem_params->image_info.image_base; 347 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 348 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); 349 assert((pager_mem_params != NULL) && (paged_mem_params != NULL)); 350 351 /* Set OP-TEE extra image load areas at run-time */ 352 pager_mem_params->image_info.image_base = STM32MP_OPTEE_BASE; 353 pager_mem_params->image_info.image_max_size = STM32MP_OPTEE_SIZE; 354 355 paged_mem_params->image_info.image_base = STM32MP_DDR_BASE + 356 dt_get_ddr_size() - 357 STM32MP_DDR_S_SIZE - 358 STM32MP_DDR_SHMEM_SIZE; 359 paged_mem_params->image_info.image_max_size = STM32MP_DDR_S_SIZE; 360 361 err = parse_optee_header(&bl_mem_params->ep_info, 362 &pager_mem_params->image_info, 363 &paged_mem_params->image_info); 364 if (err) { 365 ERROR("OPTEE header parse error.\n"); 366 panic(); 367 } 368 369 /* Set optee boot info from parsed header data */ 370 bl_mem_params->ep_info.args.arg0 = paged_mem_params->image_info.image_base; 371 bl_mem_params->ep_info.args.arg1 = 0; /* Unused */ 372 bl_mem_params->ep_info.args.arg2 = 0; /* No DT supported */ 373 } 374 break; 375 376 case BL33_IMAGE_ID: 377 bl32_mem_params = get_bl_mem_params_node(BL32_IMAGE_ID); 378 assert(bl32_mem_params != NULL); 379 bl32_mem_params->ep_info.lr_svc = bl_mem_params->ep_info.pc; 380 break; 381 382 default: 383 /* Do nothing in default case */ 384 break; 385 } 386 387 return err; 388 } 389 390 void bl2_el3_plat_prepare_exit(void) 391 { 392 stm32mp1_security_setup(); 393 } 394 #endif 395