xref: /rk3399_ARM-atf/plat/st/stm32mp1/bl2_plat_setup.c (revision 1d204ee4ab12893fceb12097bd4f0a074be253b2) 
1 /*
2  * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #include <assert.h>
8 #include <string.h>
9 
10 #include <platform_def.h>
11 
12 #include <arch_helpers.h>
13 #include <common/bl_common.h>
14 #include <common/debug.h>
15 #include <common/desc_image_load.h>
16 #include <drivers/delay_timer.h>
17 #include <drivers/generic_delay_timer.h>
18 #include <drivers/st/bsec.h>
19 #include <drivers/st/stm32_console.h>
20 #include <drivers/st/stm32_iwdg.h>
21 #include <drivers/st/stm32mp_pmic.h>
22 #include <drivers/st/stm32mp_reset.h>
23 #include <drivers/st/stm32mp1_clk.h>
24 #include <drivers/st/stm32mp1_pwr.h>
25 #include <drivers/st/stm32mp1_ram.h>
26 #include <lib/mmio.h>
27 #include <lib/optee_utils.h>
28 #include <lib/xlat_tables/xlat_tables_v2.h>
29 #include <plat/common/platform.h>
30 
31 #include <stm32mp1_context.h>
32 #include <stm32mp1_dbgmcu.h>
33 
34 #define RESET_TIMEOUT_US_1MS		1000U
35 
36 static console_t console;
37 static struct stm32mp_auth_ops stm32mp1_auth_ops;
38 
39 static void print_reset_reason(void)
40 {
41 	uint32_t rstsr = mmio_read_32(stm32mp_rcc_base() + RCC_MP_RSTSCLRR);
42 
43 	if (rstsr == 0U) {
44 		WARN("Reset reason unknown\n");
45 		return;
46 	}
47 
48 	INFO("Reset reason (0x%x):\n", rstsr);
49 
50 	if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) == 0U) {
51 		if ((rstsr & RCC_MP_RSTSCLRR_STDBYRSTF) != 0U) {
52 			INFO("System exits from STANDBY\n");
53 			return;
54 		}
55 
56 		if ((rstsr & RCC_MP_RSTSCLRR_CSTDBYRSTF) != 0U) {
57 			INFO("MPU exits from CSTANDBY\n");
58 			return;
59 		}
60 	}
61 
62 	if ((rstsr & RCC_MP_RSTSCLRR_PORRSTF) != 0U) {
63 		INFO("  Power-on Reset (rst_por)\n");
64 		return;
65 	}
66 
67 	if ((rstsr & RCC_MP_RSTSCLRR_BORRSTF) != 0U) {
68 		INFO("  Brownout Reset (rst_bor)\n");
69 		return;
70 	}
71 
72 	if ((rstsr & RCC_MP_RSTSCLRR_MCSYSRSTF) != 0U) {
73 		if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) {
74 			INFO("  System reset generated by MCU (MCSYSRST)\n");
75 		} else {
76 			INFO("  Local reset generated by MCU (MCSYSRST)\n");
77 		}
78 		return;
79 	}
80 
81 	if ((rstsr & RCC_MP_RSTSCLRR_MPSYSRSTF) != 0U) {
82 		INFO("  System reset generated by MPU (MPSYSRST)\n");
83 		return;
84 	}
85 
86 	if ((rstsr & RCC_MP_RSTSCLRR_HCSSRSTF) != 0U) {
87 		INFO("  Reset due to a clock failure on HSE\n");
88 		return;
89 	}
90 
91 	if ((rstsr & RCC_MP_RSTSCLRR_IWDG1RSTF) != 0U) {
92 		INFO("  IWDG1 Reset (rst_iwdg1)\n");
93 		return;
94 	}
95 
96 	if ((rstsr & RCC_MP_RSTSCLRR_IWDG2RSTF) != 0U) {
97 		INFO("  IWDG2 Reset (rst_iwdg2)\n");
98 		return;
99 	}
100 
101 	if ((rstsr & RCC_MP_RSTSCLRR_MPUP0RSTF) != 0U) {
102 		INFO("  MPU Processor 0 Reset\n");
103 		return;
104 	}
105 
106 	if ((rstsr & RCC_MP_RSTSCLRR_MPUP1RSTF) != 0U) {
107 		INFO("  MPU Processor 1 Reset\n");
108 		return;
109 	}
110 
111 	if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) {
112 		INFO("  Pad Reset from NRST\n");
113 		return;
114 	}
115 
116 	if ((rstsr & RCC_MP_RSTSCLRR_VCORERSTF) != 0U) {
117 		INFO("  Reset due to a failure of VDD_CORE\n");
118 		return;
119 	}
120 
121 	ERROR("  Unidentified reset reason\n");
122 }
123 
124 void bl2_el3_early_platform_setup(u_register_t arg0,
125 				  u_register_t arg1 __unused,
126 				  u_register_t arg2 __unused,
127 				  u_register_t arg3 __unused)
128 {
129 	stm32mp_save_boot_ctx_address(arg0);
130 }
131 
132 void bl2_platform_setup(void)
133 {
134 	int ret;
135 
136 	if (dt_pmic_status() > 0) {
137 		initialize_pmic();
138 	}
139 
140 	ret = stm32mp1_ddr_probe();
141 	if (ret < 0) {
142 		ERROR("Invalid DDR init: error %d\n", ret);
143 		panic();
144 	}
145 
146 	/* Map DDR for binary load, now with cacheable attribute */
147 	ret = mmap_add_dynamic_region(STM32MP_DDR_BASE, STM32MP_DDR_BASE,
148 				      STM32MP_DDR_MAX_SIZE, MT_MEMORY | MT_RW | MT_SECURE);
149 	if (ret < 0) {
150 		ERROR("DDR mapping: error %d\n", ret);
151 		panic();
152 	}
153 
154 #if STM32MP_USE_STM32IMAGE
155 #ifdef AARCH32_SP_OPTEE
156 	INFO("BL2 runs OP-TEE setup\n");
157 #else
158 	INFO("BL2 runs SP_MIN setup\n");
159 #endif
160 #endif /* STM32MP_USE_STM32IMAGE */
161 }
162 
163 void bl2_el3_plat_arch_setup(void)
164 {
165 	int32_t result;
166 	struct dt_node_info dt_uart_info;
167 	const char *board_model;
168 	boot_api_context_t *boot_context =
169 		(boot_api_context_t *)stm32mp_get_boot_ctx_address();
170 	uint32_t clk_rate;
171 	uintptr_t pwr_base;
172 	uintptr_t rcc_base;
173 
174 	mmap_add_region(BL_CODE_BASE, BL_CODE_BASE,
175 			BL_CODE_END - BL_CODE_BASE,
176 			MT_CODE | MT_SECURE);
177 
178 #if STM32MP_USE_STM32IMAGE
179 #ifdef AARCH32_SP_OPTEE
180 	mmap_add_region(STM32MP_OPTEE_BASE, STM32MP_OPTEE_BASE,
181 			STM32MP_OPTEE_SIZE,
182 			MT_MEMORY | MT_RW | MT_SECURE);
183 #else
184 	/* Prevent corruption of preloaded BL32 */
185 	mmap_add_region(BL32_BASE, BL32_BASE,
186 			BL32_LIMIT - BL32_BASE,
187 			MT_RO_DATA | MT_SECURE);
188 #endif
189 #endif /* STM32MP_USE_STM32IMAGE */
190 
191 	/* Prevent corruption of preloaded Device Tree */
192 	mmap_add_region(DTB_BASE, DTB_BASE,
193 			DTB_LIMIT - DTB_BASE,
194 			MT_RO_DATA | MT_SECURE);
195 
196 	configure_mmu();
197 
198 	if (dt_open_and_check(STM32MP_DTB_BASE) < 0) {
199 		panic();
200 	}
201 
202 	pwr_base = stm32mp_pwr_base();
203 	rcc_base = stm32mp_rcc_base();
204 
205 	/*
206 	 * Disable the backup domain write protection.
207 	 * The protection is enable at each reset by hardware
208 	 * and must be disabled by software.
209 	 */
210 	mmio_setbits_32(pwr_base + PWR_CR1, PWR_CR1_DBP);
211 
212 	while ((mmio_read_32(pwr_base + PWR_CR1) & PWR_CR1_DBP) == 0U) {
213 		;
214 	}
215 
216 	if (bsec_probe() != 0) {
217 		panic();
218 	}
219 
220 	/* Reset backup domain on cold boot cases */
221 	if ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_RTCSRC_MASK) == 0U) {
222 		mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST);
223 
224 		while ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_VSWRST) ==
225 		       0U) {
226 			;
227 		}
228 
229 		mmio_clrbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST);
230 	}
231 
232 	/* Disable MCKPROT */
233 	mmio_clrbits_32(rcc_base + RCC_TZCR, RCC_TZCR_MCKPROT);
234 
235 	generic_delay_timer_init();
236 
237 	if (stm32mp1_clk_probe() < 0) {
238 		panic();
239 	}
240 
241 	if (stm32mp1_clk_init() < 0) {
242 		panic();
243 	}
244 
245 	stm32mp1_syscfg_init();
246 
247 	result = dt_get_stdout_uart_info(&dt_uart_info);
248 
249 	if ((result <= 0) ||
250 	    (dt_uart_info.status == 0U) ||
251 	    (dt_uart_info.clock < 0) ||
252 	    (dt_uart_info.reset < 0)) {
253 		goto skip_console_init;
254 	}
255 
256 	if (dt_set_stdout_pinctrl() != 0) {
257 		goto skip_console_init;
258 	}
259 
260 	stm32mp_clk_enable((unsigned long)dt_uart_info.clock);
261 
262 	if (stm32mp_reset_assert((uint32_t)dt_uart_info.reset,
263 				 RESET_TIMEOUT_US_1MS) != 0) {
264 		panic();
265 	}
266 
267 	udelay(2);
268 
269 	if (stm32mp_reset_deassert((uint32_t)dt_uart_info.reset,
270 				   RESET_TIMEOUT_US_1MS) != 0) {
271 		panic();
272 	}
273 
274 	mdelay(1);
275 
276 	clk_rate = stm32mp_clk_get_rate((unsigned long)dt_uart_info.clock);
277 
278 	if (console_stm32_register(dt_uart_info.base, clk_rate,
279 				   STM32MP_UART_BAUDRATE, &console) == 0) {
280 		panic();
281 	}
282 
283 	console_set_scope(&console, CONSOLE_FLAG_BOOT |
284 			  CONSOLE_FLAG_CRASH | CONSOLE_FLAG_TRANSLATE_CRLF);
285 
286 	stm32mp_print_cpuinfo();
287 
288 	board_model = dt_get_board_model();
289 	if (board_model != NULL) {
290 		NOTICE("Model: %s\n", board_model);
291 	}
292 
293 	stm32mp_print_boardinfo();
294 
295 	if (boot_context->auth_status != BOOT_API_CTX_AUTH_NO) {
296 		NOTICE("Bootrom authentication %s\n",
297 		       (boot_context->auth_status == BOOT_API_CTX_AUTH_FAILED) ?
298 		       "failed" : "succeeded");
299 	}
300 
301 skip_console_init:
302 	if (stm32_iwdg_init() < 0) {
303 		panic();
304 	}
305 
306 	stm32_iwdg_refresh();
307 
308 	result = stm32mp1_dbgmcu_freeze_iwdg2();
309 	if (result != 0) {
310 		INFO("IWDG2 freeze error : %i\n", result);
311 	}
312 
313 	if (stm32_save_boot_interface(boot_context->boot_interface_selected,
314 				      boot_context->boot_interface_instance) !=
315 	    0) {
316 		ERROR("Cannot save boot interface\n");
317 	}
318 
319 	stm32mp1_auth_ops.check_key = boot_context->bootrom_ecdsa_check_key;
320 	stm32mp1_auth_ops.verify_signature =
321 		boot_context->bootrom_ecdsa_verify_signature;
322 
323 	stm32mp_init_auth(&stm32mp1_auth_ops);
324 
325 	stm32mp1_arch_security_setup();
326 
327 	print_reset_reason();
328 
329 	stm32mp_io_setup();
330 }
331 
332 /*******************************************************************************
333  * This function can be used by the platforms to update/use image
334  * information for given `image_id`.
335  ******************************************************************************/
336 int bl2_plat_handle_post_image_load(unsigned int image_id)
337 {
338 	int err = 0;
339 	bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
340 	bl_mem_params_node_t *bl32_mem_params;
341 	bl_mem_params_node_t *pager_mem_params __unused;
342 	bl_mem_params_node_t *paged_mem_params __unused;
343 
344 	assert(bl_mem_params != NULL);
345 
346 	switch (image_id) {
347 	case BL32_IMAGE_ID:
348 		if (optee_header_is_valid(bl_mem_params->image_info.image_base)) {
349 			/* BL32 is OP-TEE header */
350 			bl_mem_params->ep_info.pc = bl_mem_params->image_info.image_base;
351 			pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
352 			paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
353 			assert((pager_mem_params != NULL) && (paged_mem_params != NULL));
354 
355 #if STM32MP_USE_STM32IMAGE && defined(AARCH32_SP_OPTEE)
356 			/* Set OP-TEE extra image load areas at run-time */
357 			pager_mem_params->image_info.image_base = STM32MP_OPTEE_BASE;
358 			pager_mem_params->image_info.image_max_size = STM32MP_OPTEE_SIZE;
359 
360 			paged_mem_params->image_info.image_base = STM32MP_DDR_BASE +
361 								  dt_get_ddr_size() -
362 								  STM32MP_DDR_S_SIZE -
363 								  STM32MP_DDR_SHMEM_SIZE;
364 			paged_mem_params->image_info.image_max_size = STM32MP_DDR_S_SIZE;
365 #endif /* STM32MP_USE_STM32IMAGE && defined(AARCH32_SP_OPTEE) */
366 
367 			err = parse_optee_header(&bl_mem_params->ep_info,
368 						 &pager_mem_params->image_info,
369 						 &paged_mem_params->image_info);
370 			if (err) {
371 				ERROR("OPTEE header parse error.\n");
372 				panic();
373 			}
374 
375 			/* Set optee boot info from parsed header data */
376 			bl_mem_params->ep_info.args.arg0 = paged_mem_params->image_info.image_base;
377 			bl_mem_params->ep_info.args.arg1 = 0; /* Unused */
378 			bl_mem_params->ep_info.args.arg2 = 0; /* No DT supported */
379 		} else {
380 #if !STM32MP_USE_STM32IMAGE
381 			bl_mem_params->ep_info.pc = bl_mem_params->image_info.image_base;
382 #endif /* !STM32MP_USE_STM32IMAGE */
383 			bl_mem_params->ep_info.args.arg0 = 0;
384 		}
385 		break;
386 
387 	case BL33_IMAGE_ID:
388 		bl32_mem_params = get_bl_mem_params_node(BL32_IMAGE_ID);
389 		assert(bl32_mem_params != NULL);
390 		bl32_mem_params->ep_info.lr_svc = bl_mem_params->ep_info.pc;
391 		break;
392 
393 	default:
394 		/* Do nothing in default case */
395 		break;
396 	}
397 
398 	return err;
399 }
400 
401 void bl2_el3_plat_prepare_exit(void)
402 {
403 	stm32mp1_security_setup();
404 }
405