1 /* 2 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <string.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <common/desc_image_load.h> 16 #include <drivers/delay_timer.h> 17 #include <drivers/generic_delay_timer.h> 18 #include <drivers/mmc.h> 19 #include <drivers/st/bsec.h> 20 #include <drivers/st/stm32_console.h> 21 #include <drivers/st/stm32_iwdg.h> 22 #include <drivers/st/stm32mp_pmic.h> 23 #include <drivers/st/stm32mp_reset.h> 24 #include <drivers/st/stm32mp1_clk.h> 25 #include <drivers/st/stm32mp1_pwr.h> 26 #include <drivers/st/stm32mp1_ram.h> 27 #include <lib/mmio.h> 28 #include <lib/optee_utils.h> 29 #include <lib/xlat_tables/xlat_tables_v2.h> 30 #include <plat/common/platform.h> 31 32 #include <stm32mp1_context.h> 33 #include <stm32mp1_dbgmcu.h> 34 35 #define RESET_TIMEOUT_US_1MS 1000U 36 37 static console_t console; 38 static struct stm32mp_auth_ops stm32mp1_auth_ops; 39 40 static void print_reset_reason(void) 41 { 42 uint32_t rstsr = mmio_read_32(stm32mp_rcc_base() + RCC_MP_RSTSCLRR); 43 44 if (rstsr == 0U) { 45 WARN("Reset reason unknown\n"); 46 return; 47 } 48 49 INFO("Reset reason (0x%x):\n", rstsr); 50 51 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) == 0U) { 52 if ((rstsr & RCC_MP_RSTSCLRR_STDBYRSTF) != 0U) { 53 INFO("System exits from STANDBY\n"); 54 return; 55 } 56 57 if ((rstsr & RCC_MP_RSTSCLRR_CSTDBYRSTF) != 0U) { 58 INFO("MPU exits from CSTANDBY\n"); 59 return; 60 } 61 } 62 63 if ((rstsr & RCC_MP_RSTSCLRR_PORRSTF) != 0U) { 64 INFO(" Power-on Reset (rst_por)\n"); 65 return; 66 } 67 68 if ((rstsr & RCC_MP_RSTSCLRR_BORRSTF) != 0U) { 69 INFO(" Brownout Reset (rst_bor)\n"); 70 return; 71 } 72 73 if ((rstsr & RCC_MP_RSTSCLRR_MCSYSRSTF) != 0U) { 74 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) { 75 INFO(" System reset generated by MCU (MCSYSRST)\n"); 76 } else { 77 INFO(" Local reset generated by MCU (MCSYSRST)\n"); 78 } 79 return; 80 } 81 82 if ((rstsr & RCC_MP_RSTSCLRR_MPSYSRSTF) != 0U) { 83 INFO(" System reset generated by MPU (MPSYSRST)\n"); 84 return; 85 } 86 87 if ((rstsr & RCC_MP_RSTSCLRR_HCSSRSTF) != 0U) { 88 INFO(" Reset due to a clock failure on HSE\n"); 89 return; 90 } 91 92 if ((rstsr & RCC_MP_RSTSCLRR_IWDG1RSTF) != 0U) { 93 INFO(" IWDG1 Reset (rst_iwdg1)\n"); 94 return; 95 } 96 97 if ((rstsr & RCC_MP_RSTSCLRR_IWDG2RSTF) != 0U) { 98 INFO(" IWDG2 Reset (rst_iwdg2)\n"); 99 return; 100 } 101 102 if ((rstsr & RCC_MP_RSTSCLRR_MPUP0RSTF) != 0U) { 103 INFO(" MPU Processor 0 Reset\n"); 104 return; 105 } 106 107 if ((rstsr & RCC_MP_RSTSCLRR_MPUP1RSTF) != 0U) { 108 INFO(" MPU Processor 1 Reset\n"); 109 return; 110 } 111 112 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) { 113 INFO(" Pad Reset from NRST\n"); 114 return; 115 } 116 117 if ((rstsr & RCC_MP_RSTSCLRR_VCORERSTF) != 0U) { 118 INFO(" Reset due to a failure of VDD_CORE\n"); 119 return; 120 } 121 122 ERROR(" Unidentified reset reason\n"); 123 } 124 125 void bl2_el3_early_platform_setup(u_register_t arg0, 126 u_register_t arg1 __unused, 127 u_register_t arg2 __unused, 128 u_register_t arg3 __unused) 129 { 130 stm32mp_save_boot_ctx_address(arg0); 131 } 132 133 void bl2_platform_setup(void) 134 { 135 int ret; 136 137 if (dt_pmic_status() > 0) { 138 initialize_pmic(); 139 } 140 141 ret = stm32mp1_ddr_probe(); 142 if (ret < 0) { 143 ERROR("Invalid DDR init: error %d\n", ret); 144 panic(); 145 } 146 147 /* Map DDR for binary load, now with cacheable attribute */ 148 ret = mmap_add_dynamic_region(STM32MP_DDR_BASE, STM32MP_DDR_BASE, 149 STM32MP_DDR_MAX_SIZE, MT_MEMORY | MT_RW | MT_SECURE); 150 if (ret < 0) { 151 ERROR("DDR mapping: error %d\n", ret); 152 panic(); 153 } 154 155 #if STM32MP_USE_STM32IMAGE 156 #ifdef AARCH32_SP_OPTEE 157 INFO("BL2 runs OP-TEE setup\n"); 158 #else 159 INFO("BL2 runs SP_MIN setup\n"); 160 #endif 161 #endif /* STM32MP_USE_STM32IMAGE */ 162 } 163 164 void bl2_el3_plat_arch_setup(void) 165 { 166 int32_t result; 167 struct dt_node_info dt_uart_info; 168 const char *board_model; 169 boot_api_context_t *boot_context = 170 (boot_api_context_t *)stm32mp_get_boot_ctx_address(); 171 uint32_t clk_rate; 172 uintptr_t pwr_base; 173 uintptr_t rcc_base; 174 175 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, 176 BL_CODE_END - BL_CODE_BASE, 177 MT_CODE | MT_SECURE); 178 179 #if STM32MP_USE_STM32IMAGE 180 #ifdef AARCH32_SP_OPTEE 181 mmap_add_region(STM32MP_OPTEE_BASE, STM32MP_OPTEE_BASE, 182 STM32MP_OPTEE_SIZE, 183 MT_MEMORY | MT_RW | MT_SECURE); 184 #else 185 /* Prevent corruption of preloaded BL32 */ 186 mmap_add_region(BL32_BASE, BL32_BASE, 187 BL32_LIMIT - BL32_BASE, 188 MT_RO_DATA | MT_SECURE); 189 #endif 190 #endif /* STM32MP_USE_STM32IMAGE */ 191 192 /* Prevent corruption of preloaded Device Tree */ 193 mmap_add_region(DTB_BASE, DTB_BASE, 194 DTB_LIMIT - DTB_BASE, 195 MT_RO_DATA | MT_SECURE); 196 197 configure_mmu(); 198 199 if (dt_open_and_check(STM32MP_DTB_BASE) < 0) { 200 panic(); 201 } 202 203 pwr_base = stm32mp_pwr_base(); 204 rcc_base = stm32mp_rcc_base(); 205 206 /* 207 * Disable the backup domain write protection. 208 * The protection is enable at each reset by hardware 209 * and must be disabled by software. 210 */ 211 mmio_setbits_32(pwr_base + PWR_CR1, PWR_CR1_DBP); 212 213 while ((mmio_read_32(pwr_base + PWR_CR1) & PWR_CR1_DBP) == 0U) { 214 ; 215 } 216 217 if (bsec_probe() != 0) { 218 panic(); 219 } 220 221 /* Reset backup domain on cold boot cases */ 222 if ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_RTCSRC_MASK) == 0U) { 223 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST); 224 225 while ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_VSWRST) == 226 0U) { 227 ; 228 } 229 230 mmio_clrbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST); 231 } 232 233 /* Disable MCKPROT */ 234 mmio_clrbits_32(rcc_base + RCC_TZCR, RCC_TZCR_MCKPROT); 235 236 generic_delay_timer_init(); 237 238 if (stm32mp1_clk_probe() < 0) { 239 panic(); 240 } 241 242 if (stm32mp1_clk_init() < 0) { 243 panic(); 244 } 245 246 stm32mp1_syscfg_init(); 247 248 result = dt_get_stdout_uart_info(&dt_uart_info); 249 250 if ((result <= 0) || 251 (dt_uart_info.status == 0U) || 252 (dt_uart_info.clock < 0) || 253 (dt_uart_info.reset < 0)) { 254 goto skip_console_init; 255 } 256 257 if (dt_set_stdout_pinctrl() != 0) { 258 goto skip_console_init; 259 } 260 261 stm32mp_clk_enable((unsigned long)dt_uart_info.clock); 262 263 if (stm32mp_reset_assert((uint32_t)dt_uart_info.reset, 264 RESET_TIMEOUT_US_1MS) != 0) { 265 panic(); 266 } 267 268 udelay(2); 269 270 if (stm32mp_reset_deassert((uint32_t)dt_uart_info.reset, 271 RESET_TIMEOUT_US_1MS) != 0) { 272 panic(); 273 } 274 275 mdelay(1); 276 277 clk_rate = stm32mp_clk_get_rate((unsigned long)dt_uart_info.clock); 278 279 if (console_stm32_register(dt_uart_info.base, clk_rate, 280 STM32MP_UART_BAUDRATE, &console) == 0) { 281 panic(); 282 } 283 284 console_set_scope(&console, CONSOLE_FLAG_BOOT | 285 CONSOLE_FLAG_CRASH | CONSOLE_FLAG_TRANSLATE_CRLF); 286 287 stm32mp_print_cpuinfo(); 288 289 board_model = dt_get_board_model(); 290 if (board_model != NULL) { 291 NOTICE("Model: %s\n", board_model); 292 } 293 294 stm32mp_print_boardinfo(); 295 296 if (boot_context->auth_status != BOOT_API_CTX_AUTH_NO) { 297 NOTICE("Bootrom authentication %s\n", 298 (boot_context->auth_status == BOOT_API_CTX_AUTH_FAILED) ? 299 "failed" : "succeeded"); 300 } 301 302 skip_console_init: 303 if (stm32_iwdg_init() < 0) { 304 panic(); 305 } 306 307 stm32_iwdg_refresh(); 308 309 result = stm32mp1_dbgmcu_freeze_iwdg2(); 310 if (result != 0) { 311 INFO("IWDG2 freeze error : %i\n", result); 312 } 313 314 if (stm32_save_boot_interface(boot_context->boot_interface_selected, 315 boot_context->boot_interface_instance) != 316 0) { 317 ERROR("Cannot save boot interface\n"); 318 } 319 320 stm32mp1_auth_ops.check_key = boot_context->bootrom_ecdsa_check_key; 321 stm32mp1_auth_ops.verify_signature = 322 boot_context->bootrom_ecdsa_verify_signature; 323 324 stm32mp_init_auth(&stm32mp1_auth_ops); 325 326 stm32mp1_arch_security_setup(); 327 328 print_reset_reason(); 329 330 stm32mp_io_setup(); 331 } 332 333 /******************************************************************************* 334 * This function can be used by the platforms to update/use image 335 * information for given `image_id`. 336 ******************************************************************************/ 337 int bl2_plat_handle_post_image_load(unsigned int image_id) 338 { 339 int err = 0; 340 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 341 bl_mem_params_node_t *bl32_mem_params; 342 bl_mem_params_node_t *pager_mem_params __unused; 343 bl_mem_params_node_t *paged_mem_params __unused; 344 345 assert(bl_mem_params != NULL); 346 347 switch (image_id) { 348 case BL32_IMAGE_ID: 349 if (optee_header_is_valid(bl_mem_params->image_info.image_base)) { 350 /* BL32 is OP-TEE header */ 351 bl_mem_params->ep_info.pc = bl_mem_params->image_info.image_base; 352 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 353 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); 354 assert((pager_mem_params != NULL) && (paged_mem_params != NULL)); 355 356 #if STM32MP_USE_STM32IMAGE && defined(AARCH32_SP_OPTEE) 357 /* Set OP-TEE extra image load areas at run-time */ 358 pager_mem_params->image_info.image_base = STM32MP_OPTEE_BASE; 359 pager_mem_params->image_info.image_max_size = STM32MP_OPTEE_SIZE; 360 361 paged_mem_params->image_info.image_base = STM32MP_DDR_BASE + 362 dt_get_ddr_size() - 363 STM32MP_DDR_S_SIZE - 364 STM32MP_DDR_SHMEM_SIZE; 365 paged_mem_params->image_info.image_max_size = STM32MP_DDR_S_SIZE; 366 #endif /* STM32MP_USE_STM32IMAGE && defined(AARCH32_SP_OPTEE) */ 367 368 err = parse_optee_header(&bl_mem_params->ep_info, 369 &pager_mem_params->image_info, 370 &paged_mem_params->image_info); 371 if (err) { 372 ERROR("OPTEE header parse error.\n"); 373 panic(); 374 } 375 376 /* Set optee boot info from parsed header data */ 377 bl_mem_params->ep_info.args.arg0 = paged_mem_params->image_info.image_base; 378 bl_mem_params->ep_info.args.arg1 = 0; /* Unused */ 379 bl_mem_params->ep_info.args.arg2 = 0; /* No DT supported */ 380 } else { 381 #if !STM32MP_USE_STM32IMAGE 382 bl_mem_params->ep_info.pc = bl_mem_params->image_info.image_base; 383 #endif /* !STM32MP_USE_STM32IMAGE */ 384 bl_mem_params->ep_info.args.arg0 = 0; 385 } 386 break; 387 388 case BL33_IMAGE_ID: 389 bl32_mem_params = get_bl_mem_params_node(BL32_IMAGE_ID); 390 assert(bl32_mem_params != NULL); 391 bl32_mem_params->ep_info.lr_svc = bl_mem_params->ep_info.pc; 392 break; 393 394 default: 395 /* Do nothing in default case */ 396 break; 397 } 398 399 #if STM32MP_SDMMC || STM32MP_EMMC 400 /* 401 * Invalidate remaining data read from MMC but not flushed by load_image_flush(). 402 * We take the worst case which is 2 MMC blocks. 403 */ 404 if ((image_id != FW_CONFIG_ID) && 405 ((bl_mem_params->image_info.h.attr & IMAGE_ATTRIB_SKIP_LOADING) == 0U)) { 406 inv_dcache_range(bl_mem_params->image_info.image_base + 407 bl_mem_params->image_info.image_size, 408 2U * MMC_BLOCK_SIZE); 409 } 410 #endif /* STM32MP_SDMMC || STM32MP_EMMC */ 411 412 return err; 413 } 414 415 void bl2_el3_plat_prepare_exit(void) 416 { 417 stm32mp1_security_setup(); 418 } 419