1 /* 2 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <string.h> 9 10 #include <arch_helpers.h> 11 #include <common/debug.h> 12 #include <common/desc_image_load.h> 13 #include <drivers/io/io_block.h> 14 #include <drivers/io/io_driver.h> 15 #include <drivers/io/io_fip.h> 16 #include <drivers/io/io_mtd.h> 17 #include <drivers/io/io_storage.h> 18 #include <drivers/mmc.h> 19 #include <drivers/partition/partition.h> 20 #include <drivers/raw_nand.h> 21 #include <drivers/spi_nand.h> 22 #include <drivers/spi_nor.h> 23 #include <drivers/st/io_mmc.h> 24 #include <drivers/st/stm32_fmc2_nand.h> 25 #include <drivers/st/stm32_qspi.h> 26 #include <drivers/st/stm32_sdmmc2.h> 27 #include <lib/mmio.h> 28 #include <lib/utils.h> 29 #include <plat/common/platform.h> 30 #include <tools_share/firmware_image_package.h> 31 32 #include <platform_def.h> 33 34 /* IO devices */ 35 uintptr_t fip_dev_handle; 36 uintptr_t storage_dev_handle; 37 38 static const io_dev_connector_t *fip_dev_con; 39 40 #if STM32MP_SDMMC || STM32MP_EMMC 41 static struct mmc_device_info mmc_info; 42 static io_block_spec_t gpt_block_spec = { 43 .offset = 0U, 44 .length = 34U * MMC_BLOCK_SIZE, /* Size of GPT table */ 45 }; 46 47 static uint32_t block_buffer[MMC_BLOCK_SIZE] __aligned(MMC_BLOCK_SIZE); 48 49 static io_block_dev_spec_t mmc_block_dev_spec = { 50 /* It's used as temp buffer in block driver */ 51 .buffer = { 52 .offset = (size_t)&block_buffer, 53 .length = MMC_BLOCK_SIZE, 54 }, 55 .ops = { 56 .read = mmc_read_blocks, 57 .write = NULL, 58 }, 59 .block_size = MMC_BLOCK_SIZE, 60 }; 61 62 static const io_dev_connector_t *mmc_dev_con; 63 #endif /* STM32MP_SDMMC || STM32MP_EMMC */ 64 65 #if STM32MP_SPI_NOR 66 static io_mtd_dev_spec_t spi_nor_dev_spec = { 67 .ops = { 68 .init = spi_nor_init, 69 .read = spi_nor_read, 70 }, 71 }; 72 #endif 73 74 #if STM32MP_RAW_NAND 75 static io_mtd_dev_spec_t nand_dev_spec = { 76 .ops = { 77 .init = nand_raw_init, 78 .read = nand_read, 79 .seek = nand_seek_bb 80 }, 81 }; 82 83 static const io_dev_connector_t *nand_dev_con; 84 #endif 85 86 #if STM32MP_SPI_NAND 87 static io_mtd_dev_spec_t spi_nand_dev_spec = { 88 .ops = { 89 .init = spi_nand_init, 90 .read = nand_read, 91 .seek = nand_seek_bb 92 }, 93 }; 94 #endif 95 96 #if STM32MP_SPI_NAND || STM32MP_SPI_NOR 97 static const io_dev_connector_t *spi_dev_con; 98 #endif 99 100 static const io_uuid_spec_t fw_config_uuid_spec = { 101 .uuid = UUID_FW_CONFIG, 102 }; 103 104 static const io_uuid_spec_t bl33_partition_spec = { 105 .uuid = UUID_NON_TRUSTED_FIRMWARE_BL33 106 }; 107 108 static const io_uuid_spec_t tos_fw_config_uuid_spec = { 109 .uuid = UUID_TOS_FW_CONFIG, 110 }; 111 112 static const io_uuid_spec_t hw_config_uuid_spec = { 113 .uuid = UUID_HW_CONFIG, 114 }; 115 116 #ifdef AARCH32_SP_OPTEE 117 static const io_uuid_spec_t optee_header_partition_spec = { 118 .uuid = UUID_SECURE_PAYLOAD_BL32 119 }; 120 121 static const io_uuid_spec_t optee_core_partition_spec = { 122 .uuid = UUID_SECURE_PAYLOAD_BL32_EXTRA1 123 }; 124 125 static const io_uuid_spec_t optee_paged_partition_spec = { 126 .uuid = UUID_SECURE_PAYLOAD_BL32_EXTRA2 127 }; 128 #else 129 static const io_uuid_spec_t bl32_partition_spec = { 130 .uuid = UUID_SECURE_PAYLOAD_BL32 131 }; 132 #endif 133 134 static io_block_spec_t image_block_spec = { 135 .offset = 0U, 136 .length = 0U, 137 }; 138 139 static int open_fip(const uintptr_t spec); 140 static int open_storage(const uintptr_t spec); 141 142 struct plat_io_policy { 143 uintptr_t *dev_handle; 144 uintptr_t image_spec; 145 int (*check)(const uintptr_t spec); 146 }; 147 148 static const struct plat_io_policy policies[] = { 149 [FIP_IMAGE_ID] = { 150 .dev_handle = &storage_dev_handle, 151 .image_spec = (uintptr_t)&image_block_spec, 152 .check = open_storage 153 }, 154 #ifdef AARCH32_SP_OPTEE 155 [BL32_IMAGE_ID] = { 156 .dev_handle = &fip_dev_handle, 157 .image_spec = (uintptr_t)&optee_header_partition_spec, 158 .check = open_fip 159 }, 160 [BL32_EXTRA1_IMAGE_ID] = { 161 .dev_handle = &fip_dev_handle, 162 .image_spec = (uintptr_t)&optee_core_partition_spec, 163 .check = open_fip 164 }, 165 [BL32_EXTRA2_IMAGE_ID] = { 166 .dev_handle = &fip_dev_handle, 167 .image_spec = (uintptr_t)&optee_paged_partition_spec, 168 .check = open_fip 169 }, 170 #else 171 [BL32_IMAGE_ID] = { 172 .dev_handle = &fip_dev_handle, 173 .image_spec = (uintptr_t)&bl32_partition_spec, 174 .check = open_fip 175 }, 176 #endif 177 [BL33_IMAGE_ID] = { 178 .dev_handle = &fip_dev_handle, 179 .image_spec = (uintptr_t)&bl33_partition_spec, 180 .check = open_fip 181 }, 182 [FW_CONFIG_ID] = { 183 .dev_handle = &fip_dev_handle, 184 .image_spec = (uintptr_t)&fw_config_uuid_spec, 185 .check = open_fip 186 }, 187 [TOS_FW_CONFIG_ID] = { 188 .dev_handle = &fip_dev_handle, 189 .image_spec = (uintptr_t)&tos_fw_config_uuid_spec, 190 .check = open_fip 191 }, 192 [HW_CONFIG_ID] = { 193 .dev_handle = &fip_dev_handle, 194 .image_spec = (uintptr_t)&hw_config_uuid_spec, 195 .check = open_fip 196 }, 197 #if STM32MP_SDMMC || STM32MP_EMMC 198 [GPT_IMAGE_ID] = { 199 .dev_handle = &storage_dev_handle, 200 .image_spec = (uintptr_t)&gpt_block_spec, 201 .check = open_storage 202 }, 203 #endif 204 }; 205 206 static int open_fip(const uintptr_t spec) 207 { 208 return io_dev_init(fip_dev_handle, (uintptr_t)FIP_IMAGE_ID); 209 } 210 211 static int open_storage(const uintptr_t spec) 212 { 213 return io_dev_init(storage_dev_handle, 0); 214 } 215 216 static void print_boot_device(boot_api_context_t *boot_context) 217 { 218 switch (boot_context->boot_interface_selected) { 219 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD: 220 INFO("Using SDMMC\n"); 221 break; 222 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC: 223 INFO("Using EMMC\n"); 224 break; 225 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI: 226 INFO("Using QSPI NOR\n"); 227 break; 228 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC: 229 INFO("Using FMC NAND\n"); 230 break; 231 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_QSPI: 232 INFO("Using SPI NAND\n"); 233 break; 234 default: 235 ERROR("Boot interface %u not found\n", 236 boot_context->boot_interface_selected); 237 panic(); 238 break; 239 } 240 241 if (boot_context->boot_interface_instance != 0U) { 242 INFO(" Instance %d\n", boot_context->boot_interface_instance); 243 } 244 } 245 246 #if STM32MP_SDMMC || STM32MP_EMMC 247 static void boot_mmc(enum mmc_device_type mmc_dev_type, 248 uint16_t boot_interface_instance) 249 { 250 int io_result __unused; 251 struct stm32_sdmmc2_params params; 252 253 zeromem(¶ms, sizeof(struct stm32_sdmmc2_params)); 254 255 mmc_info.mmc_dev_type = mmc_dev_type; 256 257 switch (boot_interface_instance) { 258 case 1: 259 params.reg_base = STM32MP_SDMMC1_BASE; 260 break; 261 case 2: 262 params.reg_base = STM32MP_SDMMC2_BASE; 263 break; 264 case 3: 265 params.reg_base = STM32MP_SDMMC3_BASE; 266 break; 267 default: 268 WARN("SDMMC instance not found, using default\n"); 269 if (mmc_dev_type == MMC_IS_SD) { 270 params.reg_base = STM32MP_SDMMC1_BASE; 271 } else { 272 params.reg_base = STM32MP_SDMMC2_BASE; 273 } 274 break; 275 } 276 277 params.device_info = &mmc_info; 278 if (stm32_sdmmc2_mmc_init(¶ms) != 0) { 279 ERROR("SDMMC%u init failed\n", boot_interface_instance); 280 panic(); 281 } 282 283 /* Open MMC as a block device to read GPT table */ 284 io_result = register_io_dev_block(&mmc_dev_con); 285 if (io_result != 0) { 286 panic(); 287 } 288 289 io_result = io_dev_open(mmc_dev_con, (uintptr_t)&mmc_block_dev_spec, 290 &storage_dev_handle); 291 assert(io_result == 0); 292 } 293 #endif /* STM32MP_SDMMC || STM32MP_EMMC */ 294 295 #if STM32MP_SPI_NOR 296 static void boot_spi_nor(boot_api_context_t *boot_context) 297 { 298 int io_result __unused; 299 300 io_result = stm32_qspi_init(); 301 assert(io_result == 0); 302 303 io_result = register_io_dev_mtd(&spi_dev_con); 304 assert(io_result == 0); 305 306 /* Open connections to device */ 307 io_result = io_dev_open(spi_dev_con, 308 (uintptr_t)&spi_nor_dev_spec, 309 &storage_dev_handle); 310 assert(io_result == 0); 311 } 312 #endif /* STM32MP_SPI_NOR */ 313 314 #if STM32MP_RAW_NAND 315 static void boot_fmc2_nand(boot_api_context_t *boot_context) 316 { 317 int io_result __unused; 318 319 io_result = stm32_fmc2_init(); 320 assert(io_result == 0); 321 322 /* Register the IO device on this platform */ 323 io_result = register_io_dev_mtd(&nand_dev_con); 324 assert(io_result == 0); 325 326 /* Open connections to device */ 327 io_result = io_dev_open(nand_dev_con, (uintptr_t)&nand_dev_spec, 328 &storage_dev_handle); 329 assert(io_result == 0); 330 } 331 #endif /* STM32MP_RAW_NAND */ 332 333 #if STM32MP_SPI_NAND 334 static void boot_spi_nand(boot_api_context_t *boot_context) 335 { 336 int io_result __unused; 337 338 io_result = stm32_qspi_init(); 339 assert(io_result == 0); 340 341 io_result = register_io_dev_mtd(&spi_dev_con); 342 assert(io_result == 0); 343 344 /* Open connections to device */ 345 io_result = io_dev_open(spi_dev_con, 346 (uintptr_t)&spi_nand_dev_spec, 347 &storage_dev_handle); 348 assert(io_result == 0); 349 } 350 #endif /* STM32MP_SPI_NAND */ 351 352 void stm32mp_io_setup(void) 353 { 354 int io_result __unused; 355 boot_api_context_t *boot_context = 356 (boot_api_context_t *)stm32mp_get_boot_ctx_address(); 357 358 print_boot_device(boot_context); 359 360 if ((boot_context->boot_partition_used_toboot == 1U) || 361 (boot_context->boot_partition_used_toboot == 2U)) { 362 INFO("Boot used partition fsbl%u\n", 363 boot_context->boot_partition_used_toboot); 364 } 365 366 io_result = register_io_dev_fip(&fip_dev_con); 367 assert(io_result == 0); 368 369 io_result = io_dev_open(fip_dev_con, (uintptr_t)NULL, 370 &fip_dev_handle); 371 372 switch (boot_context->boot_interface_selected) { 373 #if STM32MP_SDMMC 374 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD: 375 dmbsy(); 376 boot_mmc(MMC_IS_SD, boot_context->boot_interface_instance); 377 break; 378 #endif 379 #if STM32MP_EMMC 380 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC: 381 dmbsy(); 382 boot_mmc(MMC_IS_EMMC, boot_context->boot_interface_instance); 383 break; 384 #endif 385 #if STM32MP_SPI_NOR 386 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI: 387 dmbsy(); 388 boot_spi_nor(boot_context); 389 break; 390 #endif 391 #if STM32MP_RAW_NAND 392 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC: 393 dmbsy(); 394 boot_fmc2_nand(boot_context); 395 break; 396 #endif 397 #if STM32MP_SPI_NAND 398 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_QSPI: 399 dmbsy(); 400 boot_spi_nand(boot_context); 401 break; 402 #endif 403 404 default: 405 ERROR("Boot interface %d not supported\n", 406 boot_context->boot_interface_selected); 407 panic(); 408 break; 409 } 410 } 411 412 int bl2_plat_handle_pre_image_load(unsigned int image_id) 413 { 414 static bool gpt_init_done __unused; 415 uint16_t boot_itf = stm32mp_get_boot_itf_selected(); 416 417 switch (boot_itf) { 418 #if STM32MP_SDMMC || STM32MP_EMMC 419 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD: 420 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC: 421 if (!gpt_init_done) { 422 const partition_entry_t *entry; 423 424 partition_init(GPT_IMAGE_ID); 425 entry = get_partition_entry(FIP_IMAGE_NAME); 426 if (entry == NULL) { 427 ERROR("Could NOT find the %s partition!\n", 428 FIP_IMAGE_NAME); 429 return -ENOENT; 430 } 431 432 image_block_spec.offset = entry->start; 433 image_block_spec.length = entry->length; 434 435 gpt_init_done = true; 436 } else { 437 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 438 439 mmc_block_dev_spec.buffer.offset = bl_mem_params->image_info.image_base; 440 mmc_block_dev_spec.buffer.length = bl_mem_params->image_info.image_max_size; 441 } 442 443 break; 444 #endif 445 446 #if STM32MP_RAW_NAND || STM32MP_SPI_NAND 447 #if STM32MP_RAW_NAND 448 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC: 449 #endif 450 #if STM32MP_SPI_NAND 451 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_QSPI: 452 #endif 453 image_block_spec.offset = STM32MP_NAND_FIP_OFFSET; 454 break; 455 #endif 456 457 #if STM32MP_SPI_NOR 458 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI: 459 image_block_spec.offset = STM32MP_NOR_FIP_OFFSET; 460 break; 461 #endif 462 463 default: 464 ERROR("FIP Not found\n"); 465 panic(); 466 } 467 468 return 0; 469 } 470 471 /* 472 * Return an IO device handle and specification which can be used to access 473 * an image. Use this to enforce platform load policy. 474 */ 475 int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle, 476 uintptr_t *image_spec) 477 { 478 int rc; 479 const struct plat_io_policy *policy; 480 481 assert(image_id < ARRAY_SIZE(policies)); 482 483 policy = &policies[image_id]; 484 rc = policy->check(policy->image_spec); 485 if (rc == 0) { 486 *image_spec = policy->image_spec; 487 *dev_handle = *(policy->dev_handle); 488 } 489 490 return rc; 491 } 492