1 /* 2 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <string.h> 9 10 #include <arch_helpers.h> 11 #include <common/debug.h> 12 #include <common/desc_image_load.h> 13 #include <drivers/io/io_block.h> 14 #include <drivers/io/io_driver.h> 15 #include <drivers/io/io_fip.h> 16 #include <drivers/io/io_mtd.h> 17 #include <drivers/io/io_storage.h> 18 #include <drivers/mmc.h> 19 #include <drivers/partition/partition.h> 20 #include <drivers/raw_nand.h> 21 #include <drivers/spi_nand.h> 22 #include <drivers/spi_nor.h> 23 #include <drivers/st/io_mmc.h> 24 #include <drivers/st/stm32_fmc2_nand.h> 25 #include <drivers/st/stm32_qspi.h> 26 #include <drivers/st/stm32_sdmmc2.h> 27 #include <lib/mmio.h> 28 #include <lib/utils.h> 29 #include <plat/common/platform.h> 30 #include <tools_share/firmware_image_package.h> 31 32 #include <platform_def.h> 33 34 /* IO devices */ 35 uintptr_t fip_dev_handle; 36 uintptr_t storage_dev_handle; 37 38 static const io_dev_connector_t *fip_dev_con; 39 40 #if STM32MP_SDMMC || STM32MP_EMMC 41 static struct mmc_device_info mmc_info; 42 static io_block_spec_t gpt_block_spec = { 43 .offset = 0U, 44 .length = 34U * MMC_BLOCK_SIZE, /* Size of GPT table */ 45 }; 46 47 static uint32_t block_buffer[MMC_BLOCK_SIZE] __aligned(MMC_BLOCK_SIZE); 48 49 static io_block_dev_spec_t mmc_block_dev_spec = { 50 /* It's used as temp buffer in block driver */ 51 .buffer = { 52 .offset = (size_t)&block_buffer, 53 .length = MMC_BLOCK_SIZE, 54 }, 55 .ops = { 56 .read = mmc_read_blocks, 57 .write = NULL, 58 }, 59 .block_size = MMC_BLOCK_SIZE, 60 }; 61 62 static const io_dev_connector_t *mmc_dev_con; 63 #endif /* STM32MP_SDMMC || STM32MP_EMMC */ 64 65 #if STM32MP_SPI_NOR 66 static io_mtd_dev_spec_t spi_nor_dev_spec = { 67 .ops = { 68 .init = spi_nor_init, 69 .read = spi_nor_read, 70 }, 71 }; 72 #endif 73 74 #if STM32MP_RAW_NAND 75 static io_mtd_dev_spec_t nand_dev_spec = { 76 .ops = { 77 .init = nand_raw_init, 78 .read = nand_read, 79 .seek = nand_seek_bb 80 }, 81 }; 82 83 static const io_dev_connector_t *nand_dev_con; 84 #endif 85 86 #if STM32MP_SPI_NAND 87 static io_mtd_dev_spec_t spi_nand_dev_spec = { 88 .ops = { 89 .init = spi_nand_init, 90 .read = nand_read, 91 .seek = nand_seek_bb 92 }, 93 }; 94 #endif 95 96 #if STM32MP_SPI_NAND || STM32MP_SPI_NOR 97 static const io_dev_connector_t *spi_dev_con; 98 #endif 99 100 static const io_uuid_spec_t bl33_partition_spec = { 101 .uuid = UUID_NON_TRUSTED_FIRMWARE_BL33 102 }; 103 104 static const io_uuid_spec_t tos_fw_config_uuid_spec = { 105 .uuid = UUID_TOS_FW_CONFIG, 106 }; 107 108 static const io_uuid_spec_t hw_config_uuid_spec = { 109 .uuid = UUID_HW_CONFIG, 110 }; 111 112 #ifdef AARCH32_SP_OPTEE 113 static const io_uuid_spec_t optee_header_partition_spec = { 114 .uuid = UUID_SECURE_PAYLOAD_BL32 115 }; 116 117 static const io_uuid_spec_t optee_core_partition_spec = { 118 .uuid = UUID_SECURE_PAYLOAD_BL32_EXTRA1 119 }; 120 121 static const io_uuid_spec_t optee_paged_partition_spec = { 122 .uuid = UUID_SECURE_PAYLOAD_BL32_EXTRA2 123 }; 124 #else 125 static const io_uuid_spec_t bl32_partition_spec = { 126 .uuid = UUID_SECURE_PAYLOAD_BL32 127 }; 128 #endif 129 130 static io_block_spec_t image_block_spec = { 131 .offset = 0U, 132 .length = 0U, 133 }; 134 135 static int open_fip(const uintptr_t spec); 136 static int open_storage(const uintptr_t spec); 137 138 struct plat_io_policy { 139 uintptr_t *dev_handle; 140 uintptr_t image_spec; 141 int (*check)(const uintptr_t spec); 142 }; 143 144 static const struct plat_io_policy policies[] = { 145 [FIP_IMAGE_ID] = { 146 .dev_handle = &storage_dev_handle, 147 .image_spec = (uintptr_t)&image_block_spec, 148 .check = open_storage 149 }, 150 #ifdef AARCH32_SP_OPTEE 151 [BL32_IMAGE_ID] = { 152 .dev_handle = &fip_dev_handle, 153 .image_spec = (uintptr_t)&optee_header_partition_spec, 154 .check = open_fip 155 }, 156 [BL32_EXTRA1_IMAGE_ID] = { 157 .dev_handle = &fip_dev_handle, 158 .image_spec = (uintptr_t)&optee_core_partition_spec, 159 .check = open_fip 160 }, 161 [BL32_EXTRA2_IMAGE_ID] = { 162 .dev_handle = &fip_dev_handle, 163 .image_spec = (uintptr_t)&optee_paged_partition_spec, 164 .check = open_fip 165 }, 166 #else 167 [BL32_IMAGE_ID] = { 168 .dev_handle = &fip_dev_handle, 169 .image_spec = (uintptr_t)&bl32_partition_spec, 170 .check = open_fip 171 }, 172 #endif 173 [BL33_IMAGE_ID] = { 174 .dev_handle = &fip_dev_handle, 175 .image_spec = (uintptr_t)&bl33_partition_spec, 176 .check = open_fip 177 }, 178 [TOS_FW_CONFIG_ID] = { 179 .dev_handle = &fip_dev_handle, 180 .image_spec = (uintptr_t)&tos_fw_config_uuid_spec, 181 .check = open_fip 182 }, 183 [HW_CONFIG_ID] = { 184 .dev_handle = &fip_dev_handle, 185 .image_spec = (uintptr_t)&hw_config_uuid_spec, 186 .check = open_fip 187 }, 188 #if STM32MP_SDMMC || STM32MP_EMMC 189 [GPT_IMAGE_ID] = { 190 .dev_handle = &storage_dev_handle, 191 .image_spec = (uintptr_t)&gpt_block_spec, 192 .check = open_storage 193 }, 194 #endif 195 }; 196 197 static int open_fip(const uintptr_t spec) 198 { 199 return io_dev_init(fip_dev_handle, (uintptr_t)FIP_IMAGE_ID); 200 } 201 202 static int open_storage(const uintptr_t spec) 203 { 204 return io_dev_init(storage_dev_handle, 0); 205 } 206 207 static void print_boot_device(boot_api_context_t *boot_context) 208 { 209 switch (boot_context->boot_interface_selected) { 210 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD: 211 INFO("Using SDMMC\n"); 212 break; 213 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC: 214 INFO("Using EMMC\n"); 215 break; 216 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI: 217 INFO("Using QSPI NOR\n"); 218 break; 219 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC: 220 INFO("Using FMC NAND\n"); 221 break; 222 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_QSPI: 223 INFO("Using SPI NAND\n"); 224 break; 225 default: 226 ERROR("Boot interface %u not found\n", 227 boot_context->boot_interface_selected); 228 panic(); 229 break; 230 } 231 232 if (boot_context->boot_interface_instance != 0U) { 233 INFO(" Instance %d\n", boot_context->boot_interface_instance); 234 } 235 } 236 237 #if STM32MP_SDMMC || STM32MP_EMMC 238 static void boot_mmc(enum mmc_device_type mmc_dev_type, 239 uint16_t boot_interface_instance) 240 { 241 int io_result __unused; 242 struct stm32_sdmmc2_params params; 243 244 zeromem(¶ms, sizeof(struct stm32_sdmmc2_params)); 245 246 mmc_info.mmc_dev_type = mmc_dev_type; 247 248 switch (boot_interface_instance) { 249 case 1: 250 params.reg_base = STM32MP_SDMMC1_BASE; 251 break; 252 case 2: 253 params.reg_base = STM32MP_SDMMC2_BASE; 254 break; 255 case 3: 256 params.reg_base = STM32MP_SDMMC3_BASE; 257 break; 258 default: 259 WARN("SDMMC instance not found, using default\n"); 260 if (mmc_dev_type == MMC_IS_SD) { 261 params.reg_base = STM32MP_SDMMC1_BASE; 262 } else { 263 params.reg_base = STM32MP_SDMMC2_BASE; 264 } 265 break; 266 } 267 268 params.device_info = &mmc_info; 269 if (stm32_sdmmc2_mmc_init(¶ms) != 0) { 270 ERROR("SDMMC%u init failed\n", boot_interface_instance); 271 panic(); 272 } 273 274 /* Open MMC as a block device to read GPT table */ 275 io_result = register_io_dev_block(&mmc_dev_con); 276 if (io_result != 0) { 277 panic(); 278 } 279 280 io_result = io_dev_open(mmc_dev_con, (uintptr_t)&mmc_block_dev_spec, 281 &storage_dev_handle); 282 assert(io_result == 0); 283 } 284 #endif /* STM32MP_SDMMC || STM32MP_EMMC */ 285 286 #if STM32MP_SPI_NOR 287 static void boot_spi_nor(boot_api_context_t *boot_context) 288 { 289 int io_result __unused; 290 291 io_result = stm32_qspi_init(); 292 assert(io_result == 0); 293 294 io_result = register_io_dev_mtd(&spi_dev_con); 295 assert(io_result == 0); 296 297 /* Open connections to device */ 298 io_result = io_dev_open(spi_dev_con, 299 (uintptr_t)&spi_nor_dev_spec, 300 &storage_dev_handle); 301 assert(io_result == 0); 302 } 303 #endif /* STM32MP_SPI_NOR */ 304 305 #if STM32MP_RAW_NAND 306 static void boot_fmc2_nand(boot_api_context_t *boot_context) 307 { 308 int io_result __unused; 309 310 io_result = stm32_fmc2_init(); 311 assert(io_result == 0); 312 313 /* Register the IO device on this platform */ 314 io_result = register_io_dev_mtd(&nand_dev_con); 315 assert(io_result == 0); 316 317 /* Open connections to device */ 318 io_result = io_dev_open(nand_dev_con, (uintptr_t)&nand_dev_spec, 319 &storage_dev_handle); 320 assert(io_result == 0); 321 } 322 #endif /* STM32MP_RAW_NAND */ 323 324 #if STM32MP_SPI_NAND 325 static void boot_spi_nand(boot_api_context_t *boot_context) 326 { 327 int io_result __unused; 328 329 io_result = stm32_qspi_init(); 330 assert(io_result == 0); 331 332 io_result = register_io_dev_mtd(&spi_dev_con); 333 assert(io_result == 0); 334 335 /* Open connections to device */ 336 io_result = io_dev_open(spi_dev_con, 337 (uintptr_t)&spi_nand_dev_spec, 338 &storage_dev_handle); 339 assert(io_result == 0); 340 } 341 #endif /* STM32MP_SPI_NAND */ 342 343 void stm32mp_io_setup(void) 344 { 345 int io_result __unused; 346 boot_api_context_t *boot_context = 347 (boot_api_context_t *)stm32mp_get_boot_ctx_address(); 348 349 print_boot_device(boot_context); 350 351 if ((boot_context->boot_partition_used_toboot == 1U) || 352 (boot_context->boot_partition_used_toboot == 2U)) { 353 INFO("Boot used partition fsbl%u\n", 354 boot_context->boot_partition_used_toboot); 355 } 356 357 io_result = register_io_dev_fip(&fip_dev_con); 358 assert(io_result == 0); 359 360 io_result = io_dev_open(fip_dev_con, (uintptr_t)NULL, 361 &fip_dev_handle); 362 363 switch (boot_context->boot_interface_selected) { 364 #if STM32MP_SDMMC 365 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD: 366 dmbsy(); 367 boot_mmc(MMC_IS_SD, boot_context->boot_interface_instance); 368 break; 369 #endif 370 #if STM32MP_EMMC 371 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC: 372 dmbsy(); 373 boot_mmc(MMC_IS_EMMC, boot_context->boot_interface_instance); 374 break; 375 #endif 376 #if STM32MP_SPI_NOR 377 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI: 378 dmbsy(); 379 boot_spi_nor(boot_context); 380 break; 381 #endif 382 #if STM32MP_RAW_NAND 383 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC: 384 dmbsy(); 385 boot_fmc2_nand(boot_context); 386 break; 387 #endif 388 #if STM32MP_SPI_NAND 389 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_QSPI: 390 dmbsy(); 391 boot_spi_nand(boot_context); 392 break; 393 #endif 394 395 default: 396 ERROR("Boot interface %d not supported\n", 397 boot_context->boot_interface_selected); 398 panic(); 399 break; 400 } 401 } 402 403 int bl2_plat_handle_pre_image_load(unsigned int image_id) 404 { 405 static bool gpt_init_done __unused; 406 uint16_t boot_itf = stm32mp_get_boot_itf_selected(); 407 408 switch (boot_itf) { 409 #if STM32MP_SDMMC || STM32MP_EMMC 410 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD: 411 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC: 412 if (!gpt_init_done) { 413 const partition_entry_t *entry; 414 415 partition_init(GPT_IMAGE_ID); 416 entry = get_partition_entry(FIP_IMAGE_NAME); 417 if (entry == NULL) { 418 ERROR("Could NOT find the %s partition!\n", 419 FIP_IMAGE_NAME); 420 return -ENOENT; 421 } 422 423 image_block_spec.offset = entry->start; 424 image_block_spec.length = entry->length; 425 426 gpt_init_done = true; 427 } else { 428 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 429 430 mmc_block_dev_spec.buffer.offset = bl_mem_params->image_info.image_base; 431 mmc_block_dev_spec.buffer.length = bl_mem_params->image_info.image_max_size; 432 } 433 434 break; 435 #endif 436 437 #if STM32MP_RAW_NAND || STM32MP_SPI_NAND 438 #if STM32MP_RAW_NAND 439 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC: 440 #endif 441 #if STM32MP_SPI_NAND 442 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_QSPI: 443 #endif 444 image_block_spec.offset = STM32MP_NAND_FIP_OFFSET; 445 break; 446 #endif 447 448 #if STM32MP_SPI_NOR 449 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI: 450 image_block_spec.offset = STM32MP_NOR_FIP_OFFSET; 451 break; 452 #endif 453 454 default: 455 ERROR("FIP Not found\n"); 456 panic(); 457 } 458 459 return 0; 460 } 461 462 /* 463 * Return an IO device handle and specification which can be used to access 464 * an image. Use this to enforce platform load policy. 465 */ 466 int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle, 467 uintptr_t *image_spec) 468 { 469 int rc; 470 const struct plat_io_policy *policy; 471 472 assert(image_id < ARRAY_SIZE(policies)); 473 474 policy = &policies[image_id]; 475 rc = policy->check(policy->image_spec); 476 if (rc == 0) { 477 *image_spec = policy->image_spec; 478 *dev_handle = *(policy->dev_handle); 479 } 480 481 return rc; 482 } 483