1 /* 2 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef STM32MP1_DEF_H 8 #define STM32MP1_DEF_H 9 10 #include <common/tbbr/tbbr_img_def.h> 11 #include <drivers/st/stm32mp1_rcc.h> 12 #include <dt-bindings/clock/stm32mp1-clks.h> 13 #include <dt-bindings/reset/stm32mp1-resets.h> 14 #include <lib/utils_def.h> 15 #include <lib/xlat_tables/xlat_tables_defs.h> 16 17 #ifndef __ASSEMBLER__ 18 #include <drivers/st/bsec.h> 19 #include <drivers/st/stm32mp1_clk.h> 20 21 #include <boot_api.h> 22 #include <stm32mp_auth.h> 23 #include <stm32mp_common.h> 24 #include <stm32mp_dt.h> 25 #include <stm32mp_shres_helpers.h> 26 #include <stm32mp1_dbgmcu.h> 27 #include <stm32mp1_private.h> 28 #include <stm32mp1_shared_resources.h> 29 #endif 30 31 #if !STM32MP_USE_STM32IMAGE 32 #include "stm32mp1_fip_def.h" 33 #else /* STM32MP_USE_STM32IMAGE */ 34 #include "stm32mp1_stm32image_def.h" 35 #endif /* STM32MP_USE_STM32IMAGE */ 36 37 /******************************************************************************* 38 * CHIP ID 39 ******************************************************************************/ 40 #define STM32MP1_CHIP_ID U(0x500) 41 42 #define STM32MP157C_PART_NB U(0x05000000) 43 #define STM32MP157A_PART_NB U(0x05000001) 44 #define STM32MP153C_PART_NB U(0x05000024) 45 #define STM32MP153A_PART_NB U(0x05000025) 46 #define STM32MP151C_PART_NB U(0x0500002E) 47 #define STM32MP151A_PART_NB U(0x0500002F) 48 #define STM32MP157F_PART_NB U(0x05000080) 49 #define STM32MP157D_PART_NB U(0x05000081) 50 #define STM32MP153F_PART_NB U(0x050000A4) 51 #define STM32MP153D_PART_NB U(0x050000A5) 52 #define STM32MP151F_PART_NB U(0x050000AE) 53 #define STM32MP151D_PART_NB U(0x050000AF) 54 55 #define STM32MP1_REV_B U(0x2000) 56 #define STM32MP1_REV_Z U(0x2001) 57 58 /******************************************************************************* 59 * PACKAGE ID 60 ******************************************************************************/ 61 #define PKG_AA_LFBGA448 U(4) 62 #define PKG_AB_LFBGA354 U(3) 63 #define PKG_AC_TFBGA361 U(2) 64 #define PKG_AD_TFBGA257 U(1) 65 66 /******************************************************************************* 67 * STM32MP1 memory map related constants 68 ******************************************************************************/ 69 #define STM32MP_ROM_BASE U(0x00000000) 70 #define STM32MP_ROM_SIZE U(0x00020000) 71 72 #define STM32MP_SYSRAM_BASE U(0x2FFC0000) 73 #define STM32MP_SYSRAM_SIZE U(0x00040000) 74 75 #define STM32MP_NS_SYSRAM_SIZE PAGE_SIZE 76 #define STM32MP_NS_SYSRAM_BASE (STM32MP_SYSRAM_BASE + \ 77 STM32MP_SYSRAM_SIZE - \ 78 STM32MP_NS_SYSRAM_SIZE) 79 80 #define STM32MP_SCMI_NS_SHM_BASE STM32MP_NS_SYSRAM_BASE 81 #define STM32MP_SCMI_NS_SHM_SIZE STM32MP_NS_SYSRAM_SIZE 82 83 #define STM32MP_SEC_SYSRAM_BASE STM32MP_SYSRAM_BASE 84 #define STM32MP_SEC_SYSRAM_SIZE (STM32MP_SYSRAM_SIZE - \ 85 STM32MP_NS_SYSRAM_SIZE) 86 87 /* DDR configuration */ 88 #define STM32MP_DDR_BASE U(0xC0000000) 89 #define STM32MP_DDR_MAX_SIZE U(0x40000000) /* Max 1GB */ 90 #ifdef AARCH32_SP_OPTEE 91 #define STM32MP_DDR_S_SIZE U(0x01E00000) /* 30 MB */ 92 #define STM32MP_DDR_SHMEM_SIZE U(0x00200000) /* 2 MB */ 93 #else 94 #define STM32MP_DDR_S_SIZE U(0) 95 #define STM32MP_DDR_SHMEM_SIZE U(0) 96 #endif 97 98 /* DDR power initializations */ 99 #ifndef __ASSEMBLER__ 100 enum ddr_type { 101 STM32MP_DDR3, 102 STM32MP_LPDDR2, 103 STM32MP_LPDDR3 104 }; 105 #endif 106 107 /* Section used inside TF binaries */ 108 #define STM32MP_PARAM_LOAD_SIZE U(0x00002400) /* 9 KB for param */ 109 /* 256 Octets reserved for header */ 110 #define STM32MP_HEADER_SIZE U(0x00000100) 111 112 #define STM32MP_BINARY_BASE (STM32MP_SEC_SYSRAM_BASE + \ 113 STM32MP_PARAM_LOAD_SIZE + \ 114 STM32MP_HEADER_SIZE) 115 116 #define STM32MP_BINARY_SIZE (STM32MP_SEC_SYSRAM_SIZE - \ 117 (STM32MP_PARAM_LOAD_SIZE + \ 118 STM32MP_HEADER_SIZE)) 119 120 /* BL2 and BL32/sp_min require 4 tables */ 121 #define MAX_XLAT_TABLES U(4) /* 16 KB for mapping */ 122 123 /* 124 * MAX_MMAP_REGIONS is usually: 125 * BL stm32mp1_mmap size + mmap regions in *_plat_arch_setup 126 */ 127 #if defined(IMAGE_BL2) 128 #define MAX_MMAP_REGIONS 11 129 #endif 130 131 #define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x100000)) 132 #define STM32MP_BL33_MAX_SIZE U(0x400000) 133 134 /* Define maximum page size for NAND devices */ 135 #define PLATFORM_MTD_MAX_PAGE_SIZE U(0x1000) 136 137 /******************************************************************************* 138 * STM32MP1 device/io map related constants (used for MMU) 139 ******************************************************************************/ 140 #define STM32MP1_DEVICE1_BASE U(0x40000000) 141 #define STM32MP1_DEVICE1_SIZE U(0x40000000) 142 143 #define STM32MP1_DEVICE2_BASE U(0x80000000) 144 #define STM32MP1_DEVICE2_SIZE U(0x40000000) 145 146 /******************************************************************************* 147 * STM32MP1 RCC 148 ******************************************************************************/ 149 #define RCC_BASE U(0x50000000) 150 151 /******************************************************************************* 152 * STM32MP1 PWR 153 ******************************************************************************/ 154 #define PWR_BASE U(0x50001000) 155 156 /******************************************************************************* 157 * STM32MP1 GPIO 158 ******************************************************************************/ 159 #define GPIOA_BASE U(0x50002000) 160 #define GPIOB_BASE U(0x50003000) 161 #define GPIOC_BASE U(0x50004000) 162 #define GPIOD_BASE U(0x50005000) 163 #define GPIOE_BASE U(0x50006000) 164 #define GPIOF_BASE U(0x50007000) 165 #define GPIOG_BASE U(0x50008000) 166 #define GPIOH_BASE U(0x50009000) 167 #define GPIOI_BASE U(0x5000A000) 168 #define GPIOJ_BASE U(0x5000B000) 169 #define GPIOK_BASE U(0x5000C000) 170 #define GPIOZ_BASE U(0x54004000) 171 #define GPIO_BANK_OFFSET U(0x1000) 172 173 /* Bank IDs used in GPIO driver API */ 174 #define GPIO_BANK_A U(0) 175 #define GPIO_BANK_B U(1) 176 #define GPIO_BANK_C U(2) 177 #define GPIO_BANK_D U(3) 178 #define GPIO_BANK_E U(4) 179 #define GPIO_BANK_F U(5) 180 #define GPIO_BANK_G U(6) 181 #define GPIO_BANK_H U(7) 182 #define GPIO_BANK_I U(8) 183 #define GPIO_BANK_J U(9) 184 #define GPIO_BANK_K U(10) 185 #define GPIO_BANK_Z U(25) 186 187 #define STM32MP_GPIOZ_PIN_MAX_COUNT 8 188 189 /******************************************************************************* 190 * STM32MP1 UART 191 ******************************************************************************/ 192 #define USART1_BASE U(0x5C000000) 193 #define USART2_BASE U(0x4000E000) 194 #define USART3_BASE U(0x4000F000) 195 #define UART4_BASE U(0x40010000) 196 #define UART5_BASE U(0x40011000) 197 #define USART6_BASE U(0x44003000) 198 #define UART7_BASE U(0x40018000) 199 #define UART8_BASE U(0x40019000) 200 #define STM32MP_UART_BAUDRATE U(115200) 201 202 /* For UART crash console */ 203 #define STM32MP_DEBUG_USART_BASE UART4_BASE 204 /* UART4 on HSI@64MHz, TX on GPIOG11 Alternate 6 */ 205 #define STM32MP_DEBUG_USART_CLK_FRQ 64000000 206 #define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOG_BASE 207 #define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_MP_AHB4ENSETR 208 #define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_MP_AHB4ENSETR_GPIOGEN 209 #define DEBUG_UART_TX_GPIO_PORT 11 210 #define DEBUG_UART_TX_GPIO_ALTERNATE 6 211 #define DEBUG_UART_TX_CLKSRC_REG RCC_UART24CKSELR 212 #define DEBUG_UART_TX_CLKSRC RCC_UART24CKSELR_HSI 213 #define DEBUG_UART_TX_EN_REG RCC_MP_APB1ENSETR 214 #define DEBUG_UART_TX_EN RCC_MP_APB1ENSETR_UART4EN 215 216 /******************************************************************************* 217 * STM32MP1 ETZPC 218 ******************************************************************************/ 219 #define STM32MP1_ETZPC_BASE U(0x5C007000) 220 221 /* ETZPC TZMA IDs */ 222 #define STM32MP1_ETZPC_TZMA_ROM U(0) 223 #define STM32MP1_ETZPC_TZMA_SYSRAM U(1) 224 225 #define STM32MP1_ETZPC_TZMA_ALL_SECURE GENMASK_32(9, 0) 226 227 /* ETZPC DECPROT IDs */ 228 #define STM32MP1_ETZPC_STGENC_ID 0 229 #define STM32MP1_ETZPC_BKPSRAM_ID 1 230 #define STM32MP1_ETZPC_IWDG1_ID 2 231 #define STM32MP1_ETZPC_USART1_ID 3 232 #define STM32MP1_ETZPC_SPI6_ID 4 233 #define STM32MP1_ETZPC_I2C4_ID 5 234 #define STM32MP1_ETZPC_RNG1_ID 7 235 #define STM32MP1_ETZPC_HASH1_ID 8 236 #define STM32MP1_ETZPC_CRYP1_ID 9 237 #define STM32MP1_ETZPC_DDRCTRL_ID 10 238 #define STM32MP1_ETZPC_DDRPHYC_ID 11 239 #define STM32MP1_ETZPC_I2C6_ID 12 240 #define STM32MP1_ETZPC_SEC_ID_LIMIT 13 241 242 #define STM32MP1_ETZPC_TIM2_ID 16 243 #define STM32MP1_ETZPC_TIM3_ID 17 244 #define STM32MP1_ETZPC_TIM4_ID 18 245 #define STM32MP1_ETZPC_TIM5_ID 19 246 #define STM32MP1_ETZPC_TIM6_ID 20 247 #define STM32MP1_ETZPC_TIM7_ID 21 248 #define STM32MP1_ETZPC_TIM12_ID 22 249 #define STM32MP1_ETZPC_TIM13_ID 23 250 #define STM32MP1_ETZPC_TIM14_ID 24 251 #define STM32MP1_ETZPC_LPTIM1_ID 25 252 #define STM32MP1_ETZPC_WWDG1_ID 26 253 #define STM32MP1_ETZPC_SPI2_ID 27 254 #define STM32MP1_ETZPC_SPI3_ID 28 255 #define STM32MP1_ETZPC_SPDIFRX_ID 29 256 #define STM32MP1_ETZPC_USART2_ID 30 257 #define STM32MP1_ETZPC_USART3_ID 31 258 #define STM32MP1_ETZPC_UART4_ID 32 259 #define STM32MP1_ETZPC_UART5_ID 33 260 #define STM32MP1_ETZPC_I2C1_ID 34 261 #define STM32MP1_ETZPC_I2C2_ID 35 262 #define STM32MP1_ETZPC_I2C3_ID 36 263 #define STM32MP1_ETZPC_I2C5_ID 37 264 #define STM32MP1_ETZPC_CEC_ID 38 265 #define STM32MP1_ETZPC_DAC_ID 39 266 #define STM32MP1_ETZPC_UART7_ID 40 267 #define STM32MP1_ETZPC_UART8_ID 41 268 #define STM32MP1_ETZPC_MDIOS_ID 44 269 #define STM32MP1_ETZPC_TIM1_ID 48 270 #define STM32MP1_ETZPC_TIM8_ID 49 271 #define STM32MP1_ETZPC_USART6_ID 51 272 #define STM32MP1_ETZPC_SPI1_ID 52 273 #define STM32MP1_ETZPC_SPI4_ID 53 274 #define STM32MP1_ETZPC_TIM15_ID 54 275 #define STM32MP1_ETZPC_TIM16_ID 55 276 #define STM32MP1_ETZPC_TIM17_ID 56 277 #define STM32MP1_ETZPC_SPI5_ID 57 278 #define STM32MP1_ETZPC_SAI1_ID 58 279 #define STM32MP1_ETZPC_SAI2_ID 59 280 #define STM32MP1_ETZPC_SAI3_ID 60 281 #define STM32MP1_ETZPC_DFSDM_ID 61 282 #define STM32MP1_ETZPC_TT_FDCAN_ID 62 283 #define STM32MP1_ETZPC_LPTIM2_ID 64 284 #define STM32MP1_ETZPC_LPTIM3_ID 65 285 #define STM32MP1_ETZPC_LPTIM4_ID 66 286 #define STM32MP1_ETZPC_LPTIM5_ID 67 287 #define STM32MP1_ETZPC_SAI4_ID 68 288 #define STM32MP1_ETZPC_VREFBUF_ID 69 289 #define STM32MP1_ETZPC_DCMI_ID 70 290 #define STM32MP1_ETZPC_CRC2_ID 71 291 #define STM32MP1_ETZPC_ADC_ID 72 292 #define STM32MP1_ETZPC_HASH2_ID 73 293 #define STM32MP1_ETZPC_RNG2_ID 74 294 #define STM32MP1_ETZPC_CRYP2_ID 75 295 #define STM32MP1_ETZPC_SRAM1_ID 80 296 #define STM32MP1_ETZPC_SRAM2_ID 81 297 #define STM32MP1_ETZPC_SRAM3_ID 82 298 #define STM32MP1_ETZPC_SRAM4_ID 83 299 #define STM32MP1_ETZPC_RETRAM_ID 84 300 #define STM32MP1_ETZPC_OTG_ID 85 301 #define STM32MP1_ETZPC_SDMMC3_ID 86 302 #define STM32MP1_ETZPC_DLYBSD3_ID 87 303 #define STM32MP1_ETZPC_DMA1_ID 88 304 #define STM32MP1_ETZPC_DMA2_ID 89 305 #define STM32MP1_ETZPC_DMAMUX_ID 90 306 #define STM32MP1_ETZPC_FMC_ID 91 307 #define STM32MP1_ETZPC_QSPI_ID 92 308 #define STM32MP1_ETZPC_DLYBQ_ID 93 309 #define STM32MP1_ETZPC_ETH_ID 94 310 #define STM32MP1_ETZPC_RSV_ID 95 311 312 #define STM32MP_ETZPC_MAX_ID 96 313 314 /******************************************************************************* 315 * STM32MP1 TZC (TZ400) 316 ******************************************************************************/ 317 #define STM32MP1_TZC_BASE U(0x5C006000) 318 319 #define STM32MP1_TZC_A7_ID U(0) 320 #define STM32MP1_TZC_M4_ID U(1) 321 #define STM32MP1_TZC_LCD_ID U(3) 322 #define STM32MP1_TZC_GPU_ID U(4) 323 #define STM32MP1_TZC_MDMA_ID U(5) 324 #define STM32MP1_TZC_DMA_ID U(6) 325 #define STM32MP1_TZC_USB_HOST_ID U(7) 326 #define STM32MP1_TZC_USB_OTG_ID U(8) 327 #define STM32MP1_TZC_SDMMC_ID U(9) 328 #define STM32MP1_TZC_ETH_ID U(10) 329 #define STM32MP1_TZC_DAP_ID U(15) 330 331 #define STM32MP1_FILTER_BIT_ALL (TZC_400_REGION_ATTR_FILTER_BIT(0) | \ 332 TZC_400_REGION_ATTR_FILTER_BIT(1)) 333 334 /******************************************************************************* 335 * STM32MP1 SDMMC 336 ******************************************************************************/ 337 #define STM32MP_SDMMC1_BASE U(0x58005000) 338 #define STM32MP_SDMMC2_BASE U(0x58007000) 339 #define STM32MP_SDMMC3_BASE U(0x48004000) 340 341 #define STM32MP_MMC_INIT_FREQ U(400000) /*400 KHz*/ 342 #define STM32MP_SD_NORMAL_SPEED_MAX_FREQ U(25000000) /*25 MHz*/ 343 #define STM32MP_SD_HIGH_SPEED_MAX_FREQ U(50000000) /*50 MHz*/ 344 #define STM32MP_EMMC_NORMAL_SPEED_MAX_FREQ U(26000000) /*26 MHz*/ 345 #define STM32MP_EMMC_HIGH_SPEED_MAX_FREQ U(52000000) /*52 MHz*/ 346 347 /******************************************************************************* 348 * STM32MP1 BSEC / OTP 349 ******************************************************************************/ 350 #define STM32MP1_OTP_MAX_ID 0x5FU 351 #define STM32MP1_UPPER_OTP_START 0x20U 352 353 #define OTP_MAX_SIZE (STM32MP1_OTP_MAX_ID + 1U) 354 355 /* OTP offsets */ 356 #define DATA0_OTP U(0) 357 #define PART_NUMBER_OTP U(1) 358 #define NAND_OTP U(9) 359 #define PACKAGE_OTP U(16) 360 #define HW2_OTP U(18) 361 362 /* OTP mask */ 363 /* DATA0 */ 364 #define DATA0_OTP_SECURED BIT(6) 365 366 /* PART NUMBER */ 367 #define PART_NUMBER_OTP_PART_MASK GENMASK_32(7, 0) 368 #define PART_NUMBER_OTP_PART_SHIFT 0 369 370 /* PACKAGE */ 371 #define PACKAGE_OTP_PKG_MASK GENMASK_32(29, 27) 372 #define PACKAGE_OTP_PKG_SHIFT 27 373 374 /* IWDG OTP */ 375 #define HW2_OTP_IWDG_HW_POS U(3) 376 #define HW2_OTP_IWDG_FZ_STOP_POS U(5) 377 #define HW2_OTP_IWDG_FZ_STANDBY_POS U(7) 378 379 /* HW2 OTP */ 380 #define HW2_OTP_PRODUCT_BELOW_2V5 BIT(13) 381 382 /* NAND OTP */ 383 /* NAND parameter storage flag */ 384 #define NAND_PARAM_STORED_IN_OTP BIT(31) 385 386 /* NAND page size in bytes */ 387 #define NAND_PAGE_SIZE_MASK GENMASK_32(30, 29) 388 #define NAND_PAGE_SIZE_SHIFT 29 389 #define NAND_PAGE_SIZE_2K U(0) 390 #define NAND_PAGE_SIZE_4K U(1) 391 #define NAND_PAGE_SIZE_8K U(2) 392 393 /* NAND block size in pages */ 394 #define NAND_BLOCK_SIZE_MASK GENMASK_32(28, 27) 395 #define NAND_BLOCK_SIZE_SHIFT 27 396 #define NAND_BLOCK_SIZE_64_PAGES U(0) 397 #define NAND_BLOCK_SIZE_128_PAGES U(1) 398 #define NAND_BLOCK_SIZE_256_PAGES U(2) 399 400 /* NAND number of block (in unit of 256 blocs) */ 401 #define NAND_BLOCK_NB_MASK GENMASK_32(26, 19) 402 #define NAND_BLOCK_NB_SHIFT 19 403 #define NAND_BLOCK_NB_UNIT U(256) 404 405 /* NAND bus width in bits */ 406 #define NAND_WIDTH_MASK BIT(18) 407 #define NAND_WIDTH_SHIFT 18 408 409 /* NAND number of ECC bits per 512 bytes */ 410 #define NAND_ECC_BIT_NB_MASK GENMASK_32(17, 15) 411 #define NAND_ECC_BIT_NB_SHIFT 15 412 #define NAND_ECC_BIT_NB_UNSET U(0) 413 #define NAND_ECC_BIT_NB_1_BITS U(1) 414 #define NAND_ECC_BIT_NB_4_BITS U(2) 415 #define NAND_ECC_BIT_NB_8_BITS U(3) 416 #define NAND_ECC_ON_DIE U(4) 417 418 /* NAND number of planes */ 419 #define NAND_PLANE_BIT_NB_MASK BIT(14) 420 421 /******************************************************************************* 422 * STM32MP1 TAMP 423 ******************************************************************************/ 424 #define TAMP_BASE U(0x5C00A000) 425 #define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100)) 426 427 #if !(defined(__LINKER__) || defined(__ASSEMBLER__)) 428 static inline uint32_t tamp_bkpr(uint32_t idx) 429 { 430 return TAMP_BKP_REGISTER_BASE + (idx << 2); 431 } 432 #endif 433 434 /******************************************************************************* 435 * STM32MP1 DDRCTRL 436 ******************************************************************************/ 437 #define DDRCTRL_BASE U(0x5A003000) 438 439 /******************************************************************************* 440 * STM32MP1 DDRPHYC 441 ******************************************************************************/ 442 #define DDRPHYC_BASE U(0x5A004000) 443 444 /******************************************************************************* 445 * STM32MP1 IWDG 446 ******************************************************************************/ 447 #define IWDG_MAX_INSTANCE U(2) 448 #define IWDG1_INST U(0) 449 #define IWDG2_INST U(1) 450 451 #define IWDG1_BASE U(0x5C003000) 452 #define IWDG2_BASE U(0x5A002000) 453 454 /******************************************************************************* 455 * Miscellaneous STM32MP1 peripherals base address 456 ******************************************************************************/ 457 #define BSEC_BASE U(0x5C005000) 458 #define CRYP1_BASE U(0x54001000) 459 #define DBGMCU_BASE U(0x50081000) 460 #define HASH1_BASE U(0x54002000) 461 #define I2C4_BASE U(0x5C002000) 462 #define I2C6_BASE U(0x5c009000) 463 #define RNG1_BASE U(0x54003000) 464 #define RTC_BASE U(0x5c004000) 465 #define SPI6_BASE U(0x5c001000) 466 #define STGEN_BASE U(0x5c008000) 467 #define SYSCFG_BASE U(0x50020000) 468 469 /******************************************************************************* 470 * Device Tree defines 471 ******************************************************************************/ 472 #define DT_BSEC_COMPAT "st,stm32mp15-bsec" 473 #define DT_IWDG_COMPAT "st,stm32mp1-iwdg" 474 #define DT_PWR_COMPAT "st,stm32mp1,pwr-reg" 475 #define DT_RCC_CLK_COMPAT "st,stm32mp1-rcc" 476 477 #endif /* STM32MP1_DEF_H */ 478