fix(imx8m): correct the rank info get fro mstr

the bitfield of active_ranks in MSTR is defined as below.
Correct the rank num get in dram_info.

0x01: one rank;
0x11: two rank;

Signed-off-by: J

fix(imx8m): correct the rank info get fro mstr

the bitfield of active_ranks in MSTR is defined as below.
Correct the rank num get in dram_info.

0x01: one rank;
0x11: two rank;

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
Change-Id: Idcadb39f492a8fe81c973ac4136d9a1eaa32f54b

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feat(imx8m): fix the ddr4 dvfs random hang on imx8m

Remove the while loop waiting in step12 to align with what
we did before, just use a 'if' condition check for debug
purpose.

Tested-by: Peng Fan

feat(imx8m): fix the ddr4 dvfs random hang on imx8m

Remove the while loop waiting in step12 to align with what
we did before, just use a 'if' condition check for debug
purpose.

Tested-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Id2685c5f628270a24944470d675a5c8706f39f13

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fix(rme): update sample platform attestation token

Update FVP platform attestation token to comply with RMM Beta0
specification. The changes are:
- change platform implementation id claim value from

fix(rme): update sample platform attestation token

Update FVP platform attestation token to comply with RMM Beta0
specification. The changes are:
- change platform implementation id claim value from 64 to 32 bits
- change Realm Challenge
- update Hash Algorithm Identifier claim value
- add protected header
- change signing algotithm to ECDSA ES384

Change-Id: I1c5907d1a4961ce08a1408d25128de125b3f2e7f
Signed-off-by: Mate Toth-Pal <mate.toth-pal@arm.com>

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feat(zynqmp): add hooks for mmap and early setup

Add early setup hooks (via custom_early_setup()) and provide a way
to cover custom memory mapping which includes extending memory map
via custom_mmap

feat(zynqmp): add hooks for mmap and early setup

Add early setup hooks (via custom_early_setup()) and provide a way
to cover custom memory mapping which includes extending memory map
via custom_mmap_add().

This likely also require to align MAX_XLAT_TABLE, MAX_XLAT_TABLES
macros. It can be done for example by defining these macros in
custom_pkg.mk
MAX_MMAP_REGIONS := XY
$(eval $(call add_define,MAX_MMAP_REGIONS))
MAX_XLAT_TABLES := XZ
$(eval $(call add_define,MAX_XLAT_TABLES))

custom_early_setup() can be used for early low level operations
related to setting up the system to correct state.

Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Change-Id: I61df6f9ba5af0bc97c430974fb10a2edde44f23d

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Merge changes from topic "panic_cleanup" into integration

* changes:
refactor(bl31): use elx_panic for sysreg_handler64
refactor(aarch64): rename do_panic and el3_panic
refactor(aarch64): remo

Merge changes from topic "panic_cleanup" into integration

* changes:
refactor(bl31): use elx_panic for sysreg_handler64
refactor(aarch64): rename do_panic and el3_panic
refactor(aarch64): remove weak links to el3_panic
refactor(aarch64): refactor usage of elx_panic
refactor(aarch64): cleanup HANDLE_EA_EL3_FIRST_NS usage

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Merge "fix: remove useless "return" at void functions" into integration

fix(zynqmp): add bitmask for get_op_char API

As per the current functionality, there are a couple of types like
PM_OPCHAR_TYPE_TEMP, PM_OPCHAR_TYPE_POWER and PM_OPCHAR_TYPE_LATENCY
for the PM_GET_OP

fix(zynqmp): add bitmask for get_op_char API

As per the current functionality, there are a couple of types like
PM_OPCHAR_TYPE_TEMP, PM_OPCHAR_TYPE_POWER and PM_OPCHAR_TYPE_LATENCY
for the PM_GET_OP_CHARACTERISTIC EEMI API which is mismatched across
the Versal and ZynqMP platforms.

So added the bitmask functionality for PM_GET_OP_CHARACTERISTIC API
in feature check in the firmware and as part of that the firmware fill
up payload[1] with the bitmask value of supported types of the
PM_GET_OP_CHARACTERISTIC EEMI API but from TF-A based on the current
codebase it is just returning the version. So filling up the bitmask
buffer which is received from the firmware and returned the same to
the user.

Signed-off-by: Ronak Jain <ronak.jain@amd.com>
Change-Id: I2c55f3e902a5f89eed899e99a97ad9b3f0a12796

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Merge changes I51c13c52,I3358c51e into integration

* changes:
build: always prefix section names with `.`
build: communicate correct page size to linker

Merge "fix(zynqmp): panic w/o handoff structure in !JTAG" into integration

refactor(aarch64): rename do_panic and el3_panic

Current panic call invokes do_panic which calls el3_panic, but now panic
handles only panic from EL3 anid clear separation to use lower_el_panic()
wh

refactor(aarch64): rename do_panic and el3_panic

Current panic call invokes do_panic which calls el3_panic, but now panic
handles only panic from EL3 anid clear separation to use lower_el_panic()
which handles panic from lower ELs.

So now we can remove do_panic and just call el3_panic for all panics.

Change-Id: I739c69271b9fb15c1176050877a9b0c0394dc739
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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refactor(aarch64): refactor usage of elx_panic

Currently we call el3_panic for panics from EL3 and elx_panic for
panics from lower ELs.

When we boot into a rich OS environment and interact with BL3

refactor(aarch64): refactor usage of elx_panic

Currently we call el3_panic for panics from EL3 and elx_panic for
panics from lower ELs.

When we boot into a rich OS environment and interact with BL31 using
SMC/ABI calls and we can also decide to handle any lower EL panics in
EL3. Panic can occur in lower EL from rich OS or during SMC/ABI calls
after context switch to EL3.

But after booting into any rich OS we may land in panic either from
rich OS or while servicing any SMC call, here the logic to use
el3_panic or elx_panic is flawed as spsr_el3[3:0] is always EL3h
and end up in elx_panic even if panic occurred from EL3 during
SMC handling.

We try to decouple the elx_panic usage for its intended purpose,
introduce lower_el_panic which would call elx_panic, currently
lower_el_panic is called from default platform_ea_handle which
would be called due to panic from any of the lower ELs.

Also remove the weak linkage for elx_panic and rename it to
report_elx_panic which could be used with lower_el_panic.

Change-Id: I268bca89c01c60520d127ef6c7ba851460edc747
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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refactor(aarch64): cleanup HANDLE_EA_EL3_FIRST_NS usage

Remove usage of HANDLE_EA_EL3_FIRST_NS in plat_default_ea_handler

Change-Id: I2bf4788960d20a090d66cf39c7bbbdea1d3243ca
Signed-off-by: Govindr

refactor(aarch64): cleanup HANDLE_EA_EL3_FIRST_NS usage

Remove usage of HANDLE_EA_EL3_FIRST_NS in plat_default_ea_handler

Change-Id: I2bf4788960d20a090d66cf39c7bbbdea1d3243ca
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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refactor(fvp): minor cleanup with TRUSTED_BOARD_BOOT

CRYPTO_SUPPORT is enabled by default when TRUSTED_BOARD_BOOT is
enabled so usage CRYPTO_SUPPORT in conjunction with TRUSTED_BOARD_BOOT
might some

refactor(fvp): minor cleanup with TRUSTED_BOARD_BOOT

CRYPTO_SUPPORT is enabled by default when TRUSTED_BOARD_BOOT is
enabled so usage CRYPTO_SUPPORT in conjunction with TRUSTED_BOARD_BOOT
might sometime be confusing to look at.

Adding minor cleanup to make it look simpler with conditions.
No functionality changes.

Change-Id: I800524d54ea56dc27b6c6da26c75a07f5f6de984
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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feat(fvp): increase BL1_RW and BL2 size

To support mbedtls3.3 increase BL1_RW and BL2 size rsa+ecdsa alg.

Increase both by one page size. In mbedtls3.3 numerous config options
have been tweaked and

feat(fvp): increase BL1_RW and BL2 size

To support mbedtls3.3 increase BL1_RW and BL2 size rsa+ecdsa alg.

Increase both by one page size. In mbedtls3.3 numerous config options
have been tweaked and made defaults[1] thus a small increase in size
can result for mbedtls-3.3

This size limitation is observed when we build TF-A with
TF_MBEDTLS_KEY_ALG=rsa+ecdsa this approach is used in juno as well,
so use similar approach for FVP.

[1]: https://github.com/Mbed-TLS/mbedtls/blob/development/docs/3.0-migration-guide.md

Change-Id: I8a423711ac50b3d615c1d9650086cdbca5051c8e
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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refactor(mbedtls): avoid including MBEDTLS_CONFIG_FILE

Currently we include MBEDTLS_CONFIG_FILE directly and if a custom
config file is used it will included.

However from mbedtls-3.x onwards it di

refactor(mbedtls): avoid including MBEDTLS_CONFIG_FILE

Currently we include MBEDTLS_CONFIG_FILE directly and if a custom
config file is used it will included.

However from mbedtls-3.x onwards it discourages usage of
MBEDTLS_CONFIG_FILE include directly, so to resolve this and keep 2.28
compatibility include version.h which would include the custom config
file if present and also would expose us with mbedtls-major-version
number which could be used for selecting features and functions for
mbedtls 2.28 or 3.3

Change-Id: I029992311be2a38b588ebbb350875b03ea29acdb
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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fix(zynqmp): panic w/o handoff structure in !JTAG

In case that FSBL (or SPL) doesn't provide valid handoff structure don't
fallback to default image location. In non JTAG boot mode all the time
stru

fix(zynqmp): panic w/o handoff structure in !JTAG

In case that FSBL (or SPL) doesn't provide valid handoff structure don't
fallback to default image location. In non JTAG boot mode all the time
structure should be passed. If it is not it can be opportunity to inject
any code to default locations and start it. That's why panic in all
these cases.

Change-Id: Ib3e11e2ae9ffec7406002cce4997b12b97bdc396
Signed-off-by: Michal Simek <michal.simek@amd.com>

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build: always prefix section names with `.`

Some of our specialized sections are not prefixed with the conventional
period. The compiler uses input section names to derive certain other
section name

build: always prefix section names with `.`

Some of our specialized sections are not prefixed with the conventional
period. The compiler uses input section names to derive certain other
section names (e.g. `.rela.text`, `.relacpu_ops`), and these can be
difficult to select in linker scripts when there is a lack of a
delimiter.

This change introduces the period prefix to all specialized section
names.

BREAKING-CHANGE: All input and output linker section names have been
prefixed with the period character, e.g. `cpu_ops` -> `.cpu_ops`.

Change-Id: I51c13c5266d5975fbd944ef4961328e72f82fc1c
Signed-off-by: Chris Kay <chris.kay@arm.com>

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fix(zynqmp): move EM SMC range to SIP range

EM SMC where out of SIP range which is 15:0 bits only. EM was used 19:17
bits which is wrong but no code was checking it. That's why vove EM SMC
to SIP ra

fix(zynqmp): move EM SMC range to SIP range

EM SMC where out of SIP range which is 15:0 bits only. EM was used 19:17
bits which is wrong but no code was checking it. That's why vove EM SMC
to SIP range.

Change-Id: I83f998a17a8b82b2c25ea8c9b247e42642c82178
Signed-off-by: Michal Simek <michal.simek@amd.com>

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Merge changes from topic "zynqmp-smc" into integration

* changes:
fix(zynqmp): check smc_fid 23:16 bits
fix(zynqmp): separate EM from PM SMCs

Merge "feat(zynqmp): add support for custom sip service" into integration

Merge "fix(versal): check smc_fid 23:16 bits" into integration

Merge "docs(xilinx): correct function description" into integration

Merge "fix(zynqmp): update the conflicting EEMI API IDs" into integration

Merge changes from topic "xlnx_zynqmp_debug" into integration

* changes:
fix(zynqmp): with DEBUG=1 move bl31 to DDR range
fix(zynqmp): update MAX_XLAT_TABLES for DDR memory range

Merge changes from topic "versal-ipi" into integration

* changes:
fix(versal): fix incorrect regbase for PMC IPI
fix(versal): sync location based on IPI_ID macros
fix(xilinx): remove unused ma

Merge changes from topic "versal-ipi" into integration

* changes:
fix(versal): fix incorrect regbase for PMC IPI
fix(versal): sync location based on IPI_ID macros
fix(xilinx): remove unused mailbox macros

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