1 /* 2 * Copyright (c) 2019-2023, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef ARCH_FEATURES_H 8 #define ARCH_FEATURES_H 9 10 #include <stdbool.h> 11 12 #include <arch_helpers.h> 13 #include <common/feat_detect.h> 14 15 #define ISOLATE_FIELD(reg, feat) \ 16 ((unsigned int)(((reg) >> (feat ## _SHIFT)) & (feat ## _MASK))) 17 18 static inline bool is_armv7_gentimer_present(void) 19 { 20 /* The Generic Timer is always present in an ARMv8-A implementation */ 21 return true; 22 } 23 24 static inline unsigned int read_feat_pan_id_field(void) 25 { 26 return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_PAN); 27 } 28 29 static inline bool is_feat_pan_supported(void) 30 { 31 if (ENABLE_FEAT_PAN == FEAT_STATE_DISABLED) { 32 return false; 33 } 34 35 if (ENABLE_FEAT_PAN == FEAT_STATE_ALWAYS) { 36 return true; 37 } 38 39 return read_feat_pan_id_field() != 0U; 40 } 41 42 static inline unsigned int read_feat_vhe_id_field(void) 43 { 44 return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_VHE); 45 } 46 47 static inline bool is_feat_vhe_supported(void) 48 { 49 if (ENABLE_FEAT_VHE == FEAT_STATE_DISABLED) { 50 return false; 51 } 52 53 if (ENABLE_FEAT_VHE == FEAT_STATE_ALWAYS) { 54 return true; 55 } 56 57 return read_feat_vhe_id_field() != 0U; 58 } 59 60 static inline bool is_armv8_2_ttcnp_present(void) 61 { 62 return ((read_id_aa64mmfr2_el1() >> ID_AA64MMFR2_EL1_CNP_SHIFT) & 63 ID_AA64MMFR2_EL1_CNP_MASK) != 0U; 64 } 65 66 static inline bool is_feat_pacqarma3_present(void) 67 { 68 uint64_t mask_id_aa64isar2 = 69 (ID_AA64ISAR2_GPA3_MASK << ID_AA64ISAR2_GPA3_SHIFT) | 70 (ID_AA64ISAR2_APA3_MASK << ID_AA64ISAR2_APA3_SHIFT); 71 72 /* If any of the fields is not zero, QARMA3 algorithm is present */ 73 return (read_id_aa64isar2_el1() & mask_id_aa64isar2) != 0U; 74 } 75 76 static inline bool is_armv8_3_pauth_present(void) 77 { 78 uint64_t mask_id_aa64isar1 = 79 (ID_AA64ISAR1_GPI_MASK << ID_AA64ISAR1_GPI_SHIFT) | 80 (ID_AA64ISAR1_GPA_MASK << ID_AA64ISAR1_GPA_SHIFT) | 81 (ID_AA64ISAR1_API_MASK << ID_AA64ISAR1_API_SHIFT) | 82 (ID_AA64ISAR1_APA_MASK << ID_AA64ISAR1_APA_SHIFT); 83 84 /* 85 * If any of the fields is not zero or QARMA3 is present, 86 * PAuth is present 87 */ 88 return ((read_id_aa64isar1_el1() & mask_id_aa64isar1) != 0U || 89 is_feat_pacqarma3_present()); 90 } 91 92 static inline bool is_armv8_4_dit_present(void) 93 { 94 return ((read_id_aa64pfr0_el1() >> ID_AA64PFR0_DIT_SHIFT) & 95 ID_AA64PFR0_DIT_MASK) == 1U; 96 } 97 98 static inline bool is_armv8_4_ttst_present(void) 99 { 100 return ((read_id_aa64mmfr2_el1() >> ID_AA64MMFR2_EL1_ST_SHIFT) & 101 ID_AA64MMFR2_EL1_ST_MASK) == 1U; 102 } 103 104 static inline bool is_armv8_5_bti_present(void) 105 { 106 return ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_BT_SHIFT) & 107 ID_AA64PFR1_EL1_BT_MASK) == BTI_IMPLEMENTED; 108 } 109 110 static inline unsigned int get_armv8_5_mte_support(void) 111 { 112 return ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_MTE_SHIFT) & 113 ID_AA64PFR1_EL1_MTE_MASK); 114 } 115 116 static inline bool is_armv8_4_sel2_present(void) 117 { 118 return ((read_id_aa64pfr0_el1() >> ID_AA64PFR0_SEL2_SHIFT) & 119 ID_AA64PFR0_SEL2_MASK) == 1ULL; 120 } 121 122 static inline bool is_armv8_6_twed_present(void) 123 { 124 return (((read_id_aa64mmfr1_el1() >> ID_AA64MMFR1_EL1_TWED_SHIFT) & 125 ID_AA64MMFR1_EL1_TWED_MASK) == ID_AA64MMFR1_EL1_TWED_SUPPORTED); 126 } 127 128 static unsigned int read_feat_fgt_id_field(void) 129 { 130 return ISOLATE_FIELD(read_id_aa64mmfr0_el1(), ID_AA64MMFR0_EL1_FGT); 131 } 132 133 static inline bool is_feat_fgt_supported(void) 134 { 135 if (ENABLE_FEAT_FGT == FEAT_STATE_DISABLED) { 136 return false; 137 } 138 139 if (ENABLE_FEAT_FGT == FEAT_STATE_ALWAYS) { 140 return true; 141 } 142 143 return read_feat_fgt_id_field() != 0U; 144 } 145 146 static unsigned int read_feat_ecv_id_field(void) 147 { 148 return ISOLATE_FIELD(read_id_aa64mmfr0_el1(), ID_AA64MMFR0_EL1_ECV); 149 } 150 151 static inline bool is_feat_ecv_supported(void) 152 { 153 if (ENABLE_FEAT_ECV == FEAT_STATE_DISABLED) { 154 return false; 155 } 156 157 if (ENABLE_FEAT_ECV == FEAT_STATE_ALWAYS) { 158 return true; 159 } 160 161 return read_feat_ecv_id_field() != 0U; 162 } 163 164 static inline bool is_feat_ecv_v2_supported(void) 165 { 166 if (ENABLE_FEAT_ECV == FEAT_STATE_DISABLED) { 167 return false; 168 } 169 170 if (ENABLE_FEAT_ECV == FEAT_STATE_ALWAYS) { 171 return true; 172 } 173 174 return read_feat_ecv_id_field() >= ID_AA64MMFR0_EL1_ECV_SELF_SYNCH; 175 } 176 177 static inline bool is_armv8_5_rng_present(void) 178 { 179 return ((read_id_aa64isar0_el1() >> ID_AA64ISAR0_RNDR_SHIFT) & 180 ID_AA64ISAR0_RNDR_MASK); 181 } 182 183 static unsigned int read_feat_tcrx_id_field(void) 184 { 185 return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_TCRX); 186 } 187 188 static inline bool is_feat_tcr2_supported(void) 189 { 190 if (ENABLE_FEAT_TCR2 == FEAT_STATE_DISABLED) { 191 return false; 192 } 193 194 if (ENABLE_FEAT_TCR2 == FEAT_STATE_ALWAYS) { 195 return true; 196 } 197 198 return read_feat_tcrx_id_field() != 0U; 199 } 200 201 /******************************************************************************* 202 * Functions to identify the presence of the Activity Monitors Extension 203 ******************************************************************************/ 204 static unsigned int read_feat_amu_id_field(void) 205 { 206 return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_AMU); 207 } 208 209 static inline bool is_feat_amu_supported(void) 210 { 211 if (ENABLE_FEAT_AMUv1 == FEAT_STATE_DISABLED) { 212 return false; 213 } 214 215 if (ENABLE_FEAT_AMUv1 == FEAT_STATE_ALWAYS) { 216 return true; 217 } 218 219 return read_feat_amu_id_field() >= ID_AA64PFR0_AMU_V1; 220 } 221 222 static inline bool is_armv8_6_feat_amuv1p1_present(void) 223 { 224 return read_feat_amu_id_field() >= ID_AA64PFR0_AMU_V1P1; 225 } 226 227 /* 228 * Return MPAM version: 229 * 230 * 0x00: None Armv8.0 or later 231 * 0x01: v0.1 Armv8.4 or later 232 * 0x10: v1.0 Armv8.2 or later 233 * 0x11: v1.1 Armv8.4 or later 234 * 235 */ 236 static inline unsigned int read_feat_mpam_version(void) 237 { 238 return (unsigned int)((((read_id_aa64pfr0_el1() >> 239 ID_AA64PFR0_MPAM_SHIFT) & ID_AA64PFR0_MPAM_MASK) << 4) | 240 ((read_id_aa64pfr1_el1() >> 241 ID_AA64PFR1_MPAM_FRAC_SHIFT) & ID_AA64PFR1_MPAM_FRAC_MASK)); 242 } 243 244 static inline bool is_feat_mpam_supported(void) 245 { 246 if (ENABLE_MPAM_FOR_LOWER_ELS == FEAT_STATE_DISABLED) { 247 return false; 248 } 249 250 if (ENABLE_MPAM_FOR_LOWER_ELS == FEAT_STATE_ALWAYS) { 251 return true; 252 } 253 254 return read_feat_mpam_version() != 0U; 255 } 256 257 static inline unsigned int read_feat_hcx_id_field(void) 258 { 259 return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_HCX); 260 } 261 262 static inline bool is_feat_hcx_supported(void) 263 { 264 if (ENABLE_FEAT_HCX == FEAT_STATE_DISABLED) { 265 return false; 266 } 267 268 if (ENABLE_FEAT_HCX == FEAT_STATE_ALWAYS) { 269 return true; 270 } 271 272 return read_feat_hcx_id_field() != 0U; 273 } 274 275 static inline bool is_feat_rng_trap_present(void) 276 { 277 return (((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT) & 278 ID_AA64PFR1_EL1_RNDR_TRAP_MASK) 279 == ID_AA64PFR1_EL1_RNG_TRAP_SUPPORTED); 280 } 281 282 static inline unsigned int get_armv9_2_feat_rme_support(void) 283 { 284 /* 285 * Return the RME version, zero if not supported. This function can be 286 * used as both an integer value for the RME version or compared to zero 287 * to detect RME presence. 288 */ 289 return (unsigned int)(read_id_aa64pfr0_el1() >> 290 ID_AA64PFR0_FEAT_RME_SHIFT) & ID_AA64PFR0_FEAT_RME_MASK; 291 } 292 293 /********************************************************************************* 294 * Function to identify the presence of FEAT_SB (Speculation Barrier Instruction) 295 ********************************************************************************/ 296 static inline unsigned int read_feat_sb_id_field(void) 297 { 298 return ISOLATE_FIELD(read_id_aa64isar1_el1(), ID_AA64ISAR1_SB); 299 } 300 301 /********************************************************************************* 302 * Function to identify the presence of FEAT_CSV2_2 (Cache Speculation Variant 2) 303 ********************************************************************************/ 304 static inline unsigned int read_feat_csv2_id_field(void) 305 { 306 return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_CSV2); 307 } 308 309 static inline bool is_feat_csv2_2_supported(void) 310 { 311 if (ENABLE_FEAT_CSV2_2 == FEAT_STATE_DISABLED) { 312 return false; 313 } 314 315 if (ENABLE_FEAT_CSV2_2 == FEAT_STATE_ALWAYS) { 316 return true; 317 } 318 319 return read_feat_csv2_id_field() >= ID_AA64PFR0_CSV2_2_SUPPORTED; 320 } 321 322 /********************************************************************************** 323 * Function to identify the presence of FEAT_SPE (Statistical Profiling Extension) 324 *********************************************************************************/ 325 static inline unsigned int read_feat_spe_id_field(void) 326 { 327 return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_PMS); 328 } 329 330 static inline bool is_feat_spe_supported(void) 331 { 332 if (ENABLE_SPE_FOR_NS == FEAT_STATE_DISABLED) { 333 return false; 334 } 335 336 if (ENABLE_SPE_FOR_NS == FEAT_STATE_ALWAYS) { 337 return true; 338 } 339 340 return read_feat_spe_id_field() != 0U; 341 } 342 343 /******************************************************************************* 344 * Function to identify the presence of FEAT_SVE (Scalable Vector Extension) 345 ******************************************************************************/ 346 static inline bool is_armv8_2_feat_sve_present(void) 347 { 348 return (((read_id_aa64pfr0_el1() >> ID_AA64PFR0_SVE_SHIFT) & 349 ID_AA64PFR0_SVE_MASK) == ID_AA64PFR0_SVE_SUPPORTED); 350 } 351 352 /******************************************************************************* 353 * Function to identify the presence of FEAT_RAS (Reliability,Availability, 354 * and Serviceability Extension) 355 ******************************************************************************/ 356 static inline bool is_armv8_2_feat_ras_present(void) 357 { 358 return (((read_id_aa64pfr0_el1() >> ID_AA64PFR0_RAS_SHIFT) & 359 ID_AA64PFR0_RAS_MASK) != ID_AA64PFR0_RAS_NOT_SUPPORTED); 360 } 361 362 /************************************************************************** 363 * Function to identify the presence of FEAT_DIT (Data Independent Timing) 364 *************************************************************************/ 365 static inline bool is_armv8_4_feat_dit_present(void) 366 { 367 return (((read_id_aa64pfr0_el1() >> ID_AA64PFR0_DIT_SHIFT) & 368 ID_AA64PFR0_DIT_MASK) == ID_AA64PFR0_DIT_SUPPORTED); 369 } 370 371 static inline unsigned int read_feat_tracever_id_field(void) 372 { 373 return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_TRACEVER); 374 } 375 376 static inline bool is_feat_sys_reg_trace_supported(void) 377 { 378 if (ENABLE_SYS_REG_TRACE_FOR_NS == FEAT_STATE_DISABLED) { 379 return false; 380 } 381 382 if (ENABLE_SYS_REG_TRACE_FOR_NS == FEAT_STATE_ALWAYS) { 383 return true; 384 } 385 386 return read_feat_tracever_id_field() != 0U; 387 } 388 389 /************************************************************************* 390 * Function to identify the presence of FEAT_TRF (TraceLift) 391 ************************************************************************/ 392 static inline unsigned int read_feat_trf_id_field(void) 393 { 394 return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_TRACEFILT); 395 } 396 397 static inline bool is_feat_trf_supported(void) 398 { 399 if (ENABLE_TRF_FOR_NS == FEAT_STATE_DISABLED) { 400 return false; 401 } 402 403 if (ENABLE_TRF_FOR_NS == FEAT_STATE_ALWAYS) { 404 return true; 405 } 406 407 return read_feat_trf_id_field() != 0U; 408 } 409 410 /******************************************************************************** 411 * Function to identify the presence of FEAT_NV2 (Enhanced Nested Virtualization 412 * Support) 413 *******************************************************************************/ 414 static inline unsigned int get_armv8_4_feat_nv_support(void) 415 { 416 return (((read_id_aa64mmfr2_el1() >> ID_AA64MMFR2_EL1_NV_SHIFT) & 417 ID_AA64MMFR2_EL1_NV_MASK)); 418 } 419 420 /******************************************************************************* 421 * Function to identify the presence of FEAT_BRBE (Branch Record Buffer 422 * Extension) 423 ******************************************************************************/ 424 static inline unsigned int read_feat_brbe_id_field(void) 425 { 426 return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_BRBE); 427 } 428 429 static inline bool is_feat_brbe_supported(void) 430 { 431 if (ENABLE_BRBE_FOR_NS == FEAT_STATE_DISABLED) { 432 return false; 433 } 434 435 if (ENABLE_BRBE_FOR_NS == FEAT_STATE_ALWAYS) { 436 return true; 437 } 438 439 return read_feat_brbe_id_field() != 0U; 440 } 441 442 /******************************************************************************* 443 * Function to identify the presence of FEAT_TRBE (Trace Buffer Extension) 444 ******************************************************************************/ 445 static inline unsigned int read_feat_trbe_id_field(void) 446 { 447 return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_TRACEBUFFER); 448 } 449 450 static inline bool is_feat_trbe_supported(void) 451 { 452 if (ENABLE_TRBE_FOR_NS == FEAT_STATE_DISABLED) { 453 return false; 454 } 455 456 if (ENABLE_TRBE_FOR_NS == FEAT_STATE_ALWAYS) { 457 return true; 458 } 459 460 return read_feat_trbe_id_field() != 0U; 461 462 } 463 #endif /* ARCH_FEATURES_H */ 464