1/* 2 * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <assert_macros.S> 10#include <context.h> 11#include <el3_common_macros.S> 12 13#if CTX_INCLUDE_EL2_REGS 14 .global el2_sysregs_context_save_common 15 .global el2_sysregs_context_restore_common 16#if CTX_INCLUDE_MTE_REGS 17 .global el2_sysregs_context_save_mte 18 .global el2_sysregs_context_restore_mte 19#endif /* CTX_INCLUDE_MTE_REGS */ 20#if RAS_EXTENSION 21 .global el2_sysregs_context_save_ras 22 .global el2_sysregs_context_restore_ras 23#endif /* RAS_EXTENSION */ 24#if CTX_INCLUDE_NEVE_REGS 25 .global el2_sysregs_context_save_nv2 26 .global el2_sysregs_context_restore_nv2 27#endif /* CTX_INCLUDE_NEVE_REGS */ 28#if ENABLE_FEAT_CSV2_2 29 .global el2_sysregs_context_save_csv2 30 .global el2_sysregs_context_restore_csv2 31#endif /* ENABLE_FEAT_CSV2_2 */ 32#endif /* CTX_INCLUDE_EL2_REGS */ 33 34 .global el1_sysregs_context_save 35 .global el1_sysregs_context_restore 36#if CTX_INCLUDE_FPREGS 37 .global fpregs_context_save 38 .global fpregs_context_restore 39#endif /* CTX_INCLUDE_FPREGS */ 40 .global prepare_el3_entry 41 .global restore_gp_pmcr_pauth_regs 42 .global save_and_update_ptw_el1_sys_regs 43 .global el3_exit 44 45#if CTX_INCLUDE_EL2_REGS 46 47/* ----------------------------------------------------- 48 * The following functions strictly follow the AArch64 49 * PCS to use x9-x16 (temporary caller-saved registers) 50 * to save/restore EL2 system register context. 51 * el2_sysregs_context_save/restore_common functions 52 * save and restore registers that are common to all 53 * configurations. The rest of the functions save and 54 * restore EL2 system registers that are present when a 55 * particular feature is enabled. All functions assume 56 * that 'x0' is pointing to a 'el2_sys_regs' structure 57 * where the register context will be saved/restored. 58 * 59 * The following registers are not added. 60 * AMEVCNTVOFF0<n>_EL2 61 * AMEVCNTVOFF1<n>_EL2 62 * ICH_AP0R<n>_EL2 63 * ICH_AP1R<n>_EL2 64 * ICH_LR<n>_EL2 65 * ----------------------------------------------------- 66 */ 67func el2_sysregs_context_save_common 68 mrs x9, actlr_el2 69 mrs x10, afsr0_el2 70 stp x9, x10, [x0, #CTX_ACTLR_EL2] 71 72 mrs x11, afsr1_el2 73 mrs x12, amair_el2 74 stp x11, x12, [x0, #CTX_AFSR1_EL2] 75 76 mrs x13, cnthctl_el2 77 mrs x14, cntvoff_el2 78 stp x13, x14, [x0, #CTX_CNTHCTL_EL2] 79 80 mrs x15, cptr_el2 81 str x15, [x0, #CTX_CPTR_EL2] 82 83#if CTX_INCLUDE_AARCH32_REGS 84 mrs x16, dbgvcr32_el2 85 str x16, [x0, #CTX_DBGVCR32_EL2] 86#endif /* CTX_INCLUDE_AARCH32_REGS */ 87 88 mrs x9, elr_el2 89 mrs x10, esr_el2 90 stp x9, x10, [x0, #CTX_ELR_EL2] 91 92 mrs x11, far_el2 93 mrs x12, hacr_el2 94 stp x11, x12, [x0, #CTX_FAR_EL2] 95 96 mrs x13, hcr_el2 97 mrs x14, hpfar_el2 98 stp x13, x14, [x0, #CTX_HCR_EL2] 99 100 mrs x15, hstr_el2 101 mrs x16, ICC_SRE_EL2 102 stp x15, x16, [x0, #CTX_HSTR_EL2] 103 104 mrs x9, ICH_HCR_EL2 105 mrs x10, ICH_VMCR_EL2 106 stp x9, x10, [x0, #CTX_ICH_HCR_EL2] 107 108 mrs x11, mair_el2 109 mrs x12, mdcr_el2 110 stp x11, x12, [x0, #CTX_MAIR_EL2] 111 112 mrs x14, sctlr_el2 113 str x14, [x0, #CTX_SCTLR_EL2] 114 115 mrs x15, spsr_el2 116 mrs x16, sp_el2 117 stp x15, x16, [x0, #CTX_SPSR_EL2] 118 119 mrs x9, tcr_el2 120 mrs x10, tpidr_el2 121 stp x9, x10, [x0, #CTX_TCR_EL2] 122 123 mrs x11, ttbr0_el2 124 mrs x12, vbar_el2 125 stp x11, x12, [x0, #CTX_TTBR0_EL2] 126 127 mrs x13, vmpidr_el2 128 mrs x14, vpidr_el2 129 stp x13, x14, [x0, #CTX_VMPIDR_EL2] 130 131 mrs x15, vtcr_el2 132 mrs x16, vttbr_el2 133 stp x15, x16, [x0, #CTX_VTCR_EL2] 134 ret 135endfunc el2_sysregs_context_save_common 136 137func el2_sysregs_context_restore_common 138 ldp x9, x10, [x0, #CTX_ACTLR_EL2] 139 msr actlr_el2, x9 140 msr afsr0_el2, x10 141 142 ldp x11, x12, [x0, #CTX_AFSR1_EL2] 143 msr afsr1_el2, x11 144 msr amair_el2, x12 145 146 ldp x13, x14, [x0, #CTX_CNTHCTL_EL2] 147 msr cnthctl_el2, x13 148 msr cntvoff_el2, x14 149 150 ldr x15, [x0, #CTX_CPTR_EL2] 151 msr cptr_el2, x15 152 153#if CTX_INCLUDE_AARCH32_REGS 154 ldr x16, [x0, #CTX_DBGVCR32_EL2] 155 msr dbgvcr32_el2, x16 156#endif /* CTX_INCLUDE_AARCH32_REGS */ 157 158 ldp x9, x10, [x0, #CTX_ELR_EL2] 159 msr elr_el2, x9 160 msr esr_el2, x10 161 162 ldp x11, x12, [x0, #CTX_FAR_EL2] 163 msr far_el2, x11 164 msr hacr_el2, x12 165 166 ldp x13, x14, [x0, #CTX_HCR_EL2] 167 msr hcr_el2, x13 168 msr hpfar_el2, x14 169 170 ldp x15, x16, [x0, #CTX_HSTR_EL2] 171 msr hstr_el2, x15 172 msr ICC_SRE_EL2, x16 173 174 ldp x9, x10, [x0, #CTX_ICH_HCR_EL2] 175 msr ICH_HCR_EL2, x9 176 msr ICH_VMCR_EL2, x10 177 178 ldp x11, x12, [x0, #CTX_MAIR_EL2] 179 msr mair_el2, x11 180 msr mdcr_el2, x12 181 182 ldr x14, [x0, #CTX_SCTLR_EL2] 183 msr sctlr_el2, x14 184 185 ldp x15, x16, [x0, #CTX_SPSR_EL2] 186 msr spsr_el2, x15 187 msr sp_el2, x16 188 189 ldp x9, x10, [x0, #CTX_TCR_EL2] 190 msr tcr_el2, x9 191 msr tpidr_el2, x10 192 193 ldp x11, x12, [x0, #CTX_TTBR0_EL2] 194 msr ttbr0_el2, x11 195 msr vbar_el2, x12 196 197 ldp x13, x14, [x0, #CTX_VMPIDR_EL2] 198 msr vmpidr_el2, x13 199 msr vpidr_el2, x14 200 201 ldp x15, x16, [x0, #CTX_VTCR_EL2] 202 msr vtcr_el2, x15 203 msr vttbr_el2, x16 204 ret 205endfunc el2_sysregs_context_restore_common 206 207#if CTX_INCLUDE_MTE_REGS 208func el2_sysregs_context_save_mte 209 mrs x9, TFSR_EL2 210 str x9, [x0, #CTX_TFSR_EL2] 211 ret 212endfunc el2_sysregs_context_save_mte 213 214func el2_sysregs_context_restore_mte 215 ldr x9, [x0, #CTX_TFSR_EL2] 216 msr TFSR_EL2, x9 217 ret 218endfunc el2_sysregs_context_restore_mte 219#endif /* CTX_INCLUDE_MTE_REGS */ 220 221#if RAS_EXTENSION 222func el2_sysregs_context_save_ras 223 /* 224 * VDISR_EL2 and VSESR_EL2 registers are saved only when 225 * FEAT_RAS is supported. 226 */ 227 mrs x11, vdisr_el2 228 mrs x12, vsesr_el2 229 stp x11, x12, [x0, #CTX_VDISR_EL2] 230 ret 231endfunc el2_sysregs_context_save_ras 232 233func el2_sysregs_context_restore_ras 234 /* 235 * VDISR_EL2 and VSESR_EL2 registers are restored only when FEAT_RAS 236 * is supported. 237 */ 238 ldp x11, x12, [x0, #CTX_VDISR_EL2] 239 msr vdisr_el2, x11 240 msr vsesr_el2, x12 241 ret 242endfunc el2_sysregs_context_restore_ras 243#endif /* RAS_EXTENSION */ 244 245#if CTX_INCLUDE_NEVE_REGS 246func el2_sysregs_context_save_nv2 247 /* 248 * VNCR_EL2 register is saved only when FEAT_NV2 is supported. 249 */ 250 mrs x16, vncr_el2 251 str x16, [x0, #CTX_VNCR_EL2] 252 ret 253endfunc el2_sysregs_context_save_nv2 254 255func el2_sysregs_context_restore_nv2 256 /* 257 * VNCR_EL2 register is restored only when FEAT_NV2 is supported. 258 */ 259 ldr x16, [x0, #CTX_VNCR_EL2] 260 msr vncr_el2, x16 261 ret 262endfunc el2_sysregs_context_restore_nv2 263#endif /* CTX_INCLUDE_NEVE_REGS */ 264 265#if ENABLE_FEAT_CSV2_2 266func el2_sysregs_context_save_csv2 267 /* 268 * SCXTNUM_EL2 register is saved only when FEAT_CSV2_2 is supported. 269 */ 270 mrs x13, scxtnum_el2 271 str x13, [x0, #CTX_SCXTNUM_EL2] 272 ret 273endfunc el2_sysregs_context_save_csv2 274 275func el2_sysregs_context_restore_csv2 276 /* 277 * SCXTNUM_EL2 register is restored only when FEAT_CSV2_2 is supported. 278 */ 279 ldr x13, [x0, #CTX_SCXTNUM_EL2] 280 msr scxtnum_el2, x13 281 ret 282endfunc el2_sysregs_context_restore_csv2 283#endif /* ENABLE_FEAT_CSV2_2 */ 284 285#endif /* CTX_INCLUDE_EL2_REGS */ 286 287/* ------------------------------------------------------------------ 288 * The following function strictly follows the AArch64 PCS to use 289 * x9-x17 (temporary caller-saved registers) to save EL1 system 290 * register context. It assumes that 'x0' is pointing to a 291 * 'el1_sys_regs' structure where the register context will be saved. 292 * ------------------------------------------------------------------ 293 */ 294func el1_sysregs_context_save 295 296 mrs x9, spsr_el1 297 mrs x10, elr_el1 298 stp x9, x10, [x0, #CTX_SPSR_EL1] 299 300#if !ERRATA_SPECULATIVE_AT 301 mrs x15, sctlr_el1 302 mrs x16, tcr_el1 303 stp x15, x16, [x0, #CTX_SCTLR_EL1] 304#endif /* ERRATA_SPECULATIVE_AT */ 305 306 mrs x17, cpacr_el1 307 mrs x9, csselr_el1 308 stp x17, x9, [x0, #CTX_CPACR_EL1] 309 310 mrs x10, sp_el1 311 mrs x11, esr_el1 312 stp x10, x11, [x0, #CTX_SP_EL1] 313 314 mrs x12, ttbr0_el1 315 mrs x13, ttbr1_el1 316 stp x12, x13, [x0, #CTX_TTBR0_EL1] 317 318 mrs x14, mair_el1 319 mrs x15, amair_el1 320 stp x14, x15, [x0, #CTX_MAIR_EL1] 321 322 mrs x16, actlr_el1 323 mrs x17, tpidr_el1 324 stp x16, x17, [x0, #CTX_ACTLR_EL1] 325 326 mrs x9, tpidr_el0 327 mrs x10, tpidrro_el0 328 stp x9, x10, [x0, #CTX_TPIDR_EL0] 329 330 mrs x13, par_el1 331 mrs x14, far_el1 332 stp x13, x14, [x0, #CTX_PAR_EL1] 333 334 mrs x15, afsr0_el1 335 mrs x16, afsr1_el1 336 stp x15, x16, [x0, #CTX_AFSR0_EL1] 337 338 mrs x17, contextidr_el1 339 mrs x9, vbar_el1 340 stp x17, x9, [x0, #CTX_CONTEXTIDR_EL1] 341 342 /* Save AArch32 system registers if the build has instructed so */ 343#if CTX_INCLUDE_AARCH32_REGS 344 mrs x11, spsr_abt 345 mrs x12, spsr_und 346 stp x11, x12, [x0, #CTX_SPSR_ABT] 347 348 mrs x13, spsr_irq 349 mrs x14, spsr_fiq 350 stp x13, x14, [x0, #CTX_SPSR_IRQ] 351 352 mrs x15, dacr32_el2 353 mrs x16, ifsr32_el2 354 stp x15, x16, [x0, #CTX_DACR32_EL2] 355#endif /* CTX_INCLUDE_AARCH32_REGS */ 356 357 /* Save NS timer registers if the build has instructed so */ 358#if NS_TIMER_SWITCH 359 mrs x10, cntp_ctl_el0 360 mrs x11, cntp_cval_el0 361 stp x10, x11, [x0, #CTX_CNTP_CTL_EL0] 362 363 mrs x12, cntv_ctl_el0 364 mrs x13, cntv_cval_el0 365 stp x12, x13, [x0, #CTX_CNTV_CTL_EL0] 366 367 mrs x14, cntkctl_el1 368 str x14, [x0, #CTX_CNTKCTL_EL1] 369#endif /* NS_TIMER_SWITCH */ 370 371 /* Save MTE system registers if the build has instructed so */ 372#if CTX_INCLUDE_MTE_REGS 373 mrs x15, TFSRE0_EL1 374 mrs x16, TFSR_EL1 375 stp x15, x16, [x0, #CTX_TFSRE0_EL1] 376 377 mrs x9, RGSR_EL1 378 mrs x10, GCR_EL1 379 stp x9, x10, [x0, #CTX_RGSR_EL1] 380#endif /* CTX_INCLUDE_MTE_REGS */ 381 382 ret 383endfunc el1_sysregs_context_save 384 385/* ------------------------------------------------------------------ 386 * The following function strictly follows the AArch64 PCS to use 387 * x9-x17 (temporary caller-saved registers) to restore EL1 system 388 * register context. It assumes that 'x0' is pointing to a 389 * 'el1_sys_regs' structure from where the register context will be 390 * restored 391 * ------------------------------------------------------------------ 392 */ 393func el1_sysregs_context_restore 394 395 ldp x9, x10, [x0, #CTX_SPSR_EL1] 396 msr spsr_el1, x9 397 msr elr_el1, x10 398 399#if !ERRATA_SPECULATIVE_AT 400 ldp x15, x16, [x0, #CTX_SCTLR_EL1] 401 msr sctlr_el1, x15 402 msr tcr_el1, x16 403#endif /* ERRATA_SPECULATIVE_AT */ 404 405 ldp x17, x9, [x0, #CTX_CPACR_EL1] 406 msr cpacr_el1, x17 407 msr csselr_el1, x9 408 409 ldp x10, x11, [x0, #CTX_SP_EL1] 410 msr sp_el1, x10 411 msr esr_el1, x11 412 413 ldp x12, x13, [x0, #CTX_TTBR0_EL1] 414 msr ttbr0_el1, x12 415 msr ttbr1_el1, x13 416 417 ldp x14, x15, [x0, #CTX_MAIR_EL1] 418 msr mair_el1, x14 419 msr amair_el1, x15 420 421 ldp x16, x17, [x0, #CTX_ACTLR_EL1] 422 msr actlr_el1, x16 423 msr tpidr_el1, x17 424 425 ldp x9, x10, [x0, #CTX_TPIDR_EL0] 426 msr tpidr_el0, x9 427 msr tpidrro_el0, x10 428 429 ldp x13, x14, [x0, #CTX_PAR_EL1] 430 msr par_el1, x13 431 msr far_el1, x14 432 433 ldp x15, x16, [x0, #CTX_AFSR0_EL1] 434 msr afsr0_el1, x15 435 msr afsr1_el1, x16 436 437 ldp x17, x9, [x0, #CTX_CONTEXTIDR_EL1] 438 msr contextidr_el1, x17 439 msr vbar_el1, x9 440 441 /* Restore AArch32 system registers if the build has instructed so */ 442#if CTX_INCLUDE_AARCH32_REGS 443 ldp x11, x12, [x0, #CTX_SPSR_ABT] 444 msr spsr_abt, x11 445 msr spsr_und, x12 446 447 ldp x13, x14, [x0, #CTX_SPSR_IRQ] 448 msr spsr_irq, x13 449 msr spsr_fiq, x14 450 451 ldp x15, x16, [x0, #CTX_DACR32_EL2] 452 msr dacr32_el2, x15 453 msr ifsr32_el2, x16 454#endif /* CTX_INCLUDE_AARCH32_REGS */ 455 456 /* Restore NS timer registers if the build has instructed so */ 457#if NS_TIMER_SWITCH 458 ldp x10, x11, [x0, #CTX_CNTP_CTL_EL0] 459 msr cntp_ctl_el0, x10 460 msr cntp_cval_el0, x11 461 462 ldp x12, x13, [x0, #CTX_CNTV_CTL_EL0] 463 msr cntv_ctl_el0, x12 464 msr cntv_cval_el0, x13 465 466 ldr x14, [x0, #CTX_CNTKCTL_EL1] 467 msr cntkctl_el1, x14 468#endif /* NS_TIMER_SWITCH */ 469 470 /* Restore MTE system registers if the build has instructed so */ 471#if CTX_INCLUDE_MTE_REGS 472 ldp x11, x12, [x0, #CTX_TFSRE0_EL1] 473 msr TFSRE0_EL1, x11 474 msr TFSR_EL1, x12 475 476 ldp x13, x14, [x0, #CTX_RGSR_EL1] 477 msr RGSR_EL1, x13 478 msr GCR_EL1, x14 479#endif /* CTX_INCLUDE_MTE_REGS */ 480 481 /* No explict ISB required here as ERET covers it */ 482 ret 483endfunc el1_sysregs_context_restore 484 485/* ------------------------------------------------------------------ 486 * The following function follows the aapcs_64 strictly to use 487 * x9-x17 (temporary caller-saved registers according to AArch64 PCS) 488 * to save floating point register context. It assumes that 'x0' is 489 * pointing to a 'fp_regs' structure where the register context will 490 * be saved. 491 * 492 * Access to VFP registers will trap if CPTR_EL3.TFP is set. 493 * However currently we don't use VFP registers nor set traps in 494 * Trusted Firmware, and assume it's cleared. 495 * 496 * TODO: Revisit when VFP is used in secure world 497 * ------------------------------------------------------------------ 498 */ 499#if CTX_INCLUDE_FPREGS 500func fpregs_context_save 501 stp q0, q1, [x0, #CTX_FP_Q0] 502 stp q2, q3, [x0, #CTX_FP_Q2] 503 stp q4, q5, [x0, #CTX_FP_Q4] 504 stp q6, q7, [x0, #CTX_FP_Q6] 505 stp q8, q9, [x0, #CTX_FP_Q8] 506 stp q10, q11, [x0, #CTX_FP_Q10] 507 stp q12, q13, [x0, #CTX_FP_Q12] 508 stp q14, q15, [x0, #CTX_FP_Q14] 509 stp q16, q17, [x0, #CTX_FP_Q16] 510 stp q18, q19, [x0, #CTX_FP_Q18] 511 stp q20, q21, [x0, #CTX_FP_Q20] 512 stp q22, q23, [x0, #CTX_FP_Q22] 513 stp q24, q25, [x0, #CTX_FP_Q24] 514 stp q26, q27, [x0, #CTX_FP_Q26] 515 stp q28, q29, [x0, #CTX_FP_Q28] 516 stp q30, q31, [x0, #CTX_FP_Q30] 517 518 mrs x9, fpsr 519 str x9, [x0, #CTX_FP_FPSR] 520 521 mrs x10, fpcr 522 str x10, [x0, #CTX_FP_FPCR] 523 524#if CTX_INCLUDE_AARCH32_REGS 525 mrs x11, fpexc32_el2 526 str x11, [x0, #CTX_FP_FPEXC32_EL2] 527#endif /* CTX_INCLUDE_AARCH32_REGS */ 528 ret 529endfunc fpregs_context_save 530 531/* ------------------------------------------------------------------ 532 * The following function follows the aapcs_64 strictly to use x9-x17 533 * (temporary caller-saved registers according to AArch64 PCS) to 534 * restore floating point register context. It assumes that 'x0' is 535 * pointing to a 'fp_regs' structure from where the register context 536 * will be restored. 537 * 538 * Access to VFP registers will trap if CPTR_EL3.TFP is set. 539 * However currently we don't use VFP registers nor set traps in 540 * Trusted Firmware, and assume it's cleared. 541 * 542 * TODO: Revisit when VFP is used in secure world 543 * ------------------------------------------------------------------ 544 */ 545func fpregs_context_restore 546 ldp q0, q1, [x0, #CTX_FP_Q0] 547 ldp q2, q3, [x0, #CTX_FP_Q2] 548 ldp q4, q5, [x0, #CTX_FP_Q4] 549 ldp q6, q7, [x0, #CTX_FP_Q6] 550 ldp q8, q9, [x0, #CTX_FP_Q8] 551 ldp q10, q11, [x0, #CTX_FP_Q10] 552 ldp q12, q13, [x0, #CTX_FP_Q12] 553 ldp q14, q15, [x0, #CTX_FP_Q14] 554 ldp q16, q17, [x0, #CTX_FP_Q16] 555 ldp q18, q19, [x0, #CTX_FP_Q18] 556 ldp q20, q21, [x0, #CTX_FP_Q20] 557 ldp q22, q23, [x0, #CTX_FP_Q22] 558 ldp q24, q25, [x0, #CTX_FP_Q24] 559 ldp q26, q27, [x0, #CTX_FP_Q26] 560 ldp q28, q29, [x0, #CTX_FP_Q28] 561 ldp q30, q31, [x0, #CTX_FP_Q30] 562 563 ldr x9, [x0, #CTX_FP_FPSR] 564 msr fpsr, x9 565 566 ldr x10, [x0, #CTX_FP_FPCR] 567 msr fpcr, x10 568 569#if CTX_INCLUDE_AARCH32_REGS 570 ldr x11, [x0, #CTX_FP_FPEXC32_EL2] 571 msr fpexc32_el2, x11 572#endif /* CTX_INCLUDE_AARCH32_REGS */ 573 574 /* 575 * No explict ISB required here as ERET to 576 * switch to secure EL1 or non-secure world 577 * covers it 578 */ 579 580 ret 581endfunc fpregs_context_restore 582#endif /* CTX_INCLUDE_FPREGS */ 583 584 /* 585 * Set SCR_EL3.EA bit to enable SErrors at EL3 586 */ 587 .macro enable_serror_at_el3 588 mrs x8, scr_el3 589 orr x8, x8, #SCR_EA_BIT 590 msr scr_el3, x8 591 .endm 592 593 /* 594 * Set the PSTATE bits not set when the exception was taken as 595 * described in the AArch64.TakeException() pseudocode function 596 * in ARM DDI 0487F.c page J1-7635 to a default value. 597 */ 598 .macro set_unset_pstate_bits 599 /* 600 * If Data Independent Timing (DIT) functionality is implemented, 601 * always enable DIT in EL3 602 */ 603#if ENABLE_FEAT_DIT 604 mov x8, #DIT_BIT 605 msr DIT, x8 606#endif /* ENABLE_FEAT_DIT */ 607 .endm /* set_unset_pstate_bits */ 608 609/* ------------------------------------------------------------------ 610 * The following macro is used to save and restore all the general 611 * purpose and ARMv8.3-PAuth (if enabled) registers. 612 * It also checks if the Secure Cycle Counter (PMCCNTR_EL0) 613 * is disabled in EL3/Secure (ARMv8.5-PMU), wherein PMCCNTR_EL0 614 * needs not to be saved/restored during world switch. 615 * 616 * Ideally we would only save and restore the callee saved registers 617 * when a world switch occurs but that type of implementation is more 618 * complex. So currently we will always save and restore these 619 * registers on entry and exit of EL3. 620 * clobbers: x18 621 * ------------------------------------------------------------------ 622 */ 623 .macro save_gp_pmcr_pauth_regs 624 stp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] 625 stp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2] 626 stp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4] 627 stp x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6] 628 stp x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8] 629 stp x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10] 630 stp x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12] 631 stp x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14] 632 stp x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16] 633 stp x18, x19, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X18] 634 stp x20, x21, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X20] 635 stp x22, x23, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X22] 636 stp x24, x25, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X24] 637 stp x26, x27, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X26] 638 stp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28] 639 mrs x18, sp_el0 640 str x18, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_SP_EL0] 641 642 /* ---------------------------------------------------------- 643 * Check if earlier initialization of MDCR_EL3.SCCD/MCCD to 1 644 * has failed. 645 * 646 * MDCR_EL3: 647 * MCCD bit set, Prohibits the Cycle Counter PMCCNTR_EL0 from 648 * counting at EL3. 649 * SCCD bit set, Secure Cycle Counter Disable. Prohibits PMCCNTR_EL0 650 * from counting in Secure state. 651 * If these bits are not set, meaning that FEAT_PMUv3p5/7 is 652 * not implemented and PMCR_EL0 should be saved in non-secure 653 * context. 654 * ---------------------------------------------------------- 655 */ 656 mov_imm x10, (MDCR_SCCD_BIT | MDCR_MCCD_BIT) 657 mrs x9, mdcr_el3 658 tst x9, x10 659 bne 1f 660 661 /* ---------------------------------------------------------- 662 * If control reaches here, it ensures the Secure Cycle 663 * Counter (PMCCNTR_EL0) is not prohibited from counting at 664 * EL3 and in secure states. 665 * Henceforth, PMCR_EL0 to be saved before world switch. 666 * ---------------------------------------------------------- 667 */ 668 mrs x9, pmcr_el0 669 670 /* Check caller's security state */ 671 mrs x10, scr_el3 672 tst x10, #SCR_NS_BIT 673 beq 2f 674 675 /* Save PMCR_EL0 if called from Non-secure state */ 676 str x9, [sp, #CTX_EL3STATE_OFFSET + CTX_PMCR_EL0] 677 678 /* Disable cycle counter when event counting is prohibited */ 6792: orr x9, x9, #PMCR_EL0_DP_BIT 680 msr pmcr_el0, x9 681 isb 6821: 683#if CTX_INCLUDE_PAUTH_REGS 684 /* ---------------------------------------------------------- 685 * Save the ARMv8.3-PAuth keys as they are not banked 686 * by exception level 687 * ---------------------------------------------------------- 688 */ 689 add x19, sp, #CTX_PAUTH_REGS_OFFSET 690 691 mrs x20, APIAKeyLo_EL1 /* x21:x20 = APIAKey */ 692 mrs x21, APIAKeyHi_EL1 693 mrs x22, APIBKeyLo_EL1 /* x23:x22 = APIBKey */ 694 mrs x23, APIBKeyHi_EL1 695 mrs x24, APDAKeyLo_EL1 /* x25:x24 = APDAKey */ 696 mrs x25, APDAKeyHi_EL1 697 mrs x26, APDBKeyLo_EL1 /* x27:x26 = APDBKey */ 698 mrs x27, APDBKeyHi_EL1 699 mrs x28, APGAKeyLo_EL1 /* x29:x28 = APGAKey */ 700 mrs x29, APGAKeyHi_EL1 701 702 stp x20, x21, [x19, #CTX_PACIAKEY_LO] 703 stp x22, x23, [x19, #CTX_PACIBKEY_LO] 704 stp x24, x25, [x19, #CTX_PACDAKEY_LO] 705 stp x26, x27, [x19, #CTX_PACDBKEY_LO] 706 stp x28, x29, [x19, #CTX_PACGAKEY_LO] 707#endif /* CTX_INCLUDE_PAUTH_REGS */ 708 .endm /* save_gp_pmcr_pauth_regs */ 709 710/* ----------------------------------------------------------------- 711 * This function saves the context and sets the PSTATE to a known 712 * state, preparing entry to el3. 713 * Save all the general purpose and ARMv8.3-PAuth (if enabled) 714 * registers. 715 * Then set any of the PSTATE bits that are not set by hardware 716 * according to the Aarch64.TakeException pseudocode in the Arm 717 * Architecture Reference Manual to a default value for EL3. 718 * clobbers: x17 719 * ----------------------------------------------------------------- 720 */ 721func prepare_el3_entry 722 save_gp_pmcr_pauth_regs 723 enable_serror_at_el3 724 /* 725 * Set the PSTATE bits not described in the Aarch64.TakeException 726 * pseudocode to their default values. 727 */ 728 set_unset_pstate_bits 729 ret 730endfunc prepare_el3_entry 731 732/* ------------------------------------------------------------------ 733 * This function restores ARMv8.3-PAuth (if enabled) and all general 734 * purpose registers except x30 from the CPU context. 735 * x30 register must be explicitly restored by the caller. 736 * ------------------------------------------------------------------ 737 */ 738func restore_gp_pmcr_pauth_regs 739#if CTX_INCLUDE_PAUTH_REGS 740 /* Restore the ARMv8.3 PAuth keys */ 741 add x10, sp, #CTX_PAUTH_REGS_OFFSET 742 743 ldp x0, x1, [x10, #CTX_PACIAKEY_LO] /* x1:x0 = APIAKey */ 744 ldp x2, x3, [x10, #CTX_PACIBKEY_LO] /* x3:x2 = APIBKey */ 745 ldp x4, x5, [x10, #CTX_PACDAKEY_LO] /* x5:x4 = APDAKey */ 746 ldp x6, x7, [x10, #CTX_PACDBKEY_LO] /* x7:x6 = APDBKey */ 747 ldp x8, x9, [x10, #CTX_PACGAKEY_LO] /* x9:x8 = APGAKey */ 748 749 msr APIAKeyLo_EL1, x0 750 msr APIAKeyHi_EL1, x1 751 msr APIBKeyLo_EL1, x2 752 msr APIBKeyHi_EL1, x3 753 msr APDAKeyLo_EL1, x4 754 msr APDAKeyHi_EL1, x5 755 msr APDBKeyLo_EL1, x6 756 msr APDBKeyHi_EL1, x7 757 msr APGAKeyLo_EL1, x8 758 msr APGAKeyHi_EL1, x9 759#endif /* CTX_INCLUDE_PAUTH_REGS */ 760 761 /* ---------------------------------------------------------- 762 * Restore PMCR_EL0 when returning to Non-secure state if 763 * Secure Cycle Counter is not disabled in MDCR_EL3 when 764 * ARMv8.5-PMU is implemented. 765 * ---------------------------------------------------------- 766 */ 767 mrs x0, scr_el3 768 tst x0, #SCR_NS_BIT 769 beq 2f 770 771 /* ---------------------------------------------------------- 772 * Back to Non-secure state. 773 * Check if earlier initialization MDCR_EL3.SCCD/MCCD to 1 774 * failed, meaning that FEAT_PMUv3p5/7 is not implemented and 775 * PMCR_EL0 should be restored from non-secure context. 776 * ---------------------------------------------------------- 777 */ 778 mov_imm x1, (MDCR_SCCD_BIT | MDCR_MCCD_BIT) 779 mrs x0, mdcr_el3 780 tst x0, x1 781 bne 2f 782 ldr x0, [sp, #CTX_EL3STATE_OFFSET + CTX_PMCR_EL0] 783 msr pmcr_el0, x0 7842: 785 ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] 786 ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2] 787 ldp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4] 788 ldp x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6] 789 ldp x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8] 790 ldp x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10] 791 ldp x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12] 792 ldp x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14] 793 ldp x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16] 794 ldp x18, x19, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X18] 795 ldp x20, x21, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X20] 796 ldp x22, x23, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X22] 797 ldp x24, x25, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X24] 798 ldp x26, x27, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X26] 799 ldr x28, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_SP_EL0] 800 msr sp_el0, x28 801 ldp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28] 802 ret 803endfunc restore_gp_pmcr_pauth_regs 804 805/* 806 * In case of ERRATA_SPECULATIVE_AT, save SCTLR_EL1 and TCR_EL1 807 * registers and update EL1 registers to disable stage1 and stage2 808 * page table walk 809 */ 810func save_and_update_ptw_el1_sys_regs 811 /* ---------------------------------------------------------- 812 * Save only sctlr_el1 and tcr_el1 registers 813 * ---------------------------------------------------------- 814 */ 815 mrs x29, sctlr_el1 816 str x29, [sp, #(CTX_EL1_SYSREGS_OFFSET + CTX_SCTLR_EL1)] 817 mrs x29, tcr_el1 818 str x29, [sp, #(CTX_EL1_SYSREGS_OFFSET + CTX_TCR_EL1)] 819 820 /* ------------------------------------------------------------ 821 * Must follow below order in order to disable page table 822 * walk for lower ELs (EL1 and EL0). First step ensures that 823 * page table walk is disabled for stage1 and second step 824 * ensures that page table walker should use TCR_EL1.EPDx 825 * bits to perform address translation. ISB ensures that CPU 826 * does these 2 steps in order. 827 * 828 * 1. Update TCR_EL1.EPDx bits to disable page table walk by 829 * stage1. 830 * 2. Enable MMU bit to avoid identity mapping via stage2 831 * and force TCR_EL1.EPDx to be used by the page table 832 * walker. 833 * ------------------------------------------------------------ 834 */ 835 orr x29, x29, #(TCR_EPD0_BIT) 836 orr x29, x29, #(TCR_EPD1_BIT) 837 msr tcr_el1, x29 838 isb 839 mrs x29, sctlr_el1 840 orr x29, x29, #SCTLR_M_BIT 841 msr sctlr_el1, x29 842 isb 843 844 ret 845endfunc save_and_update_ptw_el1_sys_regs 846 847/* ------------------------------------------------------------------ 848 * This routine assumes that the SP_EL3 is pointing to a valid 849 * context structure from where the gp regs and other special 850 * registers can be retrieved. 851 * ------------------------------------------------------------------ 852 */ 853func el3_exit 854#if ENABLE_ASSERTIONS 855 /* el3_exit assumes SP_EL0 on entry */ 856 mrs x17, spsel 857 cmp x17, #MODE_SP_EL0 858 ASM_ASSERT(eq) 859#endif /* ENABLE_ASSERTIONS */ 860 861 /* ---------------------------------------------------------- 862 * Save the current SP_EL0 i.e. the EL3 runtime stack which 863 * will be used for handling the next SMC. 864 * Then switch to SP_EL3. 865 * ---------------------------------------------------------- 866 */ 867 mov x17, sp 868 msr spsel, #MODE_SP_ELX 869 str x17, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] 870 871#if IMAGE_BL31 872 /* ---------------------------------------------------------- 873 * Restore CPTR_EL3. 874 * ZCR is only restored if SVE is supported and enabled. 875 * Synchronization is required before zcr_el3 is addressed. 876 * ---------------------------------------------------------- 877 */ 878 ldp x19, x20, [sp, #CTX_EL3STATE_OFFSET + CTX_CPTR_EL3] 879 msr cptr_el3, x19 880 881 ands x19, x19, #CPTR_EZ_BIT 882 beq sve_not_enabled 883 884 isb 885 msr S3_6_C1_C2_0, x20 /* zcr_el3 */ 886sve_not_enabled: 887#endif /* IMAGE_BL31 */ 888 889#if IMAGE_BL31 && DYNAMIC_WORKAROUND_CVE_2018_3639 890 /* ---------------------------------------------------------- 891 * Restore mitigation state as it was on entry to EL3 892 * ---------------------------------------------------------- 893 */ 894 ldr x17, [sp, #CTX_CVE_2018_3639_OFFSET + CTX_CVE_2018_3639_DISABLE] 895 cbz x17, 1f 896 blr x17 8971: 898#endif /* IMAGE_BL31 && DYNAMIC_WORKAROUND_CVE_2018_3639 */ 899 900#if IMAGE_BL31 && RAS_EXTENSION 901 /* ---------------------------------------------------------- 902 * Issue Error Synchronization Barrier to synchronize SErrors 903 * before exiting EL3. We're running with EAs unmasked, so 904 * any synchronized errors would be taken immediately; 905 * therefore no need to inspect DISR_EL1 register. 906 * ---------------------------------------------------------- 907 */ 908 esb 909#else 910 dsb sy 911#endif /* IMAGE_BL31 && RAS_EXTENSION */ 912 913 /* ---------------------------------------------------------- 914 * Restore SPSR_EL3, ELR_EL3 and SCR_EL3 prior to ERET 915 * ---------------------------------------------------------- 916 */ 917 ldr x18, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3] 918 ldp x16, x17, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] 919 msr scr_el3, x18 920 msr spsr_el3, x16 921 msr elr_el3, x17 922 923 restore_ptw_el1_sys_regs 924 925 /* ---------------------------------------------------------- 926 * Restore general purpose (including x30), PMCR_EL0 and 927 * ARMv8.3-PAuth registers. 928 * Exit EL3 via ERET to a lower exception level. 929 * ---------------------------------------------------------- 930 */ 931 bl restore_gp_pmcr_pauth_regs 932 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 933 934#ifdef IMAGE_BL31 935 str xzr, [sp, #CTX_EL3STATE_OFFSET + CTX_IS_IN_EL3] 936#endif /* IMAGE_BL31 */ 937 938 exception_return 939 940endfunc el3_exit 941