1 /* 2 * Copyright (c) 2019-2023, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef ARCH_FEATURES_H 8 #define ARCH_FEATURES_H 9 10 #include <stdbool.h> 11 12 #include <arch_helpers.h> 13 #include <common/feat_detect.h> 14 15 #define ISOLATE_FIELD(reg, feat) \ 16 ((unsigned int)(((reg) >> (feat ## _SHIFT)) & (feat ## _MASK))) 17 18 static inline bool is_armv7_gentimer_present(void) 19 { 20 /* The Generic Timer is always present in an ARMv8-A implementation */ 21 return true; 22 } 23 24 static inline unsigned int read_feat_pan_id_field(void) 25 { 26 return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_PAN); 27 } 28 29 static inline bool is_feat_pan_supported(void) 30 { 31 if (ENABLE_FEAT_PAN == FEAT_STATE_DISABLED) { 32 return false; 33 } 34 35 if (ENABLE_FEAT_PAN == FEAT_STATE_ALWAYS) { 36 return true; 37 } 38 39 return read_feat_pan_id_field() != 0U; 40 } 41 42 static inline unsigned int read_feat_vhe_id_field(void) 43 { 44 return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_VHE); 45 } 46 47 static inline bool is_feat_vhe_supported(void) 48 { 49 if (ENABLE_FEAT_VHE == FEAT_STATE_DISABLED) { 50 return false; 51 } 52 53 if (ENABLE_FEAT_VHE == FEAT_STATE_ALWAYS) { 54 return true; 55 } 56 57 return read_feat_vhe_id_field() != 0U; 58 } 59 60 static inline bool is_armv8_2_ttcnp_present(void) 61 { 62 return ((read_id_aa64mmfr2_el1() >> ID_AA64MMFR2_EL1_CNP_SHIFT) & 63 ID_AA64MMFR2_EL1_CNP_MASK) != 0U; 64 } 65 66 static inline bool is_feat_pacqarma3_present(void) 67 { 68 uint64_t mask_id_aa64isar2 = 69 (ID_AA64ISAR2_GPA3_MASK << ID_AA64ISAR2_GPA3_SHIFT) | 70 (ID_AA64ISAR2_APA3_MASK << ID_AA64ISAR2_APA3_SHIFT); 71 72 /* If any of the fields is not zero, QARMA3 algorithm is present */ 73 return (read_id_aa64isar2_el1() & mask_id_aa64isar2) != 0U; 74 } 75 76 static inline bool is_armv8_3_pauth_present(void) 77 { 78 uint64_t mask_id_aa64isar1 = 79 (ID_AA64ISAR1_GPI_MASK << ID_AA64ISAR1_GPI_SHIFT) | 80 (ID_AA64ISAR1_GPA_MASK << ID_AA64ISAR1_GPA_SHIFT) | 81 (ID_AA64ISAR1_API_MASK << ID_AA64ISAR1_API_SHIFT) | 82 (ID_AA64ISAR1_APA_MASK << ID_AA64ISAR1_APA_SHIFT); 83 84 /* 85 * If any of the fields is not zero or QARMA3 is present, 86 * PAuth is present 87 */ 88 return ((read_id_aa64isar1_el1() & mask_id_aa64isar1) != 0U || 89 is_feat_pacqarma3_present()); 90 } 91 92 static inline bool is_armv8_4_dit_present(void) 93 { 94 return ((read_id_aa64pfr0_el1() >> ID_AA64PFR0_DIT_SHIFT) & 95 ID_AA64PFR0_DIT_MASK) == 1U; 96 } 97 98 static inline bool is_armv8_4_ttst_present(void) 99 { 100 return ((read_id_aa64mmfr2_el1() >> ID_AA64MMFR2_EL1_ST_SHIFT) & 101 ID_AA64MMFR2_EL1_ST_MASK) == 1U; 102 } 103 104 static inline bool is_armv8_5_bti_present(void) 105 { 106 return ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_BT_SHIFT) & 107 ID_AA64PFR1_EL1_BT_MASK) == BTI_IMPLEMENTED; 108 } 109 110 static inline unsigned int get_armv8_5_mte_support(void) 111 { 112 return ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_MTE_SHIFT) & 113 ID_AA64PFR1_EL1_MTE_MASK); 114 } 115 116 static inline bool is_armv8_4_sel2_present(void) 117 { 118 return ((read_id_aa64pfr0_el1() >> ID_AA64PFR0_SEL2_SHIFT) & 119 ID_AA64PFR0_SEL2_MASK) == 1ULL; 120 } 121 122 static inline unsigned int read_feat_twed_id_field(void) 123 { 124 return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_TWED); 125 } 126 127 static inline bool is_feat_twed_supported(void) 128 { 129 if (ENABLE_FEAT_TWED == FEAT_STATE_DISABLED) { 130 return false; 131 } 132 133 if (ENABLE_FEAT_TWED == FEAT_STATE_ALWAYS) { 134 return true; 135 } 136 137 return read_feat_twed_id_field() != 0U; 138 } 139 140 static unsigned int read_feat_fgt_id_field(void) 141 { 142 return ISOLATE_FIELD(read_id_aa64mmfr0_el1(), ID_AA64MMFR0_EL1_FGT); 143 } 144 145 static inline bool is_feat_fgt_supported(void) 146 { 147 if (ENABLE_FEAT_FGT == FEAT_STATE_DISABLED) { 148 return false; 149 } 150 151 if (ENABLE_FEAT_FGT == FEAT_STATE_ALWAYS) { 152 return true; 153 } 154 155 return read_feat_fgt_id_field() != 0U; 156 } 157 158 static unsigned int read_feat_ecv_id_field(void) 159 { 160 return ISOLATE_FIELD(read_id_aa64mmfr0_el1(), ID_AA64MMFR0_EL1_ECV); 161 } 162 163 static inline bool is_feat_ecv_supported(void) 164 { 165 if (ENABLE_FEAT_ECV == FEAT_STATE_DISABLED) { 166 return false; 167 } 168 169 if (ENABLE_FEAT_ECV == FEAT_STATE_ALWAYS) { 170 return true; 171 } 172 173 return read_feat_ecv_id_field() != 0U; 174 } 175 176 static inline bool is_feat_ecv_v2_supported(void) 177 { 178 if (ENABLE_FEAT_ECV == FEAT_STATE_DISABLED) { 179 return false; 180 } 181 182 if (ENABLE_FEAT_ECV == FEAT_STATE_ALWAYS) { 183 return true; 184 } 185 186 return read_feat_ecv_id_field() >= ID_AA64MMFR0_EL1_ECV_SELF_SYNCH; 187 } 188 189 static inline bool is_armv8_5_rng_present(void) 190 { 191 return ((read_id_aa64isar0_el1() >> ID_AA64ISAR0_RNDR_SHIFT) & 192 ID_AA64ISAR0_RNDR_MASK); 193 } 194 195 static unsigned int read_feat_tcrx_id_field(void) 196 { 197 return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_TCRX); 198 } 199 200 static inline bool is_feat_tcr2_supported(void) 201 { 202 if (ENABLE_FEAT_TCR2 == FEAT_STATE_DISABLED) { 203 return false; 204 } 205 206 if (ENABLE_FEAT_TCR2 == FEAT_STATE_ALWAYS) { 207 return true; 208 } 209 210 return read_feat_tcrx_id_field() != 0U; 211 } 212 213 /******************************************************************************* 214 * Functions to identify the presence of the Activity Monitors Extension 215 ******************************************************************************/ 216 static unsigned int read_feat_amu_id_field(void) 217 { 218 return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_AMU); 219 } 220 221 static inline bool is_feat_amu_supported(void) 222 { 223 if (ENABLE_FEAT_AMUv1 == FEAT_STATE_DISABLED) { 224 return false; 225 } 226 227 if (ENABLE_FEAT_AMUv1 == FEAT_STATE_ALWAYS) { 228 return true; 229 } 230 231 return read_feat_amu_id_field() >= ID_AA64PFR0_AMU_V1; 232 } 233 234 static inline bool is_armv8_6_feat_amuv1p1_present(void) 235 { 236 return read_feat_amu_id_field() >= ID_AA64PFR0_AMU_V1P1; 237 } 238 239 /* 240 * Return MPAM version: 241 * 242 * 0x00: None Armv8.0 or later 243 * 0x01: v0.1 Armv8.4 or later 244 * 0x10: v1.0 Armv8.2 or later 245 * 0x11: v1.1 Armv8.4 or later 246 * 247 */ 248 static inline unsigned int read_feat_mpam_version(void) 249 { 250 return (unsigned int)((((read_id_aa64pfr0_el1() >> 251 ID_AA64PFR0_MPAM_SHIFT) & ID_AA64PFR0_MPAM_MASK) << 4) | 252 ((read_id_aa64pfr1_el1() >> 253 ID_AA64PFR1_MPAM_FRAC_SHIFT) & ID_AA64PFR1_MPAM_FRAC_MASK)); 254 } 255 256 static inline bool is_feat_mpam_supported(void) 257 { 258 if (ENABLE_MPAM_FOR_LOWER_ELS == FEAT_STATE_DISABLED) { 259 return false; 260 } 261 262 if (ENABLE_MPAM_FOR_LOWER_ELS == FEAT_STATE_ALWAYS) { 263 return true; 264 } 265 266 return read_feat_mpam_version() != 0U; 267 } 268 269 static inline unsigned int read_feat_hcx_id_field(void) 270 { 271 return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_HCX); 272 } 273 274 static inline bool is_feat_hcx_supported(void) 275 { 276 if (ENABLE_FEAT_HCX == FEAT_STATE_DISABLED) { 277 return false; 278 } 279 280 if (ENABLE_FEAT_HCX == FEAT_STATE_ALWAYS) { 281 return true; 282 } 283 284 return read_feat_hcx_id_field() != 0U; 285 } 286 287 static inline bool is_feat_rng_trap_present(void) 288 { 289 return (((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT) & 290 ID_AA64PFR1_EL1_RNDR_TRAP_MASK) 291 == ID_AA64PFR1_EL1_RNG_TRAP_SUPPORTED); 292 } 293 294 static inline unsigned int get_armv9_2_feat_rme_support(void) 295 { 296 /* 297 * Return the RME version, zero if not supported. This function can be 298 * used as both an integer value for the RME version or compared to zero 299 * to detect RME presence. 300 */ 301 return (unsigned int)(read_id_aa64pfr0_el1() >> 302 ID_AA64PFR0_FEAT_RME_SHIFT) & ID_AA64PFR0_FEAT_RME_MASK; 303 } 304 305 /********************************************************************************* 306 * Function to identify the presence of FEAT_SB (Speculation Barrier Instruction) 307 ********************************************************************************/ 308 static inline unsigned int read_feat_sb_id_field(void) 309 { 310 return ISOLATE_FIELD(read_id_aa64isar1_el1(), ID_AA64ISAR1_SB); 311 } 312 313 /********************************************************************************* 314 * Function to identify the presence of FEAT_CSV2_2 (Cache Speculation Variant 2) 315 ********************************************************************************/ 316 static inline unsigned int read_feat_csv2_id_field(void) 317 { 318 return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_CSV2); 319 } 320 321 static inline bool is_feat_csv2_2_supported(void) 322 { 323 if (ENABLE_FEAT_CSV2_2 == FEAT_STATE_DISABLED) { 324 return false; 325 } 326 327 if (ENABLE_FEAT_CSV2_2 == FEAT_STATE_ALWAYS) { 328 return true; 329 } 330 331 return read_feat_csv2_id_field() >= ID_AA64PFR0_CSV2_2_SUPPORTED; 332 } 333 334 /********************************************************************************** 335 * Function to identify the presence of FEAT_SPE (Statistical Profiling Extension) 336 *********************************************************************************/ 337 static inline unsigned int read_feat_spe_id_field(void) 338 { 339 return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_PMS); 340 } 341 342 static inline bool is_feat_spe_supported(void) 343 { 344 if (ENABLE_SPE_FOR_NS == FEAT_STATE_DISABLED) { 345 return false; 346 } 347 348 if (ENABLE_SPE_FOR_NS == FEAT_STATE_ALWAYS) { 349 return true; 350 } 351 352 return read_feat_spe_id_field() != 0U; 353 } 354 355 /******************************************************************************* 356 * Function to identify the presence of FEAT_SVE (Scalable Vector Extension) 357 ******************************************************************************/ 358 static inline bool is_armv8_2_feat_sve_present(void) 359 { 360 return (((read_id_aa64pfr0_el1() >> ID_AA64PFR0_SVE_SHIFT) & 361 ID_AA64PFR0_SVE_MASK) == ID_AA64PFR0_SVE_SUPPORTED); 362 } 363 364 /******************************************************************************* 365 * Function to identify the presence of FEAT_RAS (Reliability,Availability, 366 * and Serviceability Extension) 367 ******************************************************************************/ 368 static inline bool is_armv8_2_feat_ras_present(void) 369 { 370 return (((read_id_aa64pfr0_el1() >> ID_AA64PFR0_RAS_SHIFT) & 371 ID_AA64PFR0_RAS_MASK) != ID_AA64PFR0_RAS_NOT_SUPPORTED); 372 } 373 374 /************************************************************************** 375 * Function to identify the presence of FEAT_DIT (Data Independent Timing) 376 *************************************************************************/ 377 static inline bool is_armv8_4_feat_dit_present(void) 378 { 379 return (((read_id_aa64pfr0_el1() >> ID_AA64PFR0_DIT_SHIFT) & 380 ID_AA64PFR0_DIT_MASK) == ID_AA64PFR0_DIT_SUPPORTED); 381 } 382 383 static inline unsigned int read_feat_tracever_id_field(void) 384 { 385 return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_TRACEVER); 386 } 387 388 static inline bool is_feat_sys_reg_trace_supported(void) 389 { 390 if (ENABLE_SYS_REG_TRACE_FOR_NS == FEAT_STATE_DISABLED) { 391 return false; 392 } 393 394 if (ENABLE_SYS_REG_TRACE_FOR_NS == FEAT_STATE_ALWAYS) { 395 return true; 396 } 397 398 return read_feat_tracever_id_field() != 0U; 399 } 400 401 /************************************************************************* 402 * Function to identify the presence of FEAT_TRF (TraceLift) 403 ************************************************************************/ 404 static inline unsigned int read_feat_trf_id_field(void) 405 { 406 return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_TRACEFILT); 407 } 408 409 static inline bool is_feat_trf_supported(void) 410 { 411 if (ENABLE_TRF_FOR_NS == FEAT_STATE_DISABLED) { 412 return false; 413 } 414 415 if (ENABLE_TRF_FOR_NS == FEAT_STATE_ALWAYS) { 416 return true; 417 } 418 419 return read_feat_trf_id_field() != 0U; 420 } 421 422 /******************************************************************************** 423 * Function to identify the presence of FEAT_NV2 (Enhanced Nested Virtualization 424 * Support) 425 *******************************************************************************/ 426 static inline unsigned int read_feat_nv_id_field(void) 427 { 428 return ISOLATE_FIELD(read_id_aa64mmfr2_el1(), ID_AA64MMFR2_EL1_NV); 429 } 430 431 static inline bool is_feat_nv2_supported(void) 432 { 433 if (CTX_INCLUDE_NEVE_REGS == FEAT_STATE_DISABLED) { 434 return false; 435 } 436 437 if (CTX_INCLUDE_NEVE_REGS == FEAT_STATE_ALWAYS) { 438 return true; 439 } 440 441 return read_feat_nv_id_field() >= ID_AA64MMFR2_EL1_NV2_SUPPORTED; 442 } 443 444 /******************************************************************************* 445 * Function to identify the presence of FEAT_BRBE (Branch Record Buffer 446 * Extension) 447 ******************************************************************************/ 448 static inline unsigned int read_feat_brbe_id_field(void) 449 { 450 return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_BRBE); 451 } 452 453 static inline bool is_feat_brbe_supported(void) 454 { 455 if (ENABLE_BRBE_FOR_NS == FEAT_STATE_DISABLED) { 456 return false; 457 } 458 459 if (ENABLE_BRBE_FOR_NS == FEAT_STATE_ALWAYS) { 460 return true; 461 } 462 463 return read_feat_brbe_id_field() != 0U; 464 } 465 466 /******************************************************************************* 467 * Function to identify the presence of FEAT_TRBE (Trace Buffer Extension) 468 ******************************************************************************/ 469 static inline unsigned int read_feat_trbe_id_field(void) 470 { 471 return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_TRACEBUFFER); 472 } 473 474 static inline bool is_feat_trbe_supported(void) 475 { 476 if (ENABLE_TRBE_FOR_NS == FEAT_STATE_DISABLED) { 477 return false; 478 } 479 480 if (ENABLE_TRBE_FOR_NS == FEAT_STATE_ALWAYS) { 481 return true; 482 } 483 484 return read_feat_trbe_id_field() != 0U; 485 486 } 487 #endif /* ARCH_FEATURES_H */ 488