feat(rk3568): protect TF-As memory area with the DDR firewall

Similar to most (all?) other Rockchip SoCs, the RK3568 also has a DDR
firewall to restrict memory regions to secure usage.

The original

feat(rk3568): protect TF-As memory area with the DDR firewall

Similar to most (all?) other Rockchip SoCs, the RK3568 also has a DDR
firewall to restrict memory regions to secure usage.

The original submission didn't protect the TF-A's memory region, so
implement this now with knowledge gained from comments in the OPTEE
pull-request for the rk356x [0].

Contrary to other SoCs like RK3576 and RK3588, the RK3568 memory
regions are managed in blocks of 128KB, not blocks of 1MB size.
With the registers having 16bit for upper and lower block id, this then
can completely fill the 8GB max ram size the RK356x supports.

The whole behaviour was tested with a number of reads from main u-boot.
With the current config of protecting everything in the first MB of memory,
doing any reads before the 1MB border will trigger the expected
"Synchronous Abort" and restart.

So doing
=> md 0x100000 4
will succeed, but reading anything before this will trigger the Abort.

[0] https://github.com/OP-TEE/optee_os/pull/6954#issuecomment-3041255974

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Diederik de Haas <diederik@cknow-tech.com>
Change-Id: I6c75ab2813566e727e46cea86dd229625a64dd3f

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feat(rk3568): bring DDR firewall naming in line

The TRM declares that region as FIREWALL_DDR, so name the memory region
accordingly in TF-A and also remove the double FW_DDR + _REG addon from
the on

feat(rk3568): bring DDR firewall naming in line

The TRM declares that region as FIREWALL_DDR, so name the memory region
accordingly in TF-A and also remove the double FW_DDR + _REG addon from
the one known register.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Change-Id: Ic098baa13b5c0b4cf339905030ee7d777bcbda34

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feat(rk3568): move existing secure init to separate files

Move the existing secure_timer_init() and sgrf_init() to a separate
file similar to the other Rockchip platforms.

This allows us to add add

feat(rk3568): move existing secure init to separate files

Move the existing secure_timer_init() and sgrf_init() to a separate
file similar to the other Rockchip platforms.

This allows us to add additional secure init later on.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Change-Id: I1151abed77d68b3730d505c547919e60415e3951

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fix(rockchip): fix comment and value about TZRAM_SIZE

TZRAM_SIZE is 0x100000 which is 1MB, not 512KB as the comment suggests.
Additionally using the existing SZ_1M constant is way nicer.

Signed-off

fix(rockchip): fix comment and value about TZRAM_SIZE

TZRAM_SIZE is 0x100000 which is 1MB, not 512KB as the comment suggests.
Additionally using the existing SZ_1M constant is way nicer.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Change-Id: I277347963b93f7ac69897cc1be252087521882e4

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feat(rk3588): report actual measured PVTPLL clocks

The GRF block includes a counter that measures PVTPLL clock pulses after
the CON1 register, exposed via STATUS1 and STATUS2. The counter uses an
in

feat(rk3588): report actual measured PVTPLL clocks

The GRF block includes a counter that measures PVTPLL clock pulses after
the CON1 register, exposed via STATUS1 and STATUS2. The counter uses an
input clock that can be configured in the CRU block; however, in the
current ATF implementation it is always XIN = 24 MHz.

The counter accumulates PVTPLL pulses for a window of:

measurement_time = CON1 / input_frequency

Since CON1 is fixed to 24, the current implementation measures over:

24 / 24 MHz = 1 µs

The resulting count is stored in the lower 14 bits of STATUS2.

This commit waits 2 µs (ensuring the 1 µs accumulation period completes)
and computes the PVTPLL frequency from the measured value. While CON1
could be increased for higher accuracy (as long as the 14-bit counter
does not overflow), this change keeps the existing 1 µs window for
simplicity.

With this feature, PVTPLL frequency can be measured with ~1 MHz
accuracy, instead of reporting only the configured frequency, which can
hide information related to chip degradation and environmental effects
impacting PVTPLL clocks.

Ideally the flow of measuring PVTPLL clocks should be the same for the
rest of RK35xx devices with minor tweaks at most.

Change-Id: Idc18246e8d794777f0dacc7820f15fcecc00af33
Signed-off-by: Hüseyin BIYIK <boogiepop@gmx.com>

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fix(rk3576): shorten names to fit into the allocated space

The SCMI spec's CLOCK_ATTRIBUTES command specifies the `clock_name` part
of the return value as 16 long. Three of rk3576's names are a char

fix(rk3576): shorten names to fit into the allocated space

The SCMI spec's CLOCK_ATTRIBUTES command specifies the `clock_name` part
of the return value as 16 long. Three of rk3576's names are a character
over, which GCC15 warns about truncating the NULL terminator. So shorten
the names a tiny bit to prevent this.

Change-Id: I20c97011f906018b67b1291753ce45fa48bc84a7
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(rk3568): support SCMI for clock/reset domain

rockchip scmi clock controls clocks which only available in secure mode.

Change-Id: Ide3a8dac72512ce79331592c3cbb86577de7df70
Signed-off-by: Shengf

feat(rk3568): support SCMI for clock/reset domain

rockchip scmi clock controls clocks which only available in secure mode.

Change-Id: Ide3a8dac72512ce79331592c3cbb86577de7df70
Signed-off-by: Shengfei Xu <xsf@rock-chips.com>

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Merge changes Id711e387,I531a2ee1,Ic5b48514,I81f5f663,I6c529c13, ... into integration

* changes:
refactor(romlib): absorb WRAPPER_FLAGS into LDFLAGS
fix(build): simplify the -target options
fe

Merge changes Id711e387,I531a2ee1,Ic5b48514,I81f5f663,I6c529c13, ... into integration

* changes:
refactor(romlib): absorb WRAPPER_FLAGS into LDFLAGS
fix(build): simplify the -target options
feat(build): allow full LTO builds with clang
refactor(build): make sorting of sections generic
feat(build): use clang as a linker
fix(build): correctly detect that an option is missing with ld_option
feat(build): pass cflags to the linker when LTO is enabled

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refactor(build): make it standard to request a custom linker script

Hoist the add_define to a global location so that platforms only have to
declare its usage. Fix up #ifdef to #if since we will now

refactor(build): make it standard to request a custom linker script

Hoist the add_define to a global location so that platforms only have to
declare its usage. Fix up #ifdef to #if since we will now always pass a
definition.

Change-Id: Ia52ad5ed4dcbd157d139c8ca2fb3d35b32343b93
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(build): correctly detect that an option is missing with ld_option

We support building directly with ld and indirectly with gcc. The
`ld_option` macro is oblivious to this and does a check for bo

fix(build): correctly detect that an option is missing with ld_option

We support building directly with ld and indirectly with gcc. The
`ld_option` macro is oblivious to this and does a check for both styles
of invocation. However, the gcc one is incorrect - gcc returns `0` even
when it has printed an error saying that it doesn't recognise the
option. Add a discovery function for each linker we expect and
dynamically dispatch to the correct one.

While we're at it, also add a little bit of code to return the -Wl
prefix for gcc and not for ld.

All of the above is also true for clang and lld, although they don't
suffer from the problem that gcc does.

Change-Id: I4f7bdf40c01f4c5df9c177f5048f5e349bc2b9c9
Co-authored-by: Chris Kay <chris.kay@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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refactor(build): avoid implicit pattern rules

This change translates any implicit pattern rules into the equivalent
static pattern rules, i.e. rules like:

%.o: %.s
...

... become:

refactor(build): avoid implicit pattern rules

This change translates any implicit pattern rules into the equivalent
static pattern rules, i.e. rules like:

%.o: %.s
...

... become:

$(OBJS): %.o: %.s
...

These behave similarly, but have some subtle differences. The former
defines a rule "for any target matching %.o where there is not a more
specific rule", whereas the latter defines a rule "for these targets,
which match %.o".

Where possible it is better to use a static pattern rule as it reduces
the rule space that Make needs to search.

Change-Id: Ifba4f44bcecf4e74980c31347e192cdf1e42003e
Signed-off-by: Chris Kay <chris.kay@arm.com>

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refactor(platforms): remove usage of psci_power_down_wfi

The callers in PSCI will now call wfi() after calling the
pwr_domain_pwr_down() platform hook (previously they were mutually
exclusive). As s

refactor(platforms): remove usage of psci_power_down_wfi

The callers in PSCI will now call wfi() after calling the
pwr_domain_pwr_down() platform hook (previously they were mutually
exclusive). As such, there is no need for platforms to do this
themselves. In fact, it is strongly advisable for platforms not to do
this themselves so that the PSCI can apply any relevant errata
mitigations.

Change-Id: Ic9702edef7503996be24d984e29dfcc13bc3fcba
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge "feat(rk3576): support rk3576" into integration

Merge "feat(rockchip): increase FDT Buffer for Rockchip Devices" into integration

feat(rk3576): support rk3576

rk3576 is an Octa-core soc with Cortex-a53/a72 inside.
This patch supports the following functions:
1. basic platform setup
2. power up/off cpus
3. suspend/resume cpus
4

feat(rk3576): support rk3576

rk3576 is an Octa-core soc with Cortex-a53/a72 inside.
This patch supports the following functions:
1. basic platform setup
2. power up/off cpus
3. suspend/resume cpus
4. suspend/resume system
5. reset system
6. power off system

Change-Id: I67a019822bd4af13e4a3cdd09cf06202f4922cc4
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>

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feat(rockchip): increase FDT Buffer for Rockchip Devices

Modify the FDT buffer for Rockchip devices to 384KiB. This is done to
allow us to pass mainline devicetrees with symbols through Arm Trusted

feat(rockchip): increase FDT Buffer for Rockchip Devices

Modify the FDT buffer for Rockchip devices to 384KiB. This is done to
allow us to pass mainline devicetrees with symbols through Arm Trusted
Firmware. 384KiB was chosen as 512KiB is very near the maximum
supported with the current reserved memory. As of kernel version 6.13,
the largest devicetree with symbols enabled is 215KiB, and the largest
Rockchip devicetree with symbols enabled is 176KiB
(rk3588-evb1-v10.dtb).

Change-Id: Iea9343d7a30ee26cad3ee5cc848980a93873ae34
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>

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