1 /*
2 * Copyright (c) 2016-2024, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #ifndef PMU_COM_H
8 #define PMU_COM_H
9
10 #ifndef CHECK_CPU_WFIE_BASE
11 #define CHECK_CPU_WFIE_BASE (PMU_BASE + PMU_CORE_PWR_ST)
12 #endif
13 /*
14 * Use this macro to instantiate lock before it is used in below
15 * rockchip_pd_lock_xxx() macros
16 */
17 DECLARE_BAKERY_LOCK(rockchip_pd_lock);
18
19 /*
20 * These are wrapper macros to the powe domain Bakery Lock API.
21 */
22 #define rockchip_pd_lock_init() bakery_lock_init(&rockchip_pd_lock)
23 #define rockchip_pd_lock_get() bakery_lock_get(&rockchip_pd_lock)
24 #define rockchip_pd_lock_rls() bakery_lock_release(&rockchip_pd_lock)
25
26 /*****************************************************************************
27 * power domain on or off
28 *****************************************************************************/
29 enum pmu_pd_state {
30 pmu_pd_on = 0,
31 pmu_pd_off = 1
32 };
33
34 #pragma weak plat_ic_get_pending_interrupt_id
35
pmu_power_domain_st(uint32_t pd)36 static inline uint32_t pmu_power_domain_st(uint32_t pd)
37 {
38 uint32_t pwrdn_st = mmio_read_32(PMU_BASE + PMU_PWRDN_ST) & BIT(pd);
39
40 if (pwrdn_st)
41 return pmu_pd_off;
42 else
43 return pmu_pd_on;
44 }
45
pmu_power_domain_ctr(uint32_t pd,uint32_t pd_state)46 static int pmu_power_domain_ctr(uint32_t pd, uint32_t pd_state)
47 {
48 uint32_t val;
49 uint32_t loop = 0;
50 int ret = 0;
51
52 rockchip_pd_lock_get();
53
54 val = mmio_read_32(PMU_BASE + PMU_PWRDN_CON);
55 if (pd_state == pmu_pd_off)
56 val |= BIT(pd);
57 else
58 val &= ~BIT(pd);
59
60 mmio_write_32(PMU_BASE + PMU_PWRDN_CON, val);
61 dsb();
62
63 while ((pmu_power_domain_st(pd) != pd_state) && (loop < PD_CTR_LOOP)) {
64 udelay(1);
65 loop++;
66 }
67
68 if (pmu_power_domain_st(pd) != pd_state) {
69 WARN("%s: %d, %d, error!\n", __func__, pd, pd_state);
70 ret = -EINVAL;
71 }
72
73 rockchip_pd_lock_rls();
74
75 return ret;
76 }
77
check_cpu_wfie(uint32_t cpu_id,uint32_t wfie_msk)78 static int check_cpu_wfie(uint32_t cpu_id, uint32_t wfie_msk)
79 {
80 uint32_t cluster_id, loop = 0;
81
82 if (cpu_id >= PLATFORM_CLUSTER0_CORE_COUNT) {
83 cluster_id = 1;
84 cpu_id -= PLATFORM_CLUSTER0_CORE_COUNT;
85 } else {
86 cluster_id = 0;
87 }
88
89 /*
90 * wfe/wfi tracking not possible, hopefully the host
91 * was successful in enabling wfe/wfi.
92 * We'll give a bit of additional time, like the kernel does.
93 */
94 if ((cluster_id && clstb_cpu_wfe < 0) ||
95 (!cluster_id && clstl_cpu_wfe < 0)) {
96 mdelay(1);
97 return 0;
98 }
99
100 if (cluster_id)
101 wfie_msk <<= (clstb_cpu_wfe + cpu_id);
102 else
103 wfie_msk <<= (clstl_cpu_wfe + cpu_id);
104
105 while (!(mmio_read_32(CHECK_CPU_WFIE_BASE) & wfie_msk) &&
106 (loop < CHK_CPU_LOOP)) {
107 udelay(1);
108 loop++;
109 }
110
111 if ((mmio_read_32(CHECK_CPU_WFIE_BASE) & wfie_msk) == 0) {
112 WARN("%s: %d, %d, %d, error!\n", __func__,
113 cluster_id, cpu_id, wfie_msk);
114 return -EINVAL;
115 }
116
117 return 0;
118 }
119
120 #endif /* PMU_COM_H */
121