fix(intel): allow kernel access to TSN TBU stream control registers

Added TSN_TBU_STREAM_CTRL_REG_3_TSN0/1/2 to ATF's secure range check
to permit setting the 31st bit from kernel space.

Change-Id:

fix(intel): allow kernel access to TSN TBU stream control registers

Added TSN_TBU_STREAM_CTRL_REG_3_TSN0/1/2 to ATF's secure range check
to permit setting the 31st bit from kernel space.

Change-Id: I74bd296c4c050fb61d4df5c1bd5b57449b3a13e3
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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Merge "feat(intel): move common functions to common lib files" into integration

feat(intel): move common functions to common lib files

This patch is used to move common functions that used across
files into commmon lib files to prevent multiple functions
declaration and share a

feat(intel): move common functions to common lib files

This patch is used to move common functions that used across
files into commmon lib files to prevent multiple functions
declaration and share among files.

Change-Id: I19d9727eac895e7bf597a66076a7b68755cbe0ef
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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fix(intel): fix socfpga_psci for cpu on off function

Fix for CPU ON / OFF Function calling from Linux Kernel.

Change-Id: Ie450acf7e537ed60ef4b2e8d785e62d94e52482f
Signed-off-by: Boon Khai Ng <boon.

fix(intel): fix socfpga_psci for cpu on off function

Fix for CPU ON / OFF Function calling from Linux Kernel.

Change-Id: Ie450acf7e537ed60ef4b2e8d785e62d94e52482f
Signed-off-by: Boon Khai Ng <boon.khai.ng@altera.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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Merge changes I3303ca9a,I682da2d3 into integration

* changes:
feat(intel): migrate RSU client to SiPSVC V3
fix(intel): support generic mailbox command in SiPSVC V3

Merge "fix(intel): support SMC 64bit return args in SiPSVC V3" into integration

Merge changes I23e51bf9,I0fa9adaf into integration

* changes:
fix(intel): verify data size in AES GCM and GCM-GHASH modes
fix(intel): update FCS AES method for GCM block modes

Merge "feat(intel): support IO96B ECC Error Injection via SMC call" into integration

feat(intel): migrate RSU client to SiPSVC V3

Migrate all the RSU related commands to SiPSVC V3
framework.

Change-Id: I3303ca9ad81e412cc9543e0d50c1d7ea64dcc1f6
Signed-off-by: Girisha Dengi <girisha.

feat(intel): migrate RSU client to SiPSVC V3

Migrate all the RSU related commands to SiPSVC V3
framework.

Change-Id: I3303ca9ad81e412cc9543e0d50c1d7ea64dcc1f6
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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fix(intel): support generic mailbox command in SiPSVC V3

Support generic mailbox command in the SiPSVC V3 framework
and add filter to avoid executing FCS related commands in
the generic mailbox form

fix(intel): support generic mailbox command in SiPSVC V3

Support generic mailbox command in the SiPSVC V3 framework
and add filter to avoid executing FCS related commands in
the generic mailbox format.

Change-Id: I682da2d37c68773ef34194abd6d49c52ddc5c26e
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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feat(intel): support IO96B ECC Error Injection via SMC call

Add SMC call for IO96B ECC error injection, write dummy data
to DDR and read back. This is required to do from ATF,because
the error injec

feat(intel): support IO96B ECC Error Injection via SMC call

Add SMC call for IO96B ECC error injection, write dummy data
to DDR and read back. This is required to do from ATF,because
the error injection from Linux kernel is causing inconsitent
behaviour and sometimes causing memory crash.

Change-Id: I62f9dca319ea6a7ddbdbb7cc2965a0a4e2d41ab6
Signed-off-by: Rabara, Niravkumar L <niravkumar.l.rabara@intel.com>
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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fix(intel): support SMC 64bit return args in SiPSVC V3

Update SiPSVC V3 framework to support 64bit SMC return
arguments and other miscellaneous debug prints.

Change-Id: I659a0aea8e24eb5876e69327e44

fix(intel): support SMC 64bit return args in SiPSVC V3

Update SiPSVC V3 framework to support 64bit SMC return
arguments and other miscellaneous debug prints.

Change-Id: I659a0aea8e24eb5876e69327e44a667d2a54c241
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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fix(intel): verify data size in AES GCM and GCM-GHASH modes

On the Agilex5 platform, in the FCS AES GCM and GCM-GHASH
modes enc/dec data size should be 0 or multiple of 16bytes.

Change-Id: I23e51bf

fix(intel): verify data size in AES GCM and GCM-GHASH modes

On the Agilex5 platform, in the FCS AES GCM and GCM-GHASH
modes enc/dec data size should be 0 or multiple of 16bytes.

Change-Id: I23e51bf942771e74d16f8a87fbfdbf36ef3c3893
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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fix(intel): update FCS AES method for GCM block modes

On the Agilex5 platform, AES enc/dec with GCM and GCM-GHASH
modes, the source and destination size should be in multiples
of 16 bytes. For other

fix(intel): update FCS AES method for GCM block modes

On the Agilex5 platform, AES enc/dec with GCM and GCM-GHASH
modes, the source and destination size should be in multiples
of 16 bytes. For other platforms and other modes, it should
be in multiples of 32 bytes.

Change-Id: I0fa9adafb5d7fc4c794a4acb9339cf8259df0c78
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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feat(intel): update CPUECTLR_EL1 to boost ethernet performance

This patch is the workaround for Agilex5 Ethernet for performance
boost.

Change-Id: I702f0cb0beff8b3ea119205ec41dd4e825e9126b
Signed-o

feat(intel): update CPUECTLR_EL1 to boost ethernet performance

This patch is the workaround for Agilex5 Ethernet for performance
boost.

Change-Id: I702f0cb0beff8b3ea119205ec41dd4e825e9126b
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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Merge "fix(intel): update ssbl naming conventions" into integration

Merge changes I1dfb95aa,I9eb61c48 into integration

* changes:
feat(intel): support FCS commands with SiPSVC V3 framework
feat(intel): implementation of SiPSVC-V3 protocol framework

fix(intel): update ssbl naming conventions

Update RSU SSBL name query in line with other bootloaders
and use secure string functions.

Change-Id: I8ae6b80eb74e91c6a82e59986cba137cf5ef6977
Signed-off

fix(intel): update ssbl naming conventions

Update RSU SSBL name query in line with other bootloaders
and use secure string functions.

Change-Id: I8ae6b80eb74e91c6a82e59986cba137cf5ef6977
Signed-off-by: Mahesh Rao <mahesh.rao@intel.com>

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feat(intel): support FCS commands with SiPSVC V3 framework

Support all the FCS(FPGA Crypto Service) commands with
SiPSVC verson3 framework.

Change-Id: I1dfb95aaddf7111325ce0082eb26f7a201001141
Sign

feat(intel): support FCS commands with SiPSVC V3 framework

Support all the FCS(FPGA Crypto Service) commands with
SiPSVC verson3 framework.

Change-Id: I1dfb95aaddf7111325ce0082eb26f7a201001141
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@altera.com>

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feat(intel): implementation of SiPSVC-V3 protocol framework

- Develop SiPSVC-V3 framework to support async/yielding SMC calls.
- Add support for multi clients with multiple jobs running together.
-

feat(intel): implementation of SiPSVC-V3 protocol framework

- Develop SiPSVC-V3 framework to support async/yielding SMC calls.
- Add support for multi clients with multiple jobs running together.
- Add support for SDM doorbell interrupt handling.
- Keep the framework backward compatible with V1 clients.
- Enable the framework on all the platform Agilex7, Agilex5, N5X,
and Stratix10.

Change-Id: I9eb61c48be89867b4227e084493bfcf67cbe7924
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@altera.com>

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feat(intel): provide atf build version via smc call

This patch provides ATF build version via SMC call
on Agilex7, Agilex5, Stratix10 and N5X platforms.

Change-Id: I61af83433fe61f85987f38ffc86380a4

feat(intel): provide atf build version via smc call

This patch provides ATF build version via SMC call
on Agilex7, Agilex5, Stratix10 and N5X platforms.

Change-Id: I61af83433fe61f85987f38ffc86380a41cdb5289
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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Merge "feat(intel): add FDT support for Altera products" into integration