1/* 2 * Copyright (c) 2021-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a710.h> 11#include <cpu_macros.S> 12#include <dsu_macros.S> 13#include <plat_macros.S> 14#include "wa_cve_2022_23960_bhb_vector.S" 15 16/* Hardware handled coherency */ 17#if HW_ASSISTED_COHERENCY == 0 18#error "Cortex A710 must be compiled with HW_ASSISTED_COHERENCY enabled" 19#endif 20 21/* 64-bit only core */ 22#if CTX_INCLUDE_AARCH32_REGS == 1 23#error "Cortex A710 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 24#endif 25 26.global check_erratum_cortex_a710_3701772 27 28#if WORKAROUND_CVE_2022_23960 29 wa_cve_2022_23960_bhb_vector_table CORTEX_A710_BHB_LOOP_COUNT, cortex_a710 30#endif /* WORKAROUND_CVE_2022_23960 */ 31 32cpu_reset_prologue cortex_a710 33 34workaround_reset_start cortex_a710, ERRATUM(1987031), ERRATA_A710_1987031 35 ldr x0,=0x6 36 msr S3_6_c15_c8_0,x0 37 ldr x0,=0xF3A08002 38 msr S3_6_c15_c8_2,x0 39 ldr x0,=0xFFF0F7FE 40 msr S3_6_c15_c8_3,x0 41 ldr x0,=0x40000001003ff 42 msr S3_6_c15_c8_1,x0 43 ldr x0,=0x7 44 msr S3_6_c15_c8_0,x0 45 ldr x0,=0xBF200000 46 msr S3_6_c15_c8_2,x0 47 ldr x0,=0xFFEF0000 48 msr S3_6_c15_c8_3,x0 49 ldr x0,=0x40000001003f3 50 msr S3_6_c15_c8_1,x0 51workaround_reset_end cortex_a710, ERRATUM(1987031) 52 53check_erratum_ls cortex_a710, ERRATUM(1987031), CPU_REV(2, 0) 54 55workaround_runtime_start cortex_a710, ERRATUM(2008768), ERRATA_A710_2008768 56 /* Stash ERRSELR_EL1 in x2 */ 57 mrs x2, ERRSELR_EL1 58 59 /* Select error record 0 and clear ED bit */ 60 msr ERRSELR_EL1, xzr 61 mrs x1, ERXCTLR_EL1 62 bfi x1, xzr, #ERXCTLR_ED_SHIFT, #1 63 msr ERXCTLR_EL1, x1 64 65 /* Select error record 1 and clear ED bit */ 66 mov x0, #1 67 msr ERRSELR_EL1, x0 68 mrs x1, ERXCTLR_EL1 69 bfi x1, xzr, #ERXCTLR_ED_SHIFT, #1 70 msr ERXCTLR_EL1, x1 71 72 /* Restore ERRSELR_EL1 from x2 */ 73 msr ERRSELR_EL1, x2 74workaround_runtime_end cortex_a710, ERRATUM(2008768), NO_ISB 75 76check_erratum_ls cortex_a710, ERRATUM(2008768), CPU_REV(2, 0) 77 78workaround_reset_start cortex_a710, ERRATUM(2017096), ERRATA_A710_2017096 79 sysreg_bit_set CORTEX_A710_CPUECTLR_EL1, CORTEX_A710_CPUECTLR_EL1_PFSTIDIS_BIT 80workaround_reset_end cortex_a710, ERRATUM(2017096) 81 82check_erratum_ls cortex_a710, ERRATUM(2017096), CPU_REV(2, 0) 83 84workaround_reset_start cortex_a710, ERRATUM(2055002), ERRATA_A710_2055002 85 sysreg_bit_set CORTEX_A710_CPUACTLR_EL1, CORTEX_A710_CPUACTLR_EL1_BIT_46 86workaround_reset_end cortex_a710, ERRATUM(2055002) 87 88check_erratum_range cortex_a710, ERRATUM(2055002), CPU_REV(1, 0), CPU_REV(2, 0) 89 90workaround_reset_start cortex_a710, ERRATUM(2058056), ERRATA_A710_2058056 91 sysreg_bitfield_insert CORTEX_A710_CPUECTLR2_EL1, CORTEX_A710_CPUECTLR2_EL1_PF_MODE_CNSRV, \ 92 CPUECTLR2_EL1_PF_MODE_LSB, CPUECTLR2_EL1_PF_MODE_WIDTH 93workaround_reset_end cortex_a710, ERRATUM(2058056) 94 95check_erratum_ls cortex_a710, ERRATUM(2058056), CPU_REV(2, 1) 96 97workaround_reset_start cortex_a710, ERRATUM(2081180), ERRATA_A710_2081180 98 ldr x0,=0x3 99 msr S3_6_c15_c8_0,x0 100 ldr x0,=0xF3A08002 101 msr S3_6_c15_c8_2,x0 102 ldr x0,=0xFFF0F7FE 103 msr S3_6_c15_c8_3,x0 104 ldr x0,=0x10002001003FF 105 msr S3_6_c15_c8_1,x0 106 ldr x0,=0x4 107 msr S3_6_c15_c8_0,x0 108 ldr x0,=0xBF200000 109 msr S3_6_c15_c8_2,x0 110 ldr x0,=0xFFEF0000 111 msr S3_6_c15_c8_3,x0 112 ldr x0,=0x10002001003F3 113 msr S3_6_c15_c8_1,x0 114workaround_reset_end cortex_a710, ERRATUM(2081180) 115 116check_erratum_ls cortex_a710, ERRATUM(2081180), CPU_REV(2, 0) 117 118workaround_reset_start cortex_a710, ERRATUM(2083908), ERRATA_A710_2083908 119 sysreg_bit_set CORTEX_A710_CPUACTLR5_EL1, CORTEX_A710_CPUACTLR5_EL1_BIT_13 120workaround_reset_end cortex_a710, ERRATUM(2083908) 121 122check_erratum_range cortex_a710, ERRATUM(2083908), CPU_REV(2, 0), CPU_REV(2, 0) 123 124workaround_reset_start cortex_a710, ERRATUM(2136059), ERRATA_A710_2136059 125 sysreg_bit_set CORTEX_A710_CPUACTLR5_EL1, CORTEX_A710_CPUACTLR5_EL1_BIT_44 126workaround_reset_end cortex_a710, ERRATUM(2136059) 127 128check_erratum_ls cortex_a710, ERRATUM(2136059), CPU_REV(2, 0) 129 130workaround_reset_start cortex_a710, ERRATUM(2147715), ERRATA_A710_2147715 131 sysreg_bit_set CORTEX_A710_CPUACTLR_EL1, CORTEX_A710_CPUACTLR_EL1_BIT_22 132workaround_reset_end cortex_a710, ERRATUM(2147715) 133 134check_erratum_range cortex_a710, ERRATUM(2147715), CPU_REV(2, 0), CPU_REV(2, 0) 135 136workaround_reset_start cortex_a710, ERRATUM(2216384), ERRATA_A710_2216384 137 sysreg_bit_set CORTEX_A710_CPUACTLR5_EL1, CORTEX_A710_CPUACTLR5_EL1_BIT_17 138 139 ldr x0,=0x5 140 msr CORTEX_A710_CPUPSELR_EL3, x0 141 ldr x0,=0x10F600E000 142 msr CORTEX_A710_CPUPOR_EL3, x0 143 ldr x0,=0x10FF80E000 144 msr CORTEX_A710_CPUPMR_EL3, x0 145 ldr x0,=0x80000000003FF 146 msr CORTEX_A710_CPUPCR_EL3, x0 147workaround_reset_end cortex_a710, ERRATUM(2216384) 148 149check_erratum_ls cortex_a710, ERRATUM(2216384), CPU_REV(2, 0) 150 151workaround_reset_start cortex_a710, ERRATUM(2267065), ERRATA_A710_2267065 152 sysreg_bit_set CORTEX_A710_CPUACTLR_EL1, CORTEX_A710_CPUACTLR_EL1_BIT_22 153workaround_reset_end cortex_a710, ERRATUM(2267065) 154 155check_erratum_ls cortex_a710, ERRATUM(2267065), CPU_REV(2, 0) 156 157workaround_reset_start cortex_a710, ERRATUM(2282622), ERRATA_A710_2282622 158 sysreg_bit_set CORTEX_A710_CPUACTLR2_EL1, BIT(0) 159workaround_reset_end cortex_a710, ERRATUM(2282622) 160 161check_erratum_ls cortex_a710, ERRATUM(2282622), CPU_REV(2, 1) 162 163.global erratum_cortex_a710_2291219_wa 164workaround_runtime_start cortex_a710, ERRATUM(2291219), ERRATA_A710_2291219 165 /* Set/unset bit 36 in ACTLR2_EL1. The first call will set it, applying 166 * the workaround. Second call clears it to undo it. */ 167 sysreg_bit_toggle CORTEX_A710_CPUACTLR2_EL1, CORTEX_A710_CPUACTLR2_EL1_BIT_36 168workaround_runtime_end cortex_a710, ERRATUM(2291219), NO_ISB 169 170check_erratum_ls cortex_a710, ERRATUM(2291219), CPU_REV(2, 0) 171 172workaround_reset_start cortex_a710, ERRATUM(2313941), ERRATA_DSU_2313941 173 errata_dsu_2313941_wa_impl 174workaround_reset_end cortex_a710, ERRATUM(2313941) 175 176check_erratum_custom_start cortex_a710, ERRATUM(2313941) 177 check_errata_dsu_2313941_impl 178 ret 179check_erratum_custom_end cortex_a710, ERRATUM(2313941) 180 181workaround_reset_start cortex_a710, ERRATUM(2371105), ERRATA_A710_2371105 182 /* Set bit 40 in CPUACTLR2_EL1 */ 183 sysreg_bit_set CORTEX_A710_CPUACTLR2_EL1, CORTEX_A710_CPUACTLR2_EL1_BIT_40 184workaround_reset_end cortex_a710, ERRATUM(2371105) 185 186check_erratum_ls cortex_a710, ERRATUM(2371105), CPU_REV(2, 0) 187 188workaround_reset_start cortex_a710, ERRATUM(2742423), ERRATA_A710_2742423 189 /* Set CPUACTLR5_EL1[56:55] to 2'b01 */ 190 sysreg_bit_set CORTEX_A710_CPUACTLR5_EL1, BIT(55) 191 sysreg_bit_clear CORTEX_A710_CPUACTLR5_EL1, BIT(56) 192workaround_reset_end cortex_a710, ERRATUM(2742423) 193 194check_erratum_ls cortex_a710, ERRATUM(2742423), CPU_REV(2, 1) 195 196workaround_runtime_start cortex_a710, ERRATUM(2768515), ERRATA_A710_2768515 197 /* dsb before isb of power down sequence */ 198 dsb sy 199workaround_runtime_end cortex_a710, ERRATUM(2768515), NO_ISB 200 201check_erratum_ls cortex_a710, ERRATUM(2768515), CPU_REV(2, 1) 202 203workaround_reset_start cortex_a710, ERRATUM(2778471), ERRATA_A710_2778471 204 sysreg_bit_set CORTEX_A710_CPUACTLR3_EL1, BIT(47) 205workaround_reset_end cortex_a710, ERRATUM(2778471) 206 207check_erratum_ls cortex_a710, ERRATUM(2778471), CPU_REV(2, 1) 208 209add_erratum_entry cortex_a710, ERRATUM(3701772), ERRATA_A710_3701772 210 211check_erratum_ls cortex_a710, ERRATUM(3701772), CPU_REV(2, 1) 212 213workaround_reset_start cortex_a710, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 214#if IMAGE_BL31 215 /* 216 * The Cortex-A710 generic vectors are overridden to apply errata 217 * mitigation on exception entry from lower ELs. 218 */ 219 override_vector_table wa_cve_vbar_cortex_a710 220#endif /* IMAGE_BL31 */ 221workaround_reset_end cortex_a710, CVE(2022, 23960) 222 223check_erratum_chosen cortex_a710, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 224 225/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 226workaround_reset_start cortex_a710, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 227 sysreg_bit_set CORTEX_A710_CPUECTLR_EL1, BIT(46) 228workaround_reset_end cortex_a710, CVE(2024, 5660) 229 230check_erratum_ls cortex_a710, CVE(2024, 5660), CPU_REV(2, 1) 231 232 /* ---------------------------------------------------- 233 * HW will do the cache maintenance while powering down 234 * ---------------------------------------------------- 235 */ 236func cortex_a710_core_pwr_dwn 237 apply_erratum cortex_a710, ERRATUM(2008768), ERRATA_A710_2008768, NO_GET_CPU_REV 238 apply_erratum cortex_a710, ERRATUM(2291219), ERRATA_A710_2291219, NO_GET_CPU_REV 239 240 /* --------------------------------------------------- 241 * Enable CPU power down bit in power control register 242 * --------------------------------------------------- 243 */ 244 sysreg_bit_set CORTEX_A710_CPUPWRCTLR_EL1, CORTEX_A710_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 245 apply_erratum cortex_a710, ERRATUM(2768515), ERRATA_A710_2768515, NO_GET_CPU_REV 246 isb 247 ret 248endfunc cortex_a710_core_pwr_dwn 249 250cpu_reset_func_start cortex_a710 251 /* Disable speculative loads */ 252 msr SSBS, xzr 253 enable_mpmm 254cpu_reset_func_end cortex_a710 255 256 /* --------------------------------------------- 257 * This function provides Cortex-A710 specific 258 * register information for crash reporting. 259 * It needs to return with x6 pointing to 260 * a list of register names in ascii and 261 * x8 - x15 having values of registers to be 262 * reported. 263 * --------------------------------------------- 264 */ 265.section .rodata.cortex_a710_regs, "aS" 266cortex_a710_regs: /* The ascii list of register names to be reported */ 267 .asciz "cpuectlr_el1", "" 268 269func cortex_a710_cpu_reg_dump 270 adr x6, cortex_a710_regs 271 mrs x8, CORTEX_A710_CPUECTLR_EL1 272 ret 273endfunc cortex_a710_cpu_reg_dump 274 275declare_cpu_ops cortex_a710, CORTEX_A710_MIDR, \ 276 cortex_a710_reset_func, \ 277 cortex_a710_core_pwr_dwn 278