1 /* 2 * Copyright (c) 2019-2023, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. 4 * Copyright (c) 2024-2025, Altera Corporation. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #include <assert.h> 10 #include <common/debug.h> 11 #include <common/runtime_svc.h> 12 #include <lib/mmio.h> 13 #include <tools_share/uuid.h> 14 15 #include "socfpga_fcs.h" 16 #include "socfpga_mailbox.h" 17 #include "socfpga_plat_def.h" 18 #include "socfpga_reset_manager.h" 19 #include "socfpga_sip_svc.h" 20 #include "socfpga_system_manager.h" 21 22 /* Total buffer the driver can hold */ 23 #define FPGA_CONFIG_BUFFER_SIZE 4 24 25 static config_type request_type = NO_REQUEST; 26 static int current_block, current_buffer; 27 static int read_block, max_blocks; 28 static uint32_t send_id, rcv_id; 29 static uint32_t bytes_per_block, blocks_submitted; 30 static bool bridge_disable; 31 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 32 static uint32_t g_remapper_bypass; 33 #endif 34 35 /* RSU static variables */ 36 static uint32_t rsu_dcmf_ver[4] = {0}; 37 static uint16_t rsu_dcmf_stat[4] = {0}; 38 static uint32_t rsu_max_retry; 39 40 /* SiP Service UUID */ 41 DEFINE_SVC_UUID2(intl_svc_uid, 42 0xa85273b0, 0xe85a, 0x4862, 0xa6, 0x2a, 43 0xfa, 0x88, 0x88, 0x17, 0x68, 0x81); 44 45 static uint64_t socfpga_sip_handler(uint32_t smc_fid, 46 uint64_t x1, 47 uint64_t x2, 48 uint64_t x3, 49 uint64_t x4, 50 void *cookie, 51 void *handle, 52 uint64_t flags) 53 { 54 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); 55 SMC_RET1(handle, SMC_UNK); 56 } 57 58 struct fpga_config_info fpga_config_buffers[FPGA_CONFIG_BUFFER_SIZE]; 59 60 static int intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer) 61 { 62 uint32_t args[3]; 63 64 while (max_blocks > 0 && buffer->size > buffer->size_written) { 65 args[0] = (1<<8); 66 args[1] = buffer->addr + buffer->size_written; 67 if (buffer->size - buffer->size_written <= bytes_per_block) { 68 args[2] = buffer->size - buffer->size_written; 69 current_buffer++; 70 current_buffer %= FPGA_CONFIG_BUFFER_SIZE; 71 } else { 72 args[2] = bytes_per_block; 73 } 74 75 buffer->size_written += args[2]; 76 mailbox_send_cmd_async(&send_id, MBOX_RECONFIG_DATA, args, 77 3U, CMD_INDIRECT); 78 79 buffer->subblocks_sent++; 80 max_blocks--; 81 } 82 83 return !max_blocks; 84 } 85 86 static int intel_fpga_sdm_write_all(void) 87 { 88 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 89 if (intel_fpga_sdm_write_buffer( 90 &fpga_config_buffers[current_buffer])) { 91 break; 92 } 93 } 94 return 0; 95 } 96 97 static uint32_t intel_mailbox_fpga_config_isdone(uint32_t *err_states) 98 { 99 uint32_t ret; 100 101 if (err_states == NULL) 102 return INTEL_SIP_SMC_STATUS_REJECTED; 103 104 switch (request_type) { 105 case RECONFIGURATION: 106 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, 107 true, err_states); 108 break; 109 case BITSTREAM_AUTH: 110 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, 111 false, err_states); 112 break; 113 default: 114 ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS, 115 false, err_states); 116 break; 117 } 118 119 if (ret != 0U) { 120 if (ret == MBOX_CFGSTAT_STATE_CONFIG) { 121 return INTEL_SIP_SMC_STATUS_BUSY; 122 } else { 123 request_type = NO_REQUEST; 124 return INTEL_SIP_SMC_STATUS_ERROR; 125 } 126 } 127 128 if (bridge_disable != 0U) { 129 socfpga_bridges_enable(~0); /* Enable bridge */ 130 bridge_disable = false; 131 } 132 request_type = NO_REQUEST; 133 134 return INTEL_SIP_SMC_STATUS_OK; 135 } 136 137 static int mark_last_buffer_xfer_completed(uint32_t *buffer_addr_completed) 138 { 139 int i; 140 141 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 142 if (fpga_config_buffers[i].block_number == current_block) { 143 fpga_config_buffers[i].subblocks_sent--; 144 if (fpga_config_buffers[i].subblocks_sent == 0 145 && fpga_config_buffers[i].size <= 146 fpga_config_buffers[i].size_written) { 147 fpga_config_buffers[i].write_requested = 0; 148 current_block++; 149 *buffer_addr_completed = 150 fpga_config_buffers[i].addr; 151 return 0; 152 } 153 } 154 } 155 156 return -1; 157 } 158 159 static int intel_fpga_config_completed_write(uint32_t *completed_addr, 160 uint32_t *count, uint32_t *job_id) 161 { 162 uint32_t resp[5]; 163 unsigned int resp_len = ARRAY_SIZE(resp); 164 int status = INTEL_SIP_SMC_STATUS_OK; 165 int all_completed = 1; 166 *count = 0; 167 168 while (*count < 3) { 169 170 status = mailbox_read_response(job_id, 171 resp, &resp_len); 172 173 if (status < 0) { 174 break; 175 } 176 177 max_blocks++; 178 179 if (mark_last_buffer_xfer_completed( 180 &completed_addr[*count]) == 0) { 181 *count = *count + 1; 182 } else { 183 break; 184 } 185 } 186 187 if (*count <= 0) { 188 if (status != MBOX_NO_RESPONSE && 189 status != MBOX_TIMEOUT && resp_len != 0) { 190 mailbox_clear_response(); 191 request_type = NO_REQUEST; 192 return INTEL_SIP_SMC_STATUS_ERROR; 193 } 194 195 *count = 0; 196 } 197 198 intel_fpga_sdm_write_all(); 199 200 if (*count > 0) { 201 status = INTEL_SIP_SMC_STATUS_OK; 202 } else if (*count == 0) { 203 status = INTEL_SIP_SMC_STATUS_BUSY; 204 } 205 206 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 207 if (fpga_config_buffers[i].write_requested != 0) { 208 all_completed = 0; 209 break; 210 } 211 } 212 213 if (all_completed == 1) { 214 return INTEL_SIP_SMC_STATUS_OK; 215 } 216 217 return status; 218 } 219 220 static int intel_fpga_config_start(uint32_t flag) 221 { 222 uint32_t argument = 0x1; 223 uint32_t response[3]; 224 int status = 0; 225 unsigned int size = 0; 226 unsigned int resp_len = ARRAY_SIZE(response); 227 228 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 229 /* 230 * To trigger isolation 231 * FPGA configuration complete signal should be de-asserted 232 */ 233 INFO("SOCFPGA: Request SDM to trigger isolation\n"); 234 status = mailbox_send_fpga_config_comp(); 235 236 if (status < 0) { 237 INFO("SOCFPGA: Isolation for FPGA configuration complete is not executed\n"); 238 } 239 #endif 240 241 request_type = RECONFIGURATION; 242 243 if (!CONFIG_TEST_FLAG(flag, PARTIAL_CONFIG)) { 244 bridge_disable = true; 245 } 246 247 if (CONFIG_TEST_FLAG(flag, AUTHENTICATION)) { 248 size = 1; 249 bridge_disable = false; 250 request_type = BITSTREAM_AUTH; 251 } 252 253 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 254 intel_smmu_hps_remapper_init(0U); 255 #endif 256 257 mailbox_clear_response(); 258 259 mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_CANCEL, NULL, 0U, 260 CMD_CASUAL, NULL, NULL); 261 262 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_RECONFIG, &argument, size, 263 CMD_CASUAL, response, &resp_len); 264 265 if (status < 0) { 266 bridge_disable = false; 267 request_type = NO_REQUEST; 268 return INTEL_SIP_SMC_STATUS_ERROR; 269 } 270 271 max_blocks = response[0]; 272 bytes_per_block = response[1]; 273 274 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 275 fpga_config_buffers[i].size = 0; 276 fpga_config_buffers[i].size_written = 0; 277 fpga_config_buffers[i].addr = 0; 278 fpga_config_buffers[i].write_requested = 0; 279 fpga_config_buffers[i].block_number = 0; 280 fpga_config_buffers[i].subblocks_sent = 0; 281 } 282 283 blocks_submitted = 0; 284 current_block = 0; 285 read_block = 0; 286 current_buffer = 0; 287 288 /* Disable bridge on full reconfiguration */ 289 if (bridge_disable) { 290 socfpga_bridges_disable(~0); 291 } 292 293 return INTEL_SIP_SMC_STATUS_OK; 294 } 295 296 static bool is_fpga_config_buffer_full(void) 297 { 298 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 299 if (!fpga_config_buffers[i].write_requested) { 300 return false; 301 } 302 } 303 return true; 304 } 305 306 bool is_address_in_ddr_range(uint64_t addr, uint64_t size) 307 { 308 uint128_t dram_max_sz = (uint128_t)DRAM_BASE + (uint128_t)DRAM_SIZE; 309 uint128_t dram_region_end = (uint128_t)addr + (uint128_t)size; 310 311 if (!addr && !size) { 312 return true; 313 } 314 if (size > (UINT64_MAX - addr)) { 315 return false; 316 } 317 if (addr < BL31_LIMIT) { 318 return false; 319 } 320 if (dram_region_end > dram_max_sz) { 321 return false; 322 } 323 324 return true; 325 } 326 327 static uint32_t intel_fpga_config_write(uint64_t mem, uint64_t size) 328 { 329 int i; 330 331 intel_fpga_sdm_write_all(); 332 333 if (!is_address_in_ddr_range(mem, size) || 334 is_fpga_config_buffer_full()) { 335 return INTEL_SIP_SMC_STATUS_REJECTED; 336 } 337 338 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 339 intel_smmu_hps_remapper_init(&mem); 340 #endif 341 342 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 343 int j = (i + current_buffer) % FPGA_CONFIG_BUFFER_SIZE; 344 345 if (!fpga_config_buffers[j].write_requested) { 346 fpga_config_buffers[j].addr = mem; 347 fpga_config_buffers[j].size = size; 348 fpga_config_buffers[j].size_written = 0; 349 fpga_config_buffers[j].write_requested = 1; 350 fpga_config_buffers[j].block_number = 351 blocks_submitted++; 352 fpga_config_buffers[j].subblocks_sent = 0; 353 break; 354 } 355 } 356 357 if (is_fpga_config_buffer_full()) { 358 return INTEL_SIP_SMC_STATUS_BUSY; 359 } 360 361 return INTEL_SIP_SMC_STATUS_OK; 362 } 363 364 static int is_out_of_sec_range(uint64_t reg_addr) 365 { 366 #if DEBUG 367 return 0; 368 #endif 369 370 #if PLATFORM_MODEL != PLAT_SOCFPGA_AGILEX5 371 switch (reg_addr) { 372 case(0xF8011100): /* ECCCTRL1 */ 373 case(0xF8011104): /* ECCCTRL2 */ 374 case(0xF8011110): /* ERRINTEN */ 375 case(0xF8011114): /* ERRINTENS */ 376 case(0xF8011118): /* ERRINTENR */ 377 case(0xF801111C): /* INTMODE */ 378 case(0xF8011120): /* INTSTAT */ 379 case(0xF8011124): /* DIAGINTTEST */ 380 case(0xF801112C): /* DERRADDRA */ 381 case(0xFA000000): /* SMMU SCR0 */ 382 case(0xFA000004): /* SMMU SCR1 */ 383 case(0xFA000400): /* SMMU NSCR0 */ 384 case(0xFA004000): /* SMMU SSD0_REG */ 385 case(0xFA000820): /* SMMU SMR8 */ 386 case(0xFA000c20): /* SMMU SCR8 */ 387 case(0xFA028000): /* SMMU CB8_SCTRL */ 388 case(0xFA001020): /* SMMU CBAR8 */ 389 case(0xFA028030): /* SMMU TCR_LPAE */ 390 case(0xFA028020): /* SMMU CB8_TTBR0_LOW */ 391 case(0xFA028024): /* SMMU CB8_PRRR_HIGH */ 392 case(0xFA028038): /* SMMU CB8_PRRR_MIR0 */ 393 case(0xFA02803C): /* SMMU CB8_PRRR_MIR1 */ 394 case(0xFA028010): /* SMMU_CB8)TCR2 */ 395 case(0xFFD080A4): /* SDM SMMU STREAM ID REG */ 396 case(0xFA001820): /* SMMU_CBA2R8 */ 397 case(0xFA000074): /* SMMU_STLBGSTATUS */ 398 case(0xFA0287F4): /* SMMU_CB8_TLBSTATUS */ 399 case(0xFA000060): /* SMMU_STLBIALL */ 400 case(0xFA000070): /* SMMU_STLBGSYNC */ 401 case(0xFA028618): /* CB8_TLBALL */ 402 case(0xFA0287F0): /* CB8_TLBSYNC */ 403 case(0xFFD12028): /* SDMMCGRP_CTRL */ 404 case(0xFFD12044): /* EMAC0 */ 405 case(0xFFD12048): /* EMAC1 */ 406 case(0xFFD1204C): /* EMAC2 */ 407 case(0xFFD12090): /* ECC_INT_MASK_VALUE */ 408 case(0xFFD12094): /* ECC_INT_MASK_SET */ 409 case(0xFFD12098): /* ECC_INT_MASK_CLEAR */ 410 case(0xFFD1209C): /* ECC_INTSTATUS_SERR */ 411 case(0xFFD120A0): /* ECC_INTSTATUS_DERR */ 412 case(0xFFD120C0): /* NOC_TIMEOUT */ 413 case(0xFFD120C4): /* NOC_IDLEREQ_SET */ 414 case(0xFFD120C8): /* NOC_IDLEREQ_CLR */ 415 case(0xFFD120D0): /* NOC_IDLEACK */ 416 case(0xFFD120D4): /* NOC_IDLESTATUS */ 417 case(0xFFD12200): /* BOOT_SCRATCH_COLD0 */ 418 case(0xFFD12204): /* BOOT_SCRATCH_COLD1 */ 419 case(0xFFD12220): /* BOOT_SCRATCH_COLD8 */ 420 case(0xFFD12224): /* BOOT_SCRATCH_COLD9 */ 421 return 0; 422 #else 423 switch (reg_addr) { 424 425 case(0xF8011104): /* ECCCTRL2 */ 426 case(0xFFD12028): /* SDMMCGRP_CTRL */ 427 case(0xFFD120C4): /* NOC_IDLEREQ_SET */ 428 case(0xFFD120C8): /* NOC_IDLEREQ_CLR */ 429 case(0xFFD120D0): /* NOC_IDLEACK */ 430 431 432 case(SOCFPGA_MEMCTRL(ECCCTRL1)): /* ECCCTRL1 */ 433 case(SOCFPGA_MEMCTRL(ERRINTEN)): /* ERRINTEN */ 434 case(SOCFPGA_MEMCTRL(ERRINTENS)): /* ERRINTENS */ 435 case(SOCFPGA_MEMCTRL(ERRINTENR)): /* ERRINTENR */ 436 case(SOCFPGA_MEMCTRL(INTMODE)): /* INTMODE */ 437 case(SOCFPGA_MEMCTRL(INTSTAT)): /* INTSTAT */ 438 case(SOCFPGA_MEMCTRL(DIAGINTTEST)): /* DIAGINTTEST */ 439 case(SOCFPGA_MEMCTRL(DERRADDRA)): /* DERRADDRA */ 440 441 case(SOCFPGA_ECC_QSPI(INITSTAT)): /* ECC_QSPI_INITSTAT */ 442 case(SOCFPGA_SYSMGR(EMAC_0)): /* EMAC0 */ 443 case(SOCFPGA_SYSMGR(EMAC_1)): /* EMAC1 */ 444 case(SOCFPGA_SYSMGR(EMAC_2)): /* EMAC2 */ 445 case(SOCFPGA_SYSMGR(ECC_INTMASK_VALUE)): /* ECC_INT_MASK_VALUE */ 446 case(SOCFPGA_SYSMGR(ECC_INTMASK_SET)): /* ECC_INT_MASK_SET */ 447 case(SOCFPGA_SYSMGR(ECC_INTMASK_CLR)): /* ECC_INT_MASK_CLEAR */ 448 case(SOCFPGA_SYSMGR(ECC_INTMASK_SERR)): /* ECC_INTSTATUS_SERR */ 449 case(SOCFPGA_SYSMGR(ECC_INTMASK_DERR)): /* ECC_INTSTATUS_DERR */ 450 case(SOCFPGA_SYSMGR(NOC_TIMEOUT)): /* NOC_TIMEOUT */ 451 case(SOCFPGA_SYSMGR(NOC_IDLESTATUS)): /* NOC_IDLESTATUS */ 452 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_0)): /* BOOT_SCRATCH_COLD0 */ 453 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_1)): /* BOOT_SCRATCH_COLD1 */ 454 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_8)): /* BOOT_SCRATCH_COLD8 */ 455 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_9)): /* BOOT_SCRATCH_COLD9 */ 456 #endif 457 case(SOCFPGA_ECC_QSPI(CTRL)): /* ECC_QSPI_CTRL */ 458 case(SOCFPGA_ECC_QSPI(ERRINTEN)): /* ECC_QSPI_ERRINTEN */ 459 case(SOCFPGA_ECC_QSPI(ERRINTENS)): /* ECC_QSPI_ERRINTENS */ 460 case(SOCFPGA_ECC_QSPI(ERRINTENR)): /* ECC_QSPI_ERRINTENR */ 461 case(SOCFPGA_ECC_QSPI(INTMODE)): /* ECC_QSPI_INTMODE */ 462 case(SOCFPGA_ECC_QSPI(ECC_ACCCTRL)): /* ECC_QSPI_ECC_ACCCTRL */ 463 case(SOCFPGA_ECC_QSPI(ECC_STARTACC)): /* ECC_QSPI_ECC_STARTACC */ 464 case(SOCFPGA_ECC_QSPI(ECC_WDCTRL)): /* ECC_QSPI_ECC_WDCTRL */ 465 case(SOCFPGA_ECC_QSPI(INTSTAT)): /* ECC_QSPI_INTSTAT */ 466 case(SOCFPGA_ECC_QSPI(INTTEST)): /* ECC_QSPI_INTMODE */ 467 return 0; 468 469 default: 470 break; 471 } 472 473 return -1; 474 } 475 476 /* Secure register access */ 477 uint32_t intel_secure_reg_read(uint64_t reg_addr, uint32_t *retval) 478 { 479 if (is_out_of_sec_range(reg_addr)) { 480 return INTEL_SIP_SMC_STATUS_ERROR; 481 } 482 483 *retval = mmio_read_32(reg_addr); 484 485 return INTEL_SIP_SMC_STATUS_OK; 486 } 487 488 uint32_t intel_secure_reg_write(uint64_t reg_addr, uint32_t val, 489 uint32_t *retval) 490 { 491 if (is_out_of_sec_range(reg_addr)) { 492 return INTEL_SIP_SMC_STATUS_ERROR; 493 } 494 495 switch (reg_addr) { 496 case(SOCFPGA_ECC_QSPI(INTSTAT)): /* ECC_QSPI_INTSTAT */ 497 case(SOCFPGA_ECC_QSPI(INTTEST)): /* ECC_QSPI_INTMODE */ 498 mmio_write_16(reg_addr, val); 499 break; 500 default: 501 mmio_write_32(reg_addr, val); 502 break; 503 } 504 505 return intel_secure_reg_read(reg_addr, retval); 506 } 507 508 uint32_t intel_secure_reg_update(uint64_t reg_addr, uint32_t mask, 509 uint32_t val, uint32_t *retval) 510 { 511 if (!intel_secure_reg_read(reg_addr, retval)) { 512 *retval &= ~mask; 513 *retval |= val & mask; 514 return intel_secure_reg_write(reg_addr, *retval, retval); 515 } 516 517 return INTEL_SIP_SMC_STATUS_ERROR; 518 } 519 520 /* Intel Remote System Update (RSU) services */ 521 uint64_t intel_rsu_update_address; 522 523 static uint32_t intel_rsu_status(uint64_t *respbuf, unsigned int respbuf_sz) 524 { 525 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) { 526 return INTEL_SIP_SMC_RSU_ERROR; 527 } 528 529 return INTEL_SIP_SMC_STATUS_OK; 530 } 531 532 static uint32_t intel_rsu_get_device_info(uint32_t *respbuf, 533 unsigned int respbuf_sz) 534 { 535 if (mailbox_rsu_get_device_info((uint32_t *)respbuf, respbuf_sz) < 0) { 536 return INTEL_SIP_SMC_RSU_ERROR; 537 } 538 539 return INTEL_SIP_SMC_STATUS_OK; 540 } 541 542 uint32_t intel_rsu_update(uint64_t update_address) 543 { 544 if (update_address > SIZE_MAX) { 545 return INTEL_SIP_SMC_STATUS_REJECTED; 546 } 547 548 intel_rsu_update_address = update_address; 549 return INTEL_SIP_SMC_STATUS_OK; 550 } 551 552 static uint32_t intel_rsu_notify(uint32_t execution_stage) 553 { 554 if (mailbox_hps_stage_notify(execution_stage) < 0) { 555 return INTEL_SIP_SMC_RSU_ERROR; 556 } 557 558 return INTEL_SIP_SMC_STATUS_OK; 559 } 560 561 static uint32_t intel_rsu_retry_counter(uint32_t *respbuf, uint32_t respbuf_sz, 562 uint32_t *ret_stat) 563 { 564 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) { 565 return INTEL_SIP_SMC_RSU_ERROR; 566 } 567 568 *ret_stat = respbuf[8]; 569 return INTEL_SIP_SMC_STATUS_OK; 570 } 571 572 static uint32_t intel_rsu_copy_dcmf_version(uint64_t dcmf_ver_1_0, 573 uint64_t dcmf_ver_3_2) 574 { 575 rsu_dcmf_ver[0] = dcmf_ver_1_0; 576 rsu_dcmf_ver[1] = dcmf_ver_1_0 >> 32; 577 rsu_dcmf_ver[2] = dcmf_ver_3_2; 578 rsu_dcmf_ver[3] = dcmf_ver_3_2 >> 32; 579 580 return INTEL_SIP_SMC_STATUS_OK; 581 } 582 583 static uint32_t intel_rsu_copy_dcmf_status(uint64_t dcmf_stat) 584 { 585 rsu_dcmf_stat[0] = 0xFFFF & (dcmf_stat >> (0 * 16)); 586 rsu_dcmf_stat[1] = 0xFFFF & (dcmf_stat >> (1 * 16)); 587 rsu_dcmf_stat[2] = 0xFFFF & (dcmf_stat >> (2 * 16)); 588 rsu_dcmf_stat[3] = 0xFFFF & (dcmf_stat >> (3 * 16)); 589 590 return INTEL_SIP_SMC_STATUS_OK; 591 } 592 593 /* Intel HWMON services */ 594 static uint32_t intel_hwmon_readtemp(uint32_t chan, uint32_t *retval) 595 { 596 if (mailbox_hwmon_readtemp(chan, retval) < 0) { 597 return INTEL_SIP_SMC_STATUS_ERROR; 598 } 599 600 return INTEL_SIP_SMC_STATUS_OK; 601 } 602 603 static uint32_t intel_hwmon_readvolt(uint32_t chan, uint32_t *retval) 604 { 605 if (mailbox_hwmon_readvolt(chan, retval) < 0) { 606 return INTEL_SIP_SMC_STATUS_ERROR; 607 } 608 609 return INTEL_SIP_SMC_STATUS_OK; 610 } 611 612 /* Mailbox services */ 613 static uint32_t intel_smc_fw_version(uint32_t *fw_version) 614 { 615 int status; 616 unsigned int resp_len = CONFIG_STATUS_WORD_SIZE; 617 uint32_t resp_data[CONFIG_STATUS_WORD_SIZE] = {0U}; 618 619 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CONFIG_STATUS, NULL, 0U, 620 CMD_CASUAL, resp_data, &resp_len); 621 622 if (status < 0) { 623 return INTEL_SIP_SMC_STATUS_ERROR; 624 } 625 626 if (resp_len <= CONFIG_STATUS_FW_VER_OFFSET) { 627 return INTEL_SIP_SMC_STATUS_ERROR; 628 } 629 630 *fw_version = resp_data[CONFIG_STATUS_FW_VER_OFFSET] & CONFIG_STATUS_FW_VER_MASK; 631 632 return INTEL_SIP_SMC_STATUS_OK; 633 } 634 635 static uint32_t intel_mbox_send_cmd(uint32_t cmd, uint32_t *args, 636 unsigned int len, uint32_t urgent, uint64_t response, 637 unsigned int resp_len, int *mbox_status, 638 unsigned int *len_in_resp) 639 { 640 *len_in_resp = 0; 641 *mbox_status = GENERIC_RESPONSE_ERROR; 642 643 if (!is_address_in_ddr_range((uint64_t)args, sizeof(uint32_t) * len)) { 644 return INTEL_SIP_SMC_STATUS_REJECTED; 645 } 646 647 int status = mailbox_send_cmd(MBOX_JOB_ID, cmd, args, len, urgent, 648 (uint32_t *) response, &resp_len); 649 650 if (status < 0) { 651 *mbox_status = -status; 652 return INTEL_SIP_SMC_STATUS_ERROR; 653 } 654 655 *mbox_status = 0; 656 *len_in_resp = resp_len; 657 658 flush_dcache_range(response, resp_len * MBOX_WORD_BYTE); 659 660 return INTEL_SIP_SMC_STATUS_OK; 661 } 662 663 static int intel_smc_get_usercode(uint32_t *user_code) 664 { 665 int status; 666 unsigned int resp_len = sizeof(user_code) / MBOX_WORD_BYTE; 667 668 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_GET_USERCODE, NULL, 669 0U, CMD_CASUAL, user_code, &resp_len); 670 671 if (status < 0) { 672 return INTEL_SIP_SMC_STATUS_ERROR; 673 } 674 675 return INTEL_SIP_SMC_STATUS_OK; 676 } 677 678 uint32_t intel_smc_service_completed(uint64_t addr, uint32_t size, 679 uint32_t mode, uint32_t *job_id, 680 uint32_t *ret_size, uint32_t *mbox_error) 681 { 682 int status = 0; 683 uint32_t resp_len = size / MBOX_WORD_BYTE; 684 685 if (resp_len > MBOX_DATA_MAX_LEN) { 686 return INTEL_SIP_SMC_STATUS_REJECTED; 687 } 688 689 if (!is_address_in_ddr_range(addr, size)) { 690 return INTEL_SIP_SMC_STATUS_REJECTED; 691 } 692 693 if (mode == SERVICE_COMPLETED_MODE_ASYNC) { 694 status = mailbox_read_response_async(job_id, 695 NULL, (uint32_t *) addr, &resp_len, 0); 696 } else { 697 status = mailbox_read_response(job_id, 698 (uint32_t *) addr, &resp_len); 699 700 if (status == MBOX_NO_RESPONSE) { 701 status = MBOX_BUSY; 702 } 703 } 704 705 if (status == MBOX_NO_RESPONSE) { 706 return INTEL_SIP_SMC_STATUS_NO_RESPONSE; 707 } 708 709 if (status == MBOX_BUSY) { 710 return INTEL_SIP_SMC_STATUS_BUSY; 711 } 712 713 *ret_size = resp_len * MBOX_WORD_BYTE; 714 flush_dcache_range(addr, *ret_size); 715 716 if (status == MBOX_RET_SDOS_DECRYPTION_ERROR_102 || 717 status == MBOX_RET_SDOS_DECRYPTION_ERROR_103) { 718 *mbox_error = -status; 719 } else if (status != MBOX_RET_OK) { 720 *mbox_error = -status; 721 return INTEL_SIP_SMC_STATUS_ERROR; 722 } 723 724 return INTEL_SIP_SMC_STATUS_OK; 725 } 726 727 /* Miscellaneous HPS services */ 728 uint32_t intel_hps_set_bridges(uint64_t enable, uint64_t mask) 729 { 730 int status = 0; 731 732 if ((enable & SOCFPGA_BRIDGE_ENABLE) != 0U) { 733 if ((enable & SOCFPGA_BRIDGE_HAS_MASK) != 0U) { 734 status = socfpga_bridges_enable((uint32_t)mask); 735 } else { 736 status = socfpga_bridges_enable(~0); 737 } 738 } else { 739 if ((enable & SOCFPGA_BRIDGE_HAS_MASK) != 0U) { 740 status = socfpga_bridges_disable((uint32_t)mask); 741 } else { 742 status = socfpga_bridges_disable(~0); 743 } 744 } 745 746 if (status < 0) { 747 return INTEL_SIP_SMC_STATUS_ERROR; 748 } 749 750 return INTEL_SIP_SMC_STATUS_OK; 751 } 752 753 /* SDM SEU Error services */ 754 static uint32_t intel_sdm_seu_err_read(uint32_t *respbuf, unsigned int respbuf_sz) 755 { 756 if (mailbox_seu_err_status(respbuf, respbuf_sz) < 0) { 757 return INTEL_SIP_SMC_SEU_ERR_READ_ERROR; 758 } 759 760 return INTEL_SIP_SMC_STATUS_OK; 761 } 762 763 /* SDM SAFE SEU Error inject services */ 764 static uint32_t intel_sdm_safe_inject_seu_err(uint32_t *command, uint32_t len) 765 { 766 if (mailbox_safe_inject_seu_err(command, len) < 0) { 767 return INTEL_SIP_SMC_SEU_ERR_READ_ERROR; 768 } 769 770 return INTEL_SIP_SMC_STATUS_OK; 771 } 772 773 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 774 /* SMMU HPS Remapper */ 775 void intel_smmu_hps_remapper_init(uint64_t *mem) 776 { 777 /* Read out Bit 1 value */ 778 uint32_t remap = (mmio_read_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_POR_1)) & 0x02); 779 780 if ((remap == 0x00) && (g_remapper_bypass == 0x00)) { 781 /* Update DRAM Base address for SDM SMMU */ 782 mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_ARADDR_REMAP), DRAM_BASE); 783 mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_AWADDR_REMAP), DRAM_BASE); 784 *mem = *mem - DRAM_BASE; 785 } else { 786 *mem = *mem - DRAM_BASE; 787 } 788 } 789 790 int intel_smmu_hps_remapper_config(uint32_t remapper_bypass) 791 { 792 /* Read out the JTAG-ID from boot scratch register */ 793 if (is_agilex5_A5F0() || is_agilex5_A5F4()) { 794 if (remapper_bypass == 0x01) { 795 g_remapper_bypass = remapper_bypass; 796 mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_ARADDR_REMAP), 0); 797 mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_AWADDR_REMAP), 0); 798 } 799 } 800 return INTEL_SIP_SMC_STATUS_OK; 801 } 802 #endif 803 804 #if SIP_SVC_V3 805 uint8_t sip_smc_cmd_cb_ret2(void *resp_desc, void *cmd_desc, uint64_t *ret_args) 806 { 807 uint8_t ret_args_len = 0U; 808 sdm_response_t *resp = (sdm_response_t *)resp_desc; 809 sdm_command_t *cmd = (sdm_command_t *)cmd_desc; 810 811 (void)cmd; 812 /* Returns 3 SMC arguments for SMC_RET3 */ 813 ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK; 814 ret_args[ret_args_len++] = resp->err_code; 815 816 return ret_args_len; 817 } 818 819 uint8_t sip_smc_cmd_cb_ret3(void *resp_desc, void *cmd_desc, uint64_t *ret_args) 820 { 821 uint8_t ret_args_len = 0U; 822 sdm_response_t *resp = (sdm_response_t *)resp_desc; 823 sdm_command_t *cmd = (sdm_command_t *)cmd_desc; 824 825 (void)cmd; 826 /* Returns 3 SMC arguments for SMC_RET3 */ 827 ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK; 828 ret_args[ret_args_len++] = resp->err_code; 829 ret_args[ret_args_len++] = resp->resp_data[0]; 830 831 return ret_args_len; 832 } 833 834 uint8_t sip_smc_ret_nbytes_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args) 835 { 836 uint8_t ret_args_len = 0U; 837 sdm_response_t *resp = (sdm_response_t *)resp_desc; 838 sdm_command_t *cmd = (sdm_command_t *)cmd_desc; 839 840 (void)cmd; 841 INFO("MBOX: %s: mailbox_err 0%x, nbytes_ret %d\n", 842 __func__, resp->err_code, resp->rcvd_resp_len * MBOX_WORD_BYTE); 843 844 ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK; 845 ret_args[ret_args_len++] = resp->err_code; 846 ret_args[ret_args_len++] = resp->rcvd_resp_len * MBOX_WORD_BYTE; 847 848 return ret_args_len; 849 } 850 851 uint8_t sip_smc_get_chipid_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args) 852 { 853 uint8_t ret_args_len = 0U; 854 sdm_response_t *resp = (sdm_response_t *)resp_desc; 855 sdm_command_t *cmd = (sdm_command_t *)cmd_desc; 856 857 (void)cmd; 858 INFO("MBOX: %s: mailbox_err 0%x, data[0] 0x%x, data[1] 0x%x\n", 859 __func__, resp->err_code, resp->resp_data[0], resp->resp_data[1]); 860 861 ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK; 862 ret_args[ret_args_len++] = resp->err_code; 863 ret_args[ret_args_len++] = resp->resp_data[0]; 864 ret_args[ret_args_len++] = resp->resp_data[1]; 865 866 return ret_args_len; 867 } 868 869 uint8_t sip_smc_cmd_cb_rsu_status(void *resp_desc, void *cmd_desc, uint64_t *ret_args) 870 { 871 uint8_t ret_args_len = 0U; 872 uint32_t retry_counter = ~0U; 873 uint32_t failure_source = 0U; 874 sdm_response_t *resp = (sdm_response_t *)resp_desc; 875 sdm_command_t *cmd = (sdm_command_t *)cmd_desc; 876 877 (void)cmd; 878 /* Get the failure source and current image retry counter value from the response. */ 879 failure_source = resp->resp_data[5] & RSU_VERSION_ACMF_MASK; 880 retry_counter = resp->resp_data[8]; 881 882 if ((retry_counter != ~0U) && (failure_source == 0U)) 883 resp->resp_data[5] |= RSU_VERSION_ACMF; 884 885 ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK; 886 ret_args[ret_args_len++] = resp->err_code; 887 /* Current CMF */ 888 ret_args[ret_args_len++] = GET_ADDR64(resp->resp_data[1], resp->resp_data[0]); 889 /* Last Failing CMF Address */ 890 ret_args[ret_args_len++] = GET_ADDR64(resp->resp_data[3], resp->resp_data[2]); 891 /* Config State */ 892 ret_args[ret_args_len++] = resp->resp_data[4]; 893 /* Version */ 894 ret_args[ret_args_len++] = (GENMASK(16, 0) & resp->resp_data[5]); 895 /* Failure Source */ 896 ret_args[ret_args_len++] = ((GENMASK(32, 17) & resp->resp_data[5]) >> 16); 897 /* Error location */ 898 ret_args[ret_args_len++] = resp->resp_data[6]; 899 /* Error details */ 900 ret_args[ret_args_len++] = resp->resp_data[7]; 901 /* Current image retry counter */ 902 ret_args[ret_args_len++] = resp->resp_data[8]; 903 904 return ret_args_len; 905 } 906 907 uint8_t sip_smc_cmd_cb_rsu_spt(void *resp_desc, void *cmd_desc, uint64_t *ret_args) 908 { 909 uint8_t ret_args_len = 0U; 910 sdm_response_t *resp = (sdm_response_t *)resp_desc; 911 sdm_command_t *cmd = (sdm_command_t *)cmd_desc; 912 913 (void)cmd; 914 915 ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK; 916 ret_args[ret_args_len++] = resp->err_code; 917 /* Sub Partition Table (SPT) 0 address */ 918 ret_args[ret_args_len++] = GET_ADDR64(resp->resp_data[0], resp->resp_data[1]); 919 /* Sub Partition Table (SPT) 1 address */ 920 ret_args[ret_args_len++] = GET_ADDR64(resp->resp_data[2], resp->resp_data[3]); 921 922 return ret_args_len; 923 } 924 925 static uintptr_t smc_ret(void *handle, uint64_t *ret_args, uint32_t ret_args_len) 926 { 927 928 switch (ret_args_len) { 929 case SMC_RET_ARGS_ONE: 930 VERBOSE("SVC V3: %s: x0 0x%lx\n", __func__, ret_args[0]); 931 SMC_RET1(handle, ret_args[0]); 932 break; 933 934 case SMC_RET_ARGS_TWO: 935 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx\n", __func__, ret_args[0], ret_args[1]); 936 SMC_RET2(handle, ret_args[0], ret_args[1]); 937 break; 938 939 case SMC_RET_ARGS_THREE: 940 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx, x2 0x%lx\n", 941 __func__, ret_args[0], ret_args[1], ret_args[2]); 942 SMC_RET3(handle, ret_args[0], ret_args[1], ret_args[2]); 943 break; 944 945 case SMC_RET_ARGS_FOUR: 946 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx, x2 0x%lx, x3 0x%lx\n", 947 __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3]); 948 SMC_RET4(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3]); 949 break; 950 951 case SMC_RET_ARGS_FIVE: 952 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx, x2 0x%lx, x3 0x%lx, x4 0x%lx\n", 953 __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4]); 954 SMC_RET5(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4]); 955 break; 956 957 case SMC_RET_ARGS_SIX: 958 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx x2 0x%lx x3 0x%lx, x4 0x%lx x5 0x%lx\n", 959 __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4], 960 ret_args[5]); 961 SMC_RET6(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4], 962 ret_args[5]); 963 break; 964 965 case SMC_RET_ARGS_SEVEN: 966 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx x2 0x%lx, x3 0x%lx, x4 0x%lx, x5 0x%lx\t" 967 "x6 0x%lx\n", 968 __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4], 969 ret_args[5], ret_args[6]); 970 SMC_RET7(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4], 971 ret_args[5], ret_args[6]); 972 break; 973 974 case SMC_RET_ARGS_EIGHT: 975 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx x2 0x%lx, x3 0x%lx, x4 0x%lx x5 0x%lx\t" 976 "x6 0x%lx, x7 0x%lx\n", 977 __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4], 978 ret_args[5], ret_args[6], ret_args[7]); 979 SMC_RET8(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4], 980 ret_args[5], ret_args[6], ret_args[7]); 981 break; 982 983 case SMC_RET_ARGS_NINE: 984 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx x2 0x%lx, x3 0x%lx, x4 0x%lx, x5 0x%lx\t" 985 "x6 0x%lx, x7 0x%lx, x8 0x%lx\n", 986 __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4], 987 ret_args[5], ret_args[6], ret_args[7], ret_args[8]); 988 SMC_RET18(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4], 989 ret_args[5], ret_args[6], ret_args[7], ret_args[8], 990 0, 0, 0, 0, 0, 0, 0, 0, 0); 991 break; 992 993 case SMC_RET_ARGS_TEN: 994 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx, x2 0x%lx, x3 0x%lx, x4 0x%lx x5 0x%lx\t" 995 "x6 0x%lx, x7 0x%lx x8 0x%lx, x9 0x%lx, x10 0x%lx\n", 996 __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], 997 ret_args[4], ret_args[5], ret_args[6], ret_args[7], ret_args[8], 998 ret_args[9], ret_args[10]); 999 SMC_RET18(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4], 1000 ret_args[5], ret_args[6], ret_args[7], ret_args[8], ret_args[9], 1001 0, 0, 0, 0, 0, 0, 0, 0); 1002 break; 1003 1004 default: 1005 VERBOSE("SVC V3: %s ret_args_len is wrong, please check %d\n ", 1006 __func__, ret_args_len); 1007 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR); 1008 break; 1009 } 1010 } 1011 1012 static inline bool is_gen_mbox_cmd_allowed(uint32_t cmd) 1013 { 1014 /* Check if the command is allowed to be executed in generic mbox format */ 1015 bool is_cmd_allowed = false; 1016 1017 switch (cmd) { 1018 case ALTERA_SIP_SMC_ASYNC_FCS_OPEN_CS_SESSION: 1019 case ALTERA_SIP_SMC_ASYNC_FCS_CLOSE_CS_SESSION: 1020 case ALTERA_SIP_SMC_ASYNC_FCS_IMPORT_CS_KEY: 1021 case ALTERA_SIP_SMC_ASYNC_FCS_EXPORT_CS_KEY: 1022 case ALTERA_SIP_SMC_ASYNC_FCS_REMOVE_CS_KEY: 1023 case ALTERA_SIP_SMC_ASYNC_FCS_GET_CS_KEY_INFO: 1024 case ALTERA_SIP_SMC_ASYNC_FCS_CREATE_CS_KEY: 1025 case ALTERA_SIP_SMC_ASYNC_FCS_RANDOM_NUMBER_EXT: 1026 case ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_INIT: 1027 case ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_UPDATE: 1028 case ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_FINALIZE: 1029 case ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_INIT: 1030 case ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_UPDATE: 1031 case ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_FINALIZE: 1032 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIGN_INIT: 1033 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIGN_FINALIZE: 1034 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_INIT: 1035 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_UPDATE: 1036 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE: 1037 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_UPDATE: 1038 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_FINALIZE: 1039 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIG_VERIFY_INIT: 1040 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIG_VERIFY_FINALIZE: 1041 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_INIT: 1042 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_UPDATE: 1043 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE: 1044 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_UPDATE: 1045 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_FINALIZE: 1046 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_GET_PUBKEY_INIT: 1047 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_GET_PUBKEY_FINALIZE: 1048 case ALTERA_SIP_SMC_ASYNC_FCS_ECDH_REQUEST_INIT: 1049 case ALTERA_SIP_SMC_ASYNC_FCS_ECDH_REQUEST_FINALIZE: 1050 case ALTERA_SIP_SMC_ASYNC_FCS_HKDF_REQUEST: 1051 case ALTERA_SIP_SMC_ASYNC_FCS_CRYPTION_EXT: 1052 case ALTERA_SIP_SMC_ASYNC_FCS_CRYPTION: 1053 /* These commands are not supported in the generic mailbox format. */ 1054 break; 1055 1056 default: 1057 is_cmd_allowed = true; 1058 break; 1059 } /* switch */ 1060 1061 return is_cmd_allowed; 1062 } 1063 1064 /* 1065 * This function is responsible for handling all SiP SVC V3 calls from the 1066 * non-secure world. 1067 */ 1068 static uintptr_t sip_smc_handler_v3(uint32_t smc_fid, 1069 u_register_t x1, 1070 u_register_t x2, 1071 u_register_t x3, 1072 u_register_t x4, 1073 void *cookie, 1074 void *handle, 1075 u_register_t flags) 1076 { 1077 int status = 0; 1078 uint32_t mbox_error = 0U; 1079 u_register_t x5, x6, x7, x8, x9, x10, x11; 1080 1081 /* Get all the SMC call arguments */ 1082 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1083 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1084 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1085 x8 = SMC_GET_GP(handle, CTX_GPREG_X8); 1086 x9 = SMC_GET_GP(handle, CTX_GPREG_X9); 1087 x10 = SMC_GET_GP(handle, CTX_GPREG_X10); 1088 x11 = SMC_GET_GP(handle, CTX_GPREG_X11); 1089 1090 INFO("MBOX: SVC_V3: x0 0x%x, x1 0x%lx, x2 0x%lx, x3 0x%lx, x4 0x%lx, x5 0x%lx\n", 1091 smc_fid, x1, x2, x3, x4, x5); 1092 INFO("MBOX: SVC_V3: x6 0x%lx, x7 0x%lx, x8 0x%lx, x9 0x%lx, x10 0x%lx x11 0x%lx\n", 1093 x6, x7, x8, x9, x10, x11); 1094 1095 switch (smc_fid) { 1096 case ALTERA_SIP_SMC_ASYNC_RESP_POLL: 1097 { 1098 uint64_t ret_args[16] = {0}; 1099 uint32_t ret_args_len = 0; 1100 1101 status = mailbox_response_poll_v3(GET_CLIENT_ID(x1), 1102 GET_JOB_ID(x1), 1103 ret_args, 1104 &ret_args_len); 1105 /* Always reserve [0] index for command status. */ 1106 ret_args[0] = status; 1107 1108 /* Return SMC call based on the number of return arguments */ 1109 return smc_ret(handle, ret_args, ret_args_len); 1110 } 1111 1112 case ALTERA_SIP_SMC_ASYNC_RESP_POLL_ON_INTR: 1113 { 1114 /* TBD: Here now we don't need these CID and JID?? */ 1115 uint8_t client_id = 0U; 1116 uint8_t job_id = 0U; 1117 uint64_t trans_id_bitmap[4] = {0U}; 1118 1119 status = mailbox_response_poll_on_intr_v3(&client_id, 1120 &job_id, 1121 trans_id_bitmap); 1122 1123 SMC_RET5(handle, status, trans_id_bitmap[0], trans_id_bitmap[1], 1124 trans_id_bitmap[2], trans_id_bitmap[3]); 1125 break; 1126 } 1127 1128 case ALTERA_SIP_SMC_ASYNC_GET_DEVICE_IDENTITY: 1129 { 1130 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1131 GET_JOB_ID(x1), 1132 MBOX_CMD_GET_DEVICEID, 1133 NULL, 1134 0U, 1135 MBOX_CMD_FLAG_CASUAL, 1136 sip_smc_ret_nbytes_cb, 1137 (uint32_t *)x2, 1138 2); 1139 1140 SMC_RET1(handle, status); 1141 } 1142 1143 case ALTERA_SIP_SMC_ASYNC_GET_IDCODE: 1144 { 1145 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1146 GET_JOB_ID(x1), 1147 MBOX_CMD_GET_IDCODE, 1148 NULL, 1149 0U, 1150 MBOX_CMD_FLAG_CASUAL, 1151 sip_smc_cmd_cb_ret3, 1152 NULL, 1153 0); 1154 1155 SMC_RET1(handle, status); 1156 } 1157 1158 case ALTERA_SIP_SMC_ASYNC_QSPI_OPEN: 1159 { 1160 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1161 GET_JOB_ID(x1), 1162 MBOX_CMD_QSPI_OPEN, 1163 NULL, 1164 0U, 1165 MBOX_CMD_FLAG_CASUAL, 1166 sip_smc_cmd_cb_ret2, 1167 NULL, 1168 0U); 1169 1170 SMC_RET1(handle, status); 1171 } 1172 1173 case ALTERA_SIP_SMC_ASYNC_QSPI_CLOSE: 1174 { 1175 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1176 GET_JOB_ID(x1), 1177 MBOX_CMD_QSPI_CLOSE, 1178 NULL, 1179 0U, 1180 MBOX_CMD_FLAG_CASUAL, 1181 sip_smc_cmd_cb_ret2, 1182 NULL, 1183 0U); 1184 1185 SMC_RET1(handle, status); 1186 } 1187 1188 case ALTERA_SIP_SMC_ASYNC_QSPI_SET_CS: 1189 { 1190 uint32_t cmd_data = 0U; 1191 uint32_t chip_sel = (uint32_t)x2; 1192 uint32_t comb_addr_mode = (uint32_t)x3; 1193 uint32_t ext_dec_mode = (uint32_t)x4; 1194 1195 cmd_data = (chip_sel << MBOX_QSPI_SET_CS_OFFSET) | 1196 (comb_addr_mode << MBOX_QSPI_SET_CS_CA_OFFSET) | 1197 (ext_dec_mode << MBOX_QSPI_SET_CS_MODE_OFFSET); 1198 1199 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1200 GET_JOB_ID(x1), 1201 MBOX_CMD_QSPI_SET_CS, 1202 &cmd_data, 1203 1U, 1204 MBOX_CMD_FLAG_CASUAL, 1205 sip_smc_cmd_cb_ret2, 1206 NULL, 1207 0U); 1208 1209 SMC_RET1(handle, status); 1210 } 1211 1212 case ALTERA_SIP_SMC_ASYNC_QSPI_ERASE: 1213 { 1214 uint32_t qspi_addr = (uint32_t)x2; 1215 uint32_t qspi_nwords = (uint32_t)x3; 1216 1217 /* QSPI address offset to start erase, must be 4K aligned */ 1218 if (MBOX_IS_4K_ALIGNED(qspi_addr)) { 1219 ERROR("MBOX: 0x%x: QSPI address not 4K aligned\n", 1220 smc_fid); 1221 status = INTEL_SIP_SMC_STATUS_REJECTED; 1222 SMC_RET1(handle, status); 1223 } 1224 1225 /* Number of words to erase, multiples of 0x400 or 4K */ 1226 if (qspi_nwords % MBOX_QSPI_ERASE_SIZE_GRAN) { 1227 ERROR("MBOX: 0x%x: Given words not in multiples of 4K\n", 1228 smc_fid); 1229 status = INTEL_SIP_SMC_STATUS_REJECTED; 1230 SMC_RET1(handle, status); 1231 } 1232 1233 uint32_t cmd_data[2] = {qspi_addr, qspi_nwords}; 1234 1235 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1236 GET_JOB_ID(x1), 1237 MBOX_CMD_QSPI_ERASE, 1238 cmd_data, 1239 sizeof(cmd_data) / MBOX_WORD_BYTE, 1240 MBOX_CMD_FLAG_CASUAL, 1241 sip_smc_cmd_cb_ret2, 1242 NULL, 1243 0U); 1244 1245 SMC_RET1(handle, status); 1246 } 1247 1248 case ALTERA_SIP_SMC_ASYNC_QSPI_WRITE: 1249 { 1250 uint32_t *qspi_payload = (uint32_t *)x2; 1251 uint32_t qspi_total_nwords = (((uint32_t)x3) / MBOX_WORD_BYTE); 1252 uint32_t qspi_addr = qspi_payload[0]; 1253 uint32_t qspi_nwords = qspi_payload[1]; 1254 1255 if (!MBOX_IS_WORD_ALIGNED(qspi_addr)) { 1256 ERROR("MBOX: 0x%x: Given address is not WORD aligned\n", 1257 smc_fid); 1258 status = INTEL_SIP_SMC_STATUS_REJECTED; 1259 SMC_RET1(handle, status); 1260 } 1261 1262 if (qspi_nwords > MBOX_QSPI_RW_MAX_WORDS) { 1263 ERROR("MBOX: 0x%x: Number of words exceeds max limit\n", 1264 smc_fid); 1265 status = INTEL_SIP_SMC_STATUS_REJECTED; 1266 SMC_RET1(handle, status); 1267 } 1268 1269 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1270 GET_JOB_ID(x1), 1271 MBOX_CMD_QSPI_WRITE, 1272 qspi_payload, 1273 qspi_total_nwords, 1274 MBOX_CMD_FLAG_CASUAL, 1275 sip_smc_cmd_cb_ret2, 1276 NULL, 1277 0U); 1278 1279 SMC_RET1(handle, status); 1280 } 1281 1282 case ALTERA_SIP_SMC_ASYNC_QSPI_READ: 1283 { 1284 uint32_t qspi_addr = (uint32_t)x2; 1285 uint32_t qspi_nwords = (((uint32_t)x4) / MBOX_WORD_BYTE); 1286 1287 if (qspi_nwords > MBOX_QSPI_RW_MAX_WORDS) { 1288 ERROR("MBOX: 0x%x: Number of words exceeds max limit\n", 1289 smc_fid); 1290 status = INTEL_SIP_SMC_STATUS_REJECTED; 1291 SMC_RET1(handle, status); 1292 } 1293 1294 uint32_t cmd_data[2] = {qspi_addr, qspi_nwords}; 1295 1296 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1297 GET_JOB_ID(x1), 1298 MBOX_CMD_QSPI_READ, 1299 cmd_data, 1300 sizeof(cmd_data) / MBOX_WORD_BYTE, 1301 MBOX_CMD_FLAG_CASUAL, 1302 sip_smc_ret_nbytes_cb, 1303 (uint32_t *)x3, 1304 2); 1305 1306 SMC_RET1(handle, status); 1307 } 1308 1309 case ALTERA_SIP_SMC_ASYNC_QSPI_GET_DEV_INFO: 1310 { 1311 uint32_t *dst_addr = (uint32_t *)x2; 1312 1313 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1314 GET_JOB_ID(x1), 1315 MBOX_CMD_QSPI_GET_DEV_INFO, 1316 NULL, 1317 0U, 1318 MBOX_CMD_FLAG_CASUAL, 1319 sip_smc_ret_nbytes_cb, 1320 (uint32_t *)dst_addr, 1321 2); 1322 1323 SMC_RET1(handle, status); 1324 } 1325 1326 case ALTERA_SIP_SMC_ASYNC_HWMON_READVOLT: 1327 case ALTERA_SIP_SMC_ASYNC_HWMON_READTEMP: 1328 { 1329 uint32_t channel = (uint32_t)x2; 1330 uint32_t mbox_cmd = ((smc_fid == ALTERA_SIP_SMC_ASYNC_HWMON_READVOLT) ? 1331 MBOX_HWMON_READVOLT : MBOX_HWMON_READTEMP); 1332 1333 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1334 GET_JOB_ID(x1), 1335 mbox_cmd, 1336 &channel, 1337 1U, 1338 MBOX_CMD_FLAG_CASUAL, 1339 sip_smc_cmd_cb_ret3, 1340 NULL, 1341 0); 1342 1343 SMC_RET1(handle, status); 1344 } 1345 1346 case ALTERA_SIP_SMC_ASYNC_RSU_GET_SPT: 1347 { 1348 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1349 GET_JOB_ID(x1), 1350 MBOX_GET_SUBPARTITION_TABLE, 1351 NULL, 1352 0, 1353 MBOX_CMD_FLAG_CASUAL, 1354 sip_smc_cmd_cb_rsu_spt, 1355 NULL, 1356 0); 1357 1358 SMC_RET1(handle, status); 1359 } 1360 1361 case ALTERA_SIP_SMC_ASYNC_RSU_GET_STATUS: 1362 { 1363 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1364 GET_JOB_ID(x1), 1365 MBOX_RSU_STATUS, 1366 NULL, 1367 0, 1368 MBOX_CMD_FLAG_CASUAL, 1369 sip_smc_cmd_cb_rsu_status, 1370 NULL, 1371 0); 1372 1373 SMC_RET1(handle, status); 1374 } 1375 1376 case ALTERA_SIP_SMC_ASYNC_RSU_NOTIFY: 1377 { 1378 uint32_t notify_code = (uint32_t)x2; 1379 1380 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1381 GET_JOB_ID(x1), 1382 MBOX_HPS_STAGE_NOTIFY, 1383 ¬ify_code, 1384 1U, 1385 MBOX_CMD_FLAG_CASUAL, 1386 sip_smc_cmd_cb_ret2, 1387 NULL, 1388 0); 1389 1390 SMC_RET1(handle, status); 1391 } 1392 1393 case ALTERA_SIP_SMC_ASYNC_GEN_MBOX_CMD: 1394 { 1395 /* Filter the required commands here. */ 1396 if (!is_gen_mbox_cmd_allowed(smc_fid)) { 1397 status = INTEL_SIP_SMC_STATUS_REJECTED; 1398 SMC_RET1(handle, status); 1399 } 1400 1401 /* Collect all the args passed in, and send the mailbox command. */ 1402 uint32_t mbox_cmd = (uint32_t)x2; 1403 uint32_t *cmd_payload_addr = NULL; 1404 uint32_t cmd_payload_len = (uint32_t)x4 / MBOX_WORD_BYTE; 1405 uint32_t *resp_payload_addr = NULL; 1406 uint32_t resp_payload_len = (uint32_t)x6 / MBOX_WORD_BYTE; 1407 1408 if ((cmd_payload_len > MBOX_GEN_CMD_MAX_WORDS) || 1409 (resp_payload_len > MBOX_GEN_CMD_MAX_WORDS)) { 1410 ERROR("MBOX: 0x%x: Command/Response payload length exceeds max limit\n", 1411 smc_fid); 1412 status = INTEL_SIP_SMC_STATUS_REJECTED; 1413 SMC_RET1(handle, status); 1414 } 1415 1416 /* Make sure we have valid command payload length and buffer */ 1417 if (cmd_payload_len != 0U) { 1418 cmd_payload_addr = (uint32_t *)x3; 1419 if (cmd_payload_addr == NULL) { 1420 ERROR("MBOX: 0x%x: Command payload address is NULL\n", 1421 smc_fid); 1422 status = INTEL_SIP_SMC_STATUS_REJECTED; 1423 SMC_RET1(handle, status); 1424 } 1425 } 1426 1427 /* Make sure we have valid response payload length and buffer */ 1428 if (resp_payload_len != 0U) { 1429 resp_payload_addr = (uint32_t *)x5; 1430 if (resp_payload_addr == NULL) { 1431 ERROR("MBOX: 0x%x: Response payload address is NULL\n", 1432 smc_fid); 1433 status = INTEL_SIP_SMC_STATUS_REJECTED; 1434 SMC_RET1(handle, status); 1435 } 1436 } 1437 1438 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1439 GET_JOB_ID(x1), 1440 mbox_cmd, 1441 (uint32_t *)cmd_payload_addr, 1442 cmd_payload_len, 1443 MBOX_CMD_FLAG_CASUAL, 1444 sip_smc_ret_nbytes_cb, 1445 (uint32_t *)resp_payload_addr, 1446 resp_payload_len); 1447 1448 SMC_RET1(handle, status); 1449 } 1450 1451 case ALTERA_SIP_SMC_ASYNC_FCS_RANDOM_NUMBER_EXT: 1452 { 1453 uint32_t session_id = (uint32_t)x2; 1454 uint32_t context_id = (uint32_t)x3; 1455 uint64_t ret_random_addr = (uint64_t)x4; 1456 uint32_t random_len = (uint32_t)SMC_GET_GP(handle, CTX_GPREG_X5); 1457 uint32_t crypto_header = 0U; 1458 1459 if ((random_len > (FCS_RANDOM_EXT_MAX_WORD_SIZE * MBOX_WORD_BYTE)) || 1460 (random_len == 0U) || 1461 (!is_size_4_bytes_aligned(random_len))) { 1462 ERROR("MBOX: 0x%x is rejected\n", smc_fid); 1463 status = INTEL_SIP_SMC_STATUS_REJECTED; 1464 SMC_RET1(handle, status); 1465 } 1466 1467 crypto_header = ((FCS_CS_FIELD_FLAG_INIT | FCS_CS_FIELD_FLAG_FINALIZE) << 1468 FCS_CS_FIELD_FLAG_OFFSET); 1469 fcs_rng_payload payload = {session_id, context_id, 1470 crypto_header, random_len}; 1471 1472 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1473 GET_JOB_ID(x1), 1474 MBOX_FCS_RANDOM_GEN, 1475 (uint32_t *)&payload, 1476 sizeof(payload) / MBOX_WORD_BYTE, 1477 MBOX_CMD_FLAG_CASUAL, 1478 sip_smc_ret_nbytes_cb, 1479 (uint32_t *)ret_random_addr, 1480 2); 1481 SMC_RET1(handle, status); 1482 } 1483 1484 case ALTERA_SIP_SMC_ASYNC_FCS_GET_PROVISION_DATA: 1485 { 1486 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1487 GET_JOB_ID(x1), 1488 MBOX_FCS_GET_PROVISION, 1489 NULL, 1490 0U, 1491 MBOX_CMD_FLAG_CASUAL, 1492 sip_smc_ret_nbytes_cb, 1493 (uint32_t *)x2, 1494 2); 1495 SMC_RET1(handle, status); 1496 } 1497 1498 case ALTERA_SIP_SMC_ASYNC_FCS_CNTR_SET_PREAUTH: 1499 { 1500 status = intel_fcs_cntr_set_preauth(smc_fid, x1, x2, x3, 1501 x4, &mbox_error); 1502 SMC_RET1(handle, status); 1503 } 1504 1505 case ALTERA_SIP_SMC_ASYNC_FCS_CHIP_ID: 1506 { 1507 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1508 GET_JOB_ID(x1), 1509 MBOX_CMD_GET_CHIPID, 1510 NULL, 1511 0U, 1512 MBOX_CMD_FLAG_CASUAL, 1513 sip_smc_get_chipid_cb, 1514 NULL, 1515 0); 1516 SMC_RET1(handle, status); 1517 } 1518 1519 case ALTERA_SIP_SMC_ASYNC_FCS_GET_ATTESTATION_CERT: 1520 { 1521 status = intel_fcs_get_attestation_cert(smc_fid, x1, x2, x3, 1522 (uint32_t *) &x4, &mbox_error); 1523 SMC_RET1(handle, status); 1524 } 1525 1526 case ALTERA_SIP_SMC_ASYNC_FCS_CREATE_CERT_ON_RELOAD: 1527 { 1528 status = intel_fcs_create_cert_on_reload(smc_fid, x1, 1529 x2, &mbox_error); 1530 SMC_RET1(handle, status); 1531 } 1532 1533 case ALTERA_SIP_SMC_ASYNC_FCS_CRYPTION_EXT: 1534 { 1535 if (x4 == FCS_MODE_ENCRYPT) { 1536 status = intel_fcs_encryption_ext(smc_fid, x1, x2, x3, 1537 x5, x6, x7, (uint32_t *) &x8, 1538 &mbox_error, x10, x11); 1539 } else if (x4 == FCS_MODE_DECRYPT) { 1540 status = intel_fcs_decryption_ext(smc_fid, x1, x2, x3, 1541 x5, x6, x7, (uint32_t *) &x8, 1542 &mbox_error, x9, x10, x11); 1543 } else { 1544 ERROR("MBOX: 0x%x: Wrong crypto mode\n", smc_fid); 1545 status = INTEL_SIP_SMC_STATUS_REJECTED; 1546 } 1547 SMC_RET1(handle, status); 1548 } 1549 1550 case ALTERA_SIP_SMC_ASYNC_FCS_SEND_CERTIFICATE: 1551 { 1552 status = intel_fcs_send_cert(smc_fid, x1, x2, x3, &mbox_error); 1553 SMC_RET1(handle, status); 1554 } 1555 1556 case ALTERA_SIP_SMC_ASYNC_FCS_OPEN_CS_SESSION: 1557 { 1558 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1559 GET_JOB_ID(x1), 1560 MBOX_FCS_OPEN_CS_SESSION, 1561 NULL, 1562 0U, 1563 MBOX_CMD_FLAG_CASUAL, 1564 sip_smc_cmd_cb_ret3, 1565 NULL, 1566 0); 1567 SMC_RET1(handle, status); 1568 } 1569 1570 case ALTERA_SIP_SMC_ASYNC_FCS_CLOSE_CS_SESSION: 1571 { 1572 uint32_t session_id = (uint32_t)x2; 1573 1574 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1575 GET_JOB_ID(x1), 1576 MBOX_FCS_CLOSE_CS_SESSION, 1577 &session_id, 1578 1U, 1579 MBOX_CMD_FLAG_CASUAL, 1580 sip_smc_cmd_cb_ret2, 1581 NULL, 1582 0); 1583 SMC_RET1(handle, status); 1584 } 1585 1586 case ALTERA_SIP_SMC_ASYNC_FCS_IMPORT_CS_KEY: 1587 { 1588 uint64_t key_addr = x2; 1589 uint32_t key_len_words = (uint32_t)x3 / MBOX_WORD_BYTE; 1590 1591 if ((key_len_words > FCS_CS_KEY_OBJ_MAX_WORD_SIZE) || 1592 (!is_address_in_ddr_range(key_addr, key_len_words * 4))) { 1593 ERROR("MBOX: 0x%x: Addr not in DDR range or key len exceeds\n", 1594 smc_fid); 1595 status = INTEL_SIP_SMC_STATUS_REJECTED; 1596 SMC_RET1(handle, status); 1597 } 1598 1599 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1600 GET_JOB_ID(x1), 1601 MBOX_FCS_IMPORT_CS_KEY, 1602 (uint32_t *)key_addr, 1603 key_len_words, 1604 MBOX_CMD_FLAG_CASUAL, 1605 sip_smc_cmd_cb_ret3, 1606 NULL, 1607 0); 1608 SMC_RET1(handle, status); 1609 } 1610 1611 case ALTERA_SIP_SMC_ASYNC_FCS_CREATE_CS_KEY: 1612 { 1613 uint64_t key_addr = x2; 1614 uint32_t key_len_words = (uint32_t)x3 / MBOX_WORD_BYTE; 1615 1616 if (!is_address_in_ddr_range(key_addr, key_len_words * 4)) { 1617 ERROR("MBOX: 0x%x: Addr not in DDR range\n", smc_fid); 1618 status = INTEL_SIP_SMC_STATUS_REJECTED; 1619 SMC_RET1(handle, status); 1620 } 1621 1622 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1623 GET_JOB_ID(x1), 1624 MBOX_FCS_CREATE_CS_KEY, 1625 (uint32_t *)key_addr, 1626 key_len_words, 1627 MBOX_CMD_FLAG_CASUAL, 1628 sip_smc_cmd_cb_ret3, 1629 NULL, 1630 0); 1631 SMC_RET1(handle, status); 1632 } 1633 1634 case ALTERA_SIP_SMC_ASYNC_FCS_EXPORT_CS_KEY: 1635 { 1636 uint32_t session_id = (uint32_t)x2; 1637 uint32_t key_uid = (uint32_t)x3; 1638 uint64_t ret_key_addr = (uint64_t)x4; 1639 uint32_t key_len = (uint32_t)SMC_GET_GP(handle, CTX_GPREG_X5); 1640 1641 if (!is_address_in_ddr_range(ret_key_addr, key_len)) { 1642 ERROR("MBOX: 0x%x: Addr not in DDR range\n", smc_fid); 1643 status = INTEL_SIP_SMC_STATUS_REJECTED; 1644 SMC_RET1(handle, status); 1645 } 1646 1647 fcs_cs_key_payload payload = {session_id, RESERVED_AS_ZERO, 1648 RESERVED_AS_ZERO, key_uid}; 1649 1650 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1651 GET_JOB_ID(x1), 1652 MBOX_FCS_EXPORT_CS_KEY, 1653 (uint32_t *)&payload, 1654 sizeof(payload) / MBOX_WORD_BYTE, 1655 MBOX_CMD_FLAG_CASUAL, 1656 sip_smc_ret_nbytes_cb, 1657 (uint32_t *)ret_key_addr, 1658 2); 1659 SMC_RET1(handle, status); 1660 } 1661 1662 case ALTERA_SIP_SMC_ASYNC_FCS_REMOVE_CS_KEY: 1663 { 1664 uint32_t session_id = (uint32_t)x2; 1665 uint32_t key_uid = (uint32_t)x3; 1666 1667 fcs_cs_key_payload payload = {session_id, RESERVED_AS_ZERO, 1668 RESERVED_AS_ZERO, key_uid}; 1669 1670 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1671 GET_JOB_ID(x1), 1672 MBOX_FCS_REMOVE_CS_KEY, 1673 (uint32_t *)&payload, 1674 sizeof(payload) / MBOX_WORD_BYTE, 1675 MBOX_CMD_FLAG_CASUAL, 1676 sip_smc_cmd_cb_ret3, 1677 NULL, 1678 0); 1679 SMC_RET1(handle, status); 1680 } 1681 1682 case ALTERA_SIP_SMC_ASYNC_FCS_GET_CS_KEY_INFO: 1683 { 1684 uint32_t session_id = (uint32_t)x2; 1685 uint32_t key_uid = (uint32_t)x3; 1686 uint64_t ret_key_addr = (uint64_t)x4; 1687 uint32_t key_len = (uint32_t)SMC_GET_GP(handle, CTX_GPREG_X5); 1688 1689 if (!is_address_in_ddr_range(ret_key_addr, key_len)) { 1690 ERROR("MBOX: 0x%x: Addr not in DDR range\n", smc_fid); 1691 status = INTEL_SIP_SMC_STATUS_REJECTED; 1692 SMC_RET1(handle, status); 1693 } 1694 1695 fcs_cs_key_payload payload = {session_id, RESERVED_AS_ZERO, 1696 RESERVED_AS_ZERO, key_uid}; 1697 1698 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1699 GET_JOB_ID(x1), 1700 MBOX_FCS_GET_CS_KEY_INFO, 1701 (uint32_t *)&payload, 1702 sizeof(payload) / MBOX_WORD_BYTE, 1703 MBOX_CMD_FLAG_CASUAL, 1704 sip_smc_ret_nbytes_cb, 1705 (uint32_t *)ret_key_addr, 1706 2); 1707 SMC_RET1(handle, status); 1708 } 1709 1710 case ALTERA_SIP_SMC_ASYNC_FCS_AES_CRYPT_INIT: 1711 { 1712 status = intel_fcs_aes_crypt_init(x2, x3, x4, x5, 1713 x6, &mbox_error); 1714 SMC_RET1(handle, status); 1715 } 1716 1717 case ALTERA_SIP_SMC_ASYNC_FCS_AES_CRYPT_UPDATE: 1718 case ALTERA_SIP_SMC_ASYNC_FCS_AES_CRYPT_FINALIZE: 1719 { 1720 uint32_t job_id = 0U; 1721 bool is_final = (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_AES_CRYPT_FINALIZE) ? 1722 true : false; 1723 1724 status = intel_fcs_aes_crypt_update_finalize(smc_fid, x1, x2, 1725 x3, x4, x5, x6, x7, x8, is_final, 1726 &job_id, x9, x10); 1727 SMC_RET1(handle, status); 1728 } 1729 1730 case ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_INIT: 1731 { 1732 status = intel_fcs_get_digest_init(x2, x3, x4, x5, x6, 1733 &mbox_error); 1734 SMC_RET1(handle, status); 1735 } 1736 1737 case ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_UPDATE: 1738 case ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_FINALIZE: 1739 { 1740 bool is_final = (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_FINALIZE) ? 1741 true : false; 1742 1743 status = intel_fcs_get_digest_update_finalize(smc_fid, x1, x2, 1744 x3, x4, x5, x6, (uint32_t *) &x7, 1745 is_final, &mbox_error, x8); 1746 1747 SMC_RET1(handle, status); 1748 } 1749 1750 case ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_INIT: 1751 { 1752 status = intel_fcs_mac_verify_init(x2, x3, x4, x5, x6, 1753 &mbox_error); 1754 SMC_RET1(handle, status); 1755 } 1756 1757 case ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_UPDATE: 1758 case ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_FINALIZE: 1759 { 1760 bool is_final = (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_FINALIZE) ? 1761 true : false; 1762 1763 status = intel_fcs_mac_verify_update_finalize(smc_fid, x1, x2, 1764 x3, x4, x5, x6, (uint32_t *) &x7, x8, 1765 is_final, &mbox_error, x9); 1766 SMC_RET1(handle, status); 1767 } 1768 1769 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIGN_INIT: 1770 { 1771 status = intel_fcs_ecdsa_hash_sign_init(x2, x3, x4, x5, x6, 1772 &mbox_error); 1773 SMC_RET1(handle, status); 1774 } 1775 1776 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIGN_FINALIZE: 1777 { 1778 status = intel_fcs_ecdsa_hash_sign_finalize(smc_fid, x1, x2, x3, 1779 x4, x5, x6, (uint32_t *) &x7, 1780 &mbox_error); 1781 SMC_RET1(handle, status); 1782 } 1783 1784 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_INIT: 1785 { 1786 status = intel_fcs_ecdsa_sha2_data_sign_init(x2, x3, x4, x5, x6, 1787 &mbox_error); 1788 SMC_RET1(handle, status); 1789 } 1790 1791 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_UPDATE: 1792 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE: 1793 { 1794 bool is_final = (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE) 1795 ? true : false; 1796 1797 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(smc_fid, 1798 x1, x2, x3, x4, x5, x6, (uint32_t *) &x7, 1799 is_final, &mbox_error, x8); 1800 SMC_RET1(handle, status); 1801 } 1802 1803 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIG_VERIFY_INIT: 1804 { 1805 status = intel_fcs_ecdsa_hash_sig_verify_init(x2, x3, x4, x5, 1806 x6, &mbox_error); 1807 SMC_RET1(handle, status); 1808 } 1809 1810 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIG_VERIFY_FINALIZE: 1811 { 1812 status = intel_fcs_ecdsa_hash_sig_verify_finalize(smc_fid, x1, 1813 x2, x3, x4, x5, x6, (uint32_t *) &x7, 1814 &mbox_error); 1815 SMC_RET1(handle, status); 1816 } 1817 1818 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_INIT: 1819 { 1820 status = intel_fcs_ecdsa_sha2_data_sig_verify_init(x2, x3, x4, 1821 x5, x6, &mbox_error); 1822 SMC_RET1(handle, status); 1823 } 1824 1825 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_UPDATE: 1826 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE: 1827 { 1828 bool is_final = (smc_fid == 1829 ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE) ? 1830 true : false; 1831 1832 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize( 1833 smc_fid, x1, x2, x3, x4, x5, x6, 1834 (uint32_t *) &x7, x8, is_final, 1835 &mbox_error, x9); 1836 SMC_RET1(handle, status); 1837 } 1838 1839 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_GET_PUBKEY_INIT: 1840 { 1841 status = intel_fcs_ecdsa_get_pubkey_init(x2, x3, x4, x5, x6, 1842 &mbox_error); 1843 SMC_RET1(handle, status); 1844 } 1845 1846 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_GET_PUBKEY_FINALIZE: 1847 { 1848 status = intel_fcs_ecdsa_get_pubkey_finalize(smc_fid, x1, x2, x3, 1849 x4, (uint32_t *) &x5, &mbox_error); 1850 SMC_RET1(handle, status); 1851 } 1852 1853 case ALTERA_SIP_SMC_ASYNC_FCS_ECDH_REQUEST_INIT: 1854 { 1855 status = intel_fcs_ecdh_request_init(x2, x3, x4, x5, x6, 1856 &mbox_error); 1857 SMC_RET1(handle, status); 1858 } 1859 1860 case ALTERA_SIP_SMC_ASYNC_FCS_ECDH_REQUEST_FINALIZE: 1861 { 1862 uint32_t dest_size = (uint32_t)x7; 1863 1864 NOTICE("MBOX: %s, %d: x7 0x%x, dest_size 0x%x\n", 1865 __func__, __LINE__, (uint32_t)x7, dest_size); 1866 1867 status = intel_fcs_ecdh_request_finalize(smc_fid, x1, x2, x3, 1868 x4, x5, x6, (uint32_t *) &dest_size, 1869 &mbox_error); 1870 SMC_RET1(handle, status); 1871 } 1872 1873 case ALTERA_SIP_SMC_ASYNC_MCTP_MSG: 1874 { 1875 uint32_t *src_addr = (uint32_t *)x2; 1876 uint32_t src_size = (uint32_t)x3; 1877 uint32_t *dst_addr = (uint32_t *)x4; 1878 1879 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1880 GET_JOB_ID(x1), 1881 MBOX_CMD_MCTP_MSG, 1882 src_addr, 1883 src_size / MBOX_WORD_BYTE, 1884 MBOX_CMD_FLAG_CASUAL, 1885 sip_smc_ret_nbytes_cb, 1886 dst_addr, 1887 2); 1888 1889 SMC_RET1(handle, status); 1890 } 1891 1892 case ALTERA_SIP_SMC_ASYNC_FCS_HKDF_REQUEST: 1893 { 1894 status = intel_fcs_hkdf_request(smc_fid, x1, x2, x3, x4, x5, x6, 1895 x7); 1896 SMC_RET1(handle, status); 1897 } 1898 1899 default: 1900 return socfpga_sip_handler(smc_fid, x1, x2, x3, x4, 1901 cookie, handle, flags); 1902 } /* switch (smc_fid) */ 1903 } 1904 #endif 1905 1906 /* 1907 * This function is responsible for handling all SiP calls from the NS world 1908 */ 1909 1910 uintptr_t sip_smc_handler_v1(uint32_t smc_fid, 1911 u_register_t x1, 1912 u_register_t x2, 1913 u_register_t x3, 1914 u_register_t x4, 1915 void *cookie, 1916 void *handle, 1917 u_register_t flags) 1918 { 1919 uint32_t retval = 0, completed_addr[3]; 1920 uint32_t retval2 = 0; 1921 uint32_t mbox_error = 0; 1922 uint32_t err_states = 0; 1923 uint64_t retval64, rsu_respbuf[9]; 1924 uint32_t seu_respbuf[3]; 1925 int status = INTEL_SIP_SMC_STATUS_OK; 1926 int mbox_status; 1927 unsigned int len_in_resp; 1928 u_register_t x5, x6, x7; 1929 1930 switch (smc_fid) { 1931 case SIP_SVC_UID: 1932 /* Return UID to the caller */ 1933 SMC_UUID_RET(handle, intl_svc_uid); 1934 1935 case INTEL_SIP_SMC_FPGA_CONFIG_ISDONE: 1936 status = intel_mailbox_fpga_config_isdone(&err_states); 1937 SMC_RET4(handle, status, err_states, 0, 0); 1938 1939 case INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM: 1940 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 1941 INTEL_SIP_SMC_FPGA_CONFIG_ADDR, 1942 INTEL_SIP_SMC_FPGA_CONFIG_SIZE - 1943 INTEL_SIP_SMC_FPGA_CONFIG_ADDR); 1944 1945 case INTEL_SIP_SMC_FPGA_CONFIG_START: 1946 status = intel_fpga_config_start(x1); 1947 SMC_RET4(handle, status, 0, 0, 0); 1948 1949 case INTEL_SIP_SMC_FPGA_CONFIG_WRITE: 1950 status = intel_fpga_config_write(x1, x2); 1951 SMC_RET4(handle, status, 0, 0, 0); 1952 1953 case INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE: 1954 status = intel_fpga_config_completed_write(completed_addr, 1955 &retval, &rcv_id); 1956 switch (retval) { 1957 case 1: 1958 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 1959 completed_addr[0], 0, 0); 1960 1961 case 2: 1962 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 1963 completed_addr[0], 1964 completed_addr[1], 0); 1965 1966 case 3: 1967 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 1968 completed_addr[0], 1969 completed_addr[1], 1970 completed_addr[2]); 1971 1972 case 0: 1973 SMC_RET4(handle, status, 0, 0, 0); 1974 1975 default: 1976 mailbox_clear_response(); 1977 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR); 1978 } 1979 1980 case INTEL_SIP_SMC_REG_READ: 1981 status = intel_secure_reg_read(x1, &retval); 1982 SMC_RET3(handle, status, retval, x1); 1983 1984 case INTEL_SIP_SMC_REG_WRITE: 1985 status = intel_secure_reg_write(x1, (uint32_t)x2, &retval); 1986 SMC_RET3(handle, status, retval, x1); 1987 1988 case INTEL_SIP_SMC_REG_UPDATE: 1989 status = intel_secure_reg_update(x1, (uint32_t)x2, 1990 (uint32_t)x3, &retval); 1991 SMC_RET3(handle, status, retval, x1); 1992 1993 case INTEL_SIP_SMC_RSU_STATUS: 1994 status = intel_rsu_status(rsu_respbuf, 1995 ARRAY_SIZE(rsu_respbuf)); 1996 if (status) { 1997 SMC_RET1(handle, status); 1998 } else { 1999 SMC_RET4(handle, rsu_respbuf[0], rsu_respbuf[1], 2000 rsu_respbuf[2], rsu_respbuf[3]); 2001 } 2002 2003 case INTEL_SIP_SMC_RSU_UPDATE: 2004 status = intel_rsu_update(x1); 2005 SMC_RET1(handle, status); 2006 2007 case INTEL_SIP_SMC_RSU_NOTIFY: 2008 status = intel_rsu_notify(x1); 2009 SMC_RET1(handle, status); 2010 2011 case INTEL_SIP_SMC_RSU_RETRY_COUNTER: 2012 status = intel_rsu_retry_counter((uint32_t *)rsu_respbuf, 2013 ARRAY_SIZE(rsu_respbuf), &retval); 2014 if (status) { 2015 SMC_RET1(handle, status); 2016 } else { 2017 SMC_RET2(handle, status, retval); 2018 } 2019 2020 case INTEL_SIP_SMC_RSU_DCMF_VERSION: 2021 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 2022 ((uint64_t)rsu_dcmf_ver[1] << 32) | rsu_dcmf_ver[0], 2023 ((uint64_t)rsu_dcmf_ver[3] << 32) | rsu_dcmf_ver[2]); 2024 2025 case INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION: 2026 status = intel_rsu_copy_dcmf_version(x1, x2); 2027 SMC_RET1(handle, status); 2028 2029 case INTEL_SIP_SMC_RSU_GET_DEVICE_INFO: 2030 status = intel_rsu_get_device_info((uint32_t *)rsu_respbuf, 2031 ARRAY_SIZE(rsu_respbuf)); 2032 if (status) { 2033 SMC_RET1(handle, status); 2034 } else { 2035 SMC_RET5(handle, status, rsu_respbuf[0], rsu_respbuf[1], 2036 rsu_respbuf[2], rsu_respbuf[3]); 2037 } 2038 2039 case INTEL_SIP_SMC_RSU_DCMF_STATUS: 2040 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, 2041 ((uint64_t)rsu_dcmf_stat[3] << 48) | 2042 ((uint64_t)rsu_dcmf_stat[2] << 32) | 2043 ((uint64_t)rsu_dcmf_stat[1] << 16) | 2044 rsu_dcmf_stat[0]); 2045 2046 case INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS: 2047 status = intel_rsu_copy_dcmf_status(x1); 2048 SMC_RET1(handle, status); 2049 2050 case INTEL_SIP_SMC_RSU_MAX_RETRY: 2051 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, rsu_max_retry); 2052 2053 case INTEL_SIP_SMC_RSU_COPY_MAX_RETRY: 2054 rsu_max_retry = x1; 2055 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_OK); 2056 2057 case INTEL_SIP_SMC_ECC_DBE: 2058 status = intel_ecc_dbe_notification(x1); 2059 SMC_RET1(handle, status); 2060 2061 case INTEL_SIP_SMC_SERVICE_COMPLETED: 2062 status = intel_smc_service_completed(x1, x2, x3, &rcv_id, 2063 &len_in_resp, &mbox_error); 2064 SMC_RET4(handle, status, mbox_error, x1, len_in_resp); 2065 2066 case INTEL_SIP_SMC_FIRMWARE_VERSION: 2067 status = intel_smc_fw_version(&retval); 2068 SMC_RET2(handle, status, retval); 2069 2070 case INTEL_SIP_SMC_MBOX_SEND_CMD: 2071 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2072 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2073 status = intel_mbox_send_cmd(x1, (uint32_t *)x2, x3, x4, x5, x6, 2074 &mbox_status, &len_in_resp); 2075 SMC_RET3(handle, status, mbox_status, len_in_resp); 2076 2077 case INTEL_SIP_SMC_GET_USERCODE: 2078 status = intel_smc_get_usercode(&retval); 2079 SMC_RET2(handle, status, retval); 2080 2081 case INTEL_SIP_SMC_FCS_CRYPTION: 2082 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2083 2084 if (x1 == FCS_MODE_DECRYPT) { 2085 status = intel_fcs_decryption(x2, x3, x4, x5, &send_id); 2086 } else if (x1 == FCS_MODE_ENCRYPT) { 2087 status = intel_fcs_encryption(x2, x3, x4, x5, &send_id); 2088 } else { 2089 status = INTEL_SIP_SMC_STATUS_REJECTED; 2090 } 2091 2092 SMC_RET3(handle, status, x4, x5); 2093 2094 case INTEL_SIP_SMC_FCS_CRYPTION_EXT: 2095 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2096 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2097 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2098 2099 if (x3 == FCS_MODE_DECRYPT) { 2100 status = intel_fcs_decryption_ext(smc_fid, 0, x1, x2, x4, x5, x6, 2101 (uint32_t *) &x7, &mbox_error, 0, 0, 0); 2102 } else if (x3 == FCS_MODE_ENCRYPT) { 2103 status = intel_fcs_encryption_ext(smc_fid, 0, x1, x2, x4, x5, x6, 2104 (uint32_t *) &x7, &mbox_error, 0, 0); 2105 } else { 2106 status = INTEL_SIP_SMC_STATUS_REJECTED; 2107 } 2108 2109 SMC_RET4(handle, status, mbox_error, x6, x7); 2110 2111 case INTEL_SIP_SMC_FCS_RANDOM_NUMBER: 2112 status = intel_fcs_random_number_gen(x1, &retval64, 2113 &mbox_error); 2114 SMC_RET4(handle, status, mbox_error, x1, retval64); 2115 2116 case INTEL_SIP_SMC_FCS_RANDOM_NUMBER_EXT: 2117 status = intel_fcs_random_number_gen_ext(x1, x2, x3, 2118 &send_id); 2119 SMC_RET1(handle, status); 2120 2121 case INTEL_SIP_SMC_FCS_SEND_CERTIFICATE: 2122 status = intel_fcs_send_cert(smc_fid, 0, x1, x2, &send_id); 2123 SMC_RET1(handle, status); 2124 2125 case INTEL_SIP_SMC_FCS_GET_PROVISION_DATA: 2126 status = intel_fcs_get_provision_data(&send_id); 2127 SMC_RET1(handle, status); 2128 2129 case INTEL_SIP_SMC_FCS_CNTR_SET_PREAUTH: 2130 status = intel_fcs_cntr_set_preauth(smc_fid, 0, x1, x2, x3, 2131 &mbox_error); 2132 SMC_RET2(handle, status, mbox_error); 2133 2134 case INTEL_SIP_SMC_HPS_SET_BRIDGES: 2135 status = intel_hps_set_bridges(x1, x2); 2136 SMC_RET1(handle, status); 2137 2138 case INTEL_SIP_SMC_HWMON_READTEMP: 2139 status = intel_hwmon_readtemp(x1, &retval); 2140 SMC_RET2(handle, status, retval); 2141 2142 case INTEL_SIP_SMC_HWMON_READVOLT: 2143 status = intel_hwmon_readvolt(x1, &retval); 2144 SMC_RET2(handle, status, retval); 2145 2146 case INTEL_SIP_SMC_FCS_PSGSIGMA_TEARDOWN: 2147 status = intel_fcs_sigma_teardown(x1, &mbox_error); 2148 SMC_RET2(handle, status, mbox_error); 2149 2150 case INTEL_SIP_SMC_FCS_CHIP_ID: 2151 status = intel_fcs_chip_id(&retval, &retval2, &mbox_error); 2152 SMC_RET4(handle, status, mbox_error, retval, retval2); 2153 2154 case INTEL_SIP_SMC_FCS_ATTESTATION_SUBKEY: 2155 status = intel_fcs_attestation_subkey(x1, x2, x3, 2156 (uint32_t *) &x4, &mbox_error); 2157 SMC_RET4(handle, status, mbox_error, x3, x4); 2158 2159 case INTEL_SIP_SMC_FCS_ATTESTATION_MEASUREMENTS: 2160 status = intel_fcs_get_measurement(x1, x2, x3, 2161 (uint32_t *) &x4, &mbox_error); 2162 SMC_RET4(handle, status, mbox_error, x3, x4); 2163 2164 case INTEL_SIP_SMC_FCS_GET_ATTESTATION_CERT: 2165 status = intel_fcs_get_attestation_cert(smc_fid, 0, x1, x2, 2166 (uint32_t *) &x3, &mbox_error); 2167 SMC_RET4(handle, status, mbox_error, x2, x3); 2168 2169 case INTEL_SIP_SMC_FCS_CREATE_CERT_ON_RELOAD: 2170 status = intel_fcs_create_cert_on_reload(smc_fid, 0, x1, &mbox_error); 2171 SMC_RET2(handle, status, mbox_error); 2172 2173 case INTEL_SIP_SMC_FCS_OPEN_CS_SESSION: 2174 status = intel_fcs_open_crypto_service_session(&retval, &mbox_error); 2175 SMC_RET3(handle, status, mbox_error, retval); 2176 2177 case INTEL_SIP_SMC_FCS_CLOSE_CS_SESSION: 2178 status = intel_fcs_close_crypto_service_session(x1, &mbox_error); 2179 SMC_RET2(handle, status, mbox_error); 2180 2181 case INTEL_SIP_SMC_FCS_IMPORT_CS_KEY: 2182 status = intel_fcs_import_crypto_service_key(x1, x2, &send_id); 2183 SMC_RET1(handle, status); 2184 2185 case INTEL_SIP_SMC_FCS_EXPORT_CS_KEY: 2186 status = intel_fcs_export_crypto_service_key(x1, x2, x3, 2187 (uint32_t *) &x4, &mbox_error); 2188 SMC_RET4(handle, status, mbox_error, x3, x4); 2189 2190 case INTEL_SIP_SMC_FCS_REMOVE_CS_KEY: 2191 status = intel_fcs_remove_crypto_service_key(x1, x2, 2192 &mbox_error); 2193 SMC_RET2(handle, status, mbox_error); 2194 2195 case INTEL_SIP_SMC_FCS_GET_CS_KEY_INFO: 2196 status = intel_fcs_get_crypto_service_key_info(x1, x2, x3, 2197 (uint32_t *) &x4, &mbox_error); 2198 SMC_RET4(handle, status, mbox_error, x3, x4); 2199 2200 case INTEL_SIP_SMC_FCS_GET_DIGEST_INIT: 2201 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2202 status = intel_fcs_get_digest_init(x1, x2, x3, 2203 x4, x5, &mbox_error); 2204 SMC_RET2(handle, status, mbox_error); 2205 2206 case INTEL_SIP_SMC_FCS_GET_DIGEST_UPDATE: 2207 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2208 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2209 status = intel_fcs_get_digest_update_finalize(smc_fid, 0, x1, x2, 2210 x3, x4, x5, (uint32_t *) &x6, false, 2211 &mbox_error, 0); 2212 SMC_RET4(handle, status, mbox_error, x5, x6); 2213 2214 case INTEL_SIP_SMC_FCS_GET_DIGEST_FINALIZE: 2215 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2216 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2217 status = intel_fcs_get_digest_update_finalize(smc_fid, 0, x1, x2, 2218 x3, x4, x5, (uint32_t *) &x6, true, 2219 &mbox_error, 0); 2220 SMC_RET4(handle, status, mbox_error, x5, x6); 2221 2222 case INTEL_SIP_SMC_FCS_GET_DIGEST_SMMU_UPDATE: 2223 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2224 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2225 status = intel_fcs_get_digest_smmu_update_finalize(x1, x2, x3, 2226 x4, x5, (uint32_t *) &x6, false, 2227 &mbox_error, &send_id); 2228 SMC_RET4(handle, status, mbox_error, x5, x6); 2229 2230 case INTEL_SIP_SMC_FCS_GET_DIGEST_SMMU_FINALIZE: 2231 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2232 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2233 status = intel_fcs_get_digest_smmu_update_finalize(x1, x2, x3, 2234 x4, x5, (uint32_t *) &x6, true, 2235 &mbox_error, &send_id); 2236 SMC_RET4(handle, status, mbox_error, x5, x6); 2237 2238 case INTEL_SIP_SMC_FCS_MAC_VERIFY_INIT: 2239 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2240 status = intel_fcs_mac_verify_init(x1, x2, x3, 2241 x4, x5, &mbox_error); 2242 SMC_RET2(handle, status, mbox_error); 2243 2244 case INTEL_SIP_SMC_FCS_MAC_VERIFY_UPDATE: 2245 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2246 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2247 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2248 status = intel_fcs_mac_verify_update_finalize(smc_fid, 0, x1, x2, 2249 x3, x4, x5, (uint32_t *) &x6, x7, false, 2250 &mbox_error, 0); 2251 SMC_RET4(handle, status, mbox_error, x5, x6); 2252 2253 case INTEL_SIP_SMC_FCS_MAC_VERIFY_FINALIZE: 2254 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2255 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2256 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2257 status = intel_fcs_mac_verify_update_finalize(smc_fid, 0, x1, x2, 2258 x3, x4, x5, (uint32_t *) &x6, x7, true, 2259 &mbox_error, 0); 2260 SMC_RET4(handle, status, mbox_error, x5, x6); 2261 2262 case INTEL_SIP_SMC_FCS_MAC_VERIFY_SMMU_UPDATE: 2263 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2264 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2265 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2266 status = intel_fcs_mac_verify_smmu_update_finalize(x1, x2, x3, 2267 x4, x5, (uint32_t *) &x6, x7, 2268 false, &mbox_error, &send_id); 2269 SMC_RET4(handle, status, mbox_error, x5, x6); 2270 2271 case INTEL_SIP_SMC_FCS_MAC_VERIFY_SMMU_FINALIZE: 2272 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2273 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2274 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2275 status = intel_fcs_mac_verify_smmu_update_finalize(x1, x2, x3, 2276 x4, x5, (uint32_t *) &x6, x7, 2277 true, &mbox_error, &send_id); 2278 SMC_RET4(handle, status, mbox_error, x5, x6); 2279 2280 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_INIT: 2281 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2282 status = intel_fcs_ecdsa_sha2_data_sign_init(x1, x2, x3, 2283 x4, x5, &mbox_error); 2284 SMC_RET2(handle, status, mbox_error); 2285 2286 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_UPDATE: 2287 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2288 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2289 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(smc_fid, 2290 0, x1, x2, x3, x4, x5, (uint32_t *) &x6, 2291 false, &mbox_error, 0); 2292 SMC_RET4(handle, status, mbox_error, x5, x6); 2293 2294 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE: 2295 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2296 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2297 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(smc_fid, 2298 0, x1, x2, x3, x4, x5, (uint32_t *) &x6, 2299 true, &mbox_error, 0); 2300 SMC_RET4(handle, status, mbox_error, x5, x6); 2301 2302 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_UPDATE: 2303 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2304 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2305 status = intel_fcs_ecdsa_sha2_data_sign_smmu_update_finalize(x1, 2306 x2, x3, x4, x5, (uint32_t *) &x6, false, 2307 &mbox_error, &send_id); 2308 SMC_RET4(handle, status, mbox_error, x5, x6); 2309 2310 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_FINALIZE: 2311 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2312 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2313 status = intel_fcs_ecdsa_sha2_data_sign_smmu_update_finalize(x1, 2314 x2, x3, x4, x5, (uint32_t *) &x6, true, 2315 &mbox_error, &send_id); 2316 SMC_RET4(handle, status, mbox_error, x5, x6); 2317 2318 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_INIT: 2319 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2320 status = intel_fcs_ecdsa_hash_sign_init(x1, x2, x3, 2321 x4, x5, &mbox_error); 2322 SMC_RET2(handle, status, mbox_error); 2323 2324 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_FINALIZE: 2325 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2326 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2327 status = intel_fcs_ecdsa_hash_sign_finalize(smc_fid, 0, x1, x2, 2328 x3, x4, x5, (uint32_t *) &x6, 2329 &mbox_error); 2330 SMC_RET4(handle, status, mbox_error, x5, x6); 2331 2332 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_INIT: 2333 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2334 status = intel_fcs_ecdsa_hash_sig_verify_init(x1, x2, x3, 2335 x4, x5, &mbox_error); 2336 SMC_RET2(handle, status, mbox_error); 2337 2338 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_FINALIZE: 2339 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2340 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2341 status = intel_fcs_ecdsa_hash_sig_verify_finalize(smc_fid, 0, x1, 2342 x2, x3, x4, x5, (uint32_t *) &x6, 2343 &mbox_error); 2344 SMC_RET4(handle, status, mbox_error, x5, x6); 2345 2346 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_INIT: 2347 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2348 status = intel_fcs_ecdsa_sha2_data_sig_verify_init(x1, x2, x3, 2349 x4, x5, &mbox_error); 2350 SMC_RET2(handle, status, mbox_error); 2351 2352 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_UPDATE: 2353 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2354 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2355 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2356 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize( 2357 smc_fid, 0, x1, x2, x3, x4, x5, 2358 (uint32_t *) &x6, x7, false, 2359 &mbox_error, 0); 2360 SMC_RET4(handle, status, mbox_error, x5, x6); 2361 2362 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_UPDATE: 2363 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2364 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2365 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2366 status = intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize( 2367 x1, x2, x3, x4, x5, (uint32_t *) &x6, 2368 x7, false, &mbox_error, &send_id); 2369 SMC_RET4(handle, status, mbox_error, x5, x6); 2370 2371 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_FINALIZE: 2372 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2373 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2374 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2375 status = intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize( 2376 x1, x2, x3, x4, x5, (uint32_t *) &x6, 2377 x7, true, &mbox_error, &send_id); 2378 SMC_RET4(handle, status, mbox_error, x5, x6); 2379 2380 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE: 2381 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2382 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2383 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2384 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize( 2385 smc_fid, 0, x1, x2, x3, x4, x5, 2386 (uint32_t *) &x6, x7, true, 2387 &mbox_error, 0); 2388 SMC_RET4(handle, status, mbox_error, x5, x6); 2389 2390 case INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_INIT: 2391 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2392 status = intel_fcs_ecdsa_get_pubkey_init(x1, x2, x3, 2393 x4, x5, &mbox_error); 2394 SMC_RET2(handle, status, mbox_error); 2395 2396 case INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_FINALIZE: 2397 status = intel_fcs_ecdsa_get_pubkey_finalize( 2398 INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_FINALIZE, 0, 2399 x1, x2, x3, (uint32_t *) &x4, &mbox_error); 2400 SMC_RET4(handle, status, mbox_error, x3, x4); 2401 2402 case INTEL_SIP_SMC_FCS_ECDH_REQUEST_INIT: 2403 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2404 status = intel_fcs_ecdh_request_init(x1, x2, x3, 2405 x4, x5, &mbox_error); 2406 SMC_RET2(handle, status, mbox_error); 2407 2408 case INTEL_SIP_SMC_FCS_ECDH_REQUEST_FINALIZE: 2409 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2410 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2411 status = intel_fcs_ecdh_request_finalize(smc_fid, 0, x1, x2, x3, 2412 x4, x5, (uint32_t *) &x6, &mbox_error); 2413 SMC_RET4(handle, status, mbox_error, x5, x6); 2414 2415 case INTEL_SIP_SMC_FCS_AES_CRYPT_INIT: 2416 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2417 status = intel_fcs_aes_crypt_init(x1, x2, x3, x4, x5, 2418 &mbox_error); 2419 SMC_RET2(handle, status, mbox_error); 2420 2421 case INTEL_SIP_SMC_FCS_AES_CRYPT_UPDATE: 2422 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2423 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2424 status = intel_fcs_aes_crypt_update_finalize(smc_fid, 0, x1, x2, 2425 x3, x4, x5, x6, 0, false, &send_id, 0, 0); 2426 SMC_RET1(handle, status); 2427 2428 case INTEL_SIP_SMC_FCS_AES_CRYPT_FINALIZE: 2429 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2430 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2431 status = intel_fcs_aes_crypt_update_finalize(smc_fid, 0, x1, x2, 2432 x3, x4, x5, x6, 0, true, &send_id, 0, 0); 2433 SMC_RET1(handle, status); 2434 2435 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 2436 case INTEL_SIP_SMC_FCS_SDM_REMAPPER_CONFIG: 2437 status = intel_smmu_hps_remapper_config(x1); 2438 SMC_RET1(handle, status); 2439 #endif 2440 2441 case INTEL_SIP_SMC_GET_ROM_PATCH_SHA384: 2442 status = intel_fcs_get_rom_patch_sha384(x1, &retval64, 2443 &mbox_error); 2444 SMC_RET4(handle, status, mbox_error, x1, retval64); 2445 2446 case INTEL_SIP_SMC_SVC_VERSION: 2447 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 2448 SIP_SVC_VERSION_MAJOR, 2449 SIP_SVC_VERSION_MINOR); 2450 2451 case INTEL_SIP_SMC_SEU_ERR_STATUS: 2452 status = intel_sdm_seu_err_read(seu_respbuf, 2453 ARRAY_SIZE(seu_respbuf)); 2454 if (status) { 2455 SMC_RET1(handle, status); 2456 } else { 2457 SMC_RET3(handle, seu_respbuf[0], seu_respbuf[1], seu_respbuf[2]); 2458 } 2459 2460 case INTEL_SIP_SMC_SAFE_INJECT_SEU_ERR: 2461 status = intel_sdm_safe_inject_seu_err((uint32_t *)&x1, (uint32_t)x2); 2462 SMC_RET1(handle, status); 2463 2464 case INTEL_SIP_SMC_ATF_BUILD_VER: 2465 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, VERSION_MAJOR, 2466 VERSION_MINOR, VERSION_PATCH); 2467 2468 default: 2469 return socfpga_sip_handler(smc_fid, x1, x2, x3, x4, 2470 cookie, handle, flags); 2471 } 2472 } 2473 2474 uintptr_t sip_smc_handler(uint32_t smc_fid, 2475 u_register_t x1, 2476 u_register_t x2, 2477 u_register_t x3, 2478 u_register_t x4, 2479 void *cookie, 2480 void *handle, 2481 u_register_t flags) 2482 { 2483 uint32_t cmd = smc_fid & INTEL_SIP_SMC_CMD_MASK; 2484 2485 if (cmd >= INTEL_SIP_SMC_CMD_V2_RANGE_BEGIN && 2486 cmd <= INTEL_SIP_SMC_CMD_V2_RANGE_END) { 2487 return sip_smc_handler_v2(smc_fid, x1, x2, x3, x4, 2488 cookie, handle, flags); 2489 } 2490 #if SIP_SVC_V3 2491 else if ((cmd >= INTEL_SIP_SMC_CMD_V3_RANGE_BEGIN) && 2492 (cmd <= INTEL_SIP_SMC_CMD_V3_RANGE_END)) { 2493 uintptr_t ret = sip_smc_handler_v3(smc_fid, x1, x2, x3, x4, 2494 cookie, handle, flags); 2495 return ret; 2496 } 2497 #endif 2498 else { 2499 return sip_smc_handler_v1(smc_fid, x1, x2, x3, x4, 2500 cookie, handle, flags); 2501 } 2502 } 2503 2504 DECLARE_RT_SVC( 2505 socfpga_sip_svc, 2506 OEN_SIP_START, 2507 OEN_SIP_END, 2508 SMC_TYPE_FAST, 2509 NULL, 2510 sip_smc_handler 2511 ); 2512 2513 DECLARE_RT_SVC( 2514 socfpga_sip_svc_std, 2515 OEN_SIP_START, 2516 OEN_SIP_END, 2517 SMC_TYPE_YIELD, 2518 NULL, 2519 sip_smc_handler 2520 ); 2521