1 /* 2 * Copyright (c) 2019-2025, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. 4 * Copyright (c) 2024-2025, Altera Corporation. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #include <assert.h> 10 #include <common/debug.h> 11 #include <common/runtime_svc.h> 12 #include <drivers/delay_timer.h> 13 #include <lib/mmio.h> 14 #include <tools_share/uuid.h> 15 16 #include "lib/utils/alignment_utils.h" 17 #include "socfpga_fcs.h" 18 #include "socfpga_mailbox.h" 19 #include "socfpga_plat_def.h" 20 #include "socfpga_reset_manager.h" 21 #include "socfpga_sip_svc.h" 22 #include "socfpga_system_manager.h" 23 24 /* Total buffer the driver can hold */ 25 #define FPGA_CONFIG_BUFFER_SIZE 4 26 27 static config_type request_type = NO_REQUEST; 28 static int current_block, current_buffer; 29 static int read_block, max_blocks; 30 static uint32_t send_id, rcv_id; 31 static uint32_t bytes_per_block, blocks_submitted; 32 static bool bridge_disable; 33 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 34 static uint32_t g_remapper_bypass; 35 #endif 36 37 /* RSU static variables */ 38 static uint32_t rsu_dcmf_ver[4] = {0}; 39 static uint16_t rsu_dcmf_stat[4] = {0}; 40 static uint32_t rsu_max_retry; 41 42 /* SiP Service UUID */ 43 DEFINE_SVC_UUID2(intl_svc_uid, 44 0xa85273b0, 0xe85a, 0x4862, 0xa6, 0x2a, 45 0xfa, 0x88, 0x88, 0x17, 0x68, 0x81); 46 47 static uint64_t socfpga_sip_handler(uint32_t smc_fid, 48 uint64_t x1, 49 uint64_t x2, 50 uint64_t x3, 51 uint64_t x4, 52 void *cookie, 53 void *handle, 54 uint64_t flags) 55 { 56 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); 57 SMC_RET1(handle, SMC_UNK); 58 } 59 60 struct fpga_config_info fpga_config_buffers[FPGA_CONFIG_BUFFER_SIZE]; 61 62 static int intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer) 63 { 64 uint32_t args[3]; 65 66 while (max_blocks > 0 && buffer->size > buffer->size_written) { 67 args[0] = (1<<8); 68 args[1] = buffer->addr + buffer->size_written; 69 if (buffer->size - buffer->size_written <= bytes_per_block) { 70 args[2] = buffer->size - buffer->size_written; 71 current_buffer++; 72 current_buffer %= FPGA_CONFIG_BUFFER_SIZE; 73 } else { 74 args[2] = bytes_per_block; 75 } 76 77 buffer->size_written += args[2]; 78 mailbox_send_cmd_async(&send_id, MBOX_RECONFIG_DATA, args, 79 3U, CMD_INDIRECT); 80 81 buffer->subblocks_sent++; 82 max_blocks--; 83 } 84 85 return !max_blocks; 86 } 87 88 static int intel_fpga_sdm_write_all(void) 89 { 90 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 91 if (intel_fpga_sdm_write_buffer( 92 &fpga_config_buffers[current_buffer])) { 93 break; 94 } 95 } 96 return 0; 97 } 98 99 static uint32_t intel_mailbox_fpga_config_isdone(uint32_t *err_states) 100 { 101 uint32_t ret; 102 103 if (err_states == NULL) 104 return INTEL_SIP_SMC_STATUS_REJECTED; 105 106 switch (request_type) { 107 case RECONFIGURATION: 108 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, 109 true, err_states); 110 break; 111 case BITSTREAM_AUTH: 112 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, 113 false, err_states); 114 break; 115 default: 116 ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS, 117 false, err_states); 118 break; 119 } 120 121 if (ret != 0U) { 122 if (ret == MBOX_CFGSTAT_STATE_CONFIG) { 123 return INTEL_SIP_SMC_STATUS_BUSY; 124 } else { 125 request_type = NO_REQUEST; 126 return INTEL_SIP_SMC_STATUS_ERROR; 127 } 128 } 129 130 if (bridge_disable != 0U) { 131 socfpga_bridges_enable(~0); /* Enable bridge */ 132 bridge_disable = false; 133 } 134 request_type = NO_REQUEST; 135 136 return INTEL_SIP_SMC_STATUS_OK; 137 } 138 139 static int mark_last_buffer_xfer_completed(uint32_t *buffer_addr_completed) 140 { 141 int i; 142 143 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 144 if (fpga_config_buffers[i].block_number == current_block) { 145 fpga_config_buffers[i].subblocks_sent--; 146 if (fpga_config_buffers[i].subblocks_sent == 0 147 && fpga_config_buffers[i].size <= 148 fpga_config_buffers[i].size_written) { 149 fpga_config_buffers[i].write_requested = 0; 150 current_block++; 151 *buffer_addr_completed = 152 fpga_config_buffers[i].addr; 153 return 0; 154 } 155 } 156 } 157 158 return -1; 159 } 160 161 static int intel_fpga_config_completed_write(uint32_t *completed_addr, 162 uint32_t *count, uint32_t *job_id) 163 { 164 uint32_t resp[5]; 165 unsigned int resp_len = ARRAY_SIZE(resp); 166 int status = INTEL_SIP_SMC_STATUS_OK; 167 int all_completed = 1; 168 *count = 0; 169 170 while (*count < 3) { 171 172 status = mailbox_read_response(job_id, 173 resp, &resp_len); 174 175 if (status < 0) { 176 break; 177 } 178 179 max_blocks++; 180 181 if (mark_last_buffer_xfer_completed( 182 &completed_addr[*count]) == 0) { 183 *count = *count + 1; 184 } else { 185 break; 186 } 187 } 188 189 if (*count <= 0) { 190 if (status != MBOX_NO_RESPONSE && 191 status != MBOX_TIMEOUT && resp_len != 0) { 192 mailbox_clear_response(); 193 request_type = NO_REQUEST; 194 return INTEL_SIP_SMC_STATUS_ERROR; 195 } 196 197 *count = 0; 198 } 199 200 intel_fpga_sdm_write_all(); 201 202 if (*count > 0) { 203 status = INTEL_SIP_SMC_STATUS_OK; 204 } else if (*count == 0) { 205 status = INTEL_SIP_SMC_STATUS_BUSY; 206 } 207 208 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 209 if (fpga_config_buffers[i].write_requested != 0) { 210 all_completed = 0; 211 break; 212 } 213 } 214 215 if (all_completed == 1) { 216 return INTEL_SIP_SMC_STATUS_OK; 217 } 218 219 return status; 220 } 221 222 static int intel_fpga_config_start(uint32_t flag) 223 { 224 uint32_t argument = 0x1; 225 uint32_t response[3]; 226 int status = 0; 227 unsigned int size = 0; 228 unsigned int resp_len = ARRAY_SIZE(response); 229 230 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 231 /* 232 * To trigger isolation 233 * FPGA configuration complete signal should be de-asserted 234 */ 235 INFO("SOCFPGA: Request SDM to trigger isolation\n"); 236 status = mailbox_send_fpga_config_comp(); 237 238 if (status < 0) { 239 INFO("SOCFPGA: Isolation for FPGA configuration complete is not executed\n"); 240 } 241 #endif 242 243 request_type = RECONFIGURATION; 244 245 if (!CONFIG_TEST_FLAG(flag, PARTIAL_CONFIG)) { 246 bridge_disable = true; 247 } 248 249 if (CONFIG_TEST_FLAG(flag, AUTHENTICATION)) { 250 size = 1; 251 bridge_disable = false; 252 request_type = BITSTREAM_AUTH; 253 } 254 255 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 256 intel_smmu_hps_remapper_init(0U); 257 #endif 258 259 mailbox_clear_response(); 260 261 mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_CANCEL, NULL, 0U, 262 CMD_CASUAL, NULL, NULL); 263 264 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_RECONFIG, &argument, size, 265 CMD_CASUAL, response, &resp_len); 266 267 if (status < 0) { 268 bridge_disable = false; 269 request_type = NO_REQUEST; 270 return INTEL_SIP_SMC_STATUS_ERROR; 271 } 272 273 max_blocks = response[0]; 274 bytes_per_block = response[1]; 275 276 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 277 fpga_config_buffers[i].size = 0; 278 fpga_config_buffers[i].size_written = 0; 279 fpga_config_buffers[i].addr = 0; 280 fpga_config_buffers[i].write_requested = 0; 281 fpga_config_buffers[i].block_number = 0; 282 fpga_config_buffers[i].subblocks_sent = 0; 283 } 284 285 blocks_submitted = 0; 286 current_block = 0; 287 read_block = 0; 288 current_buffer = 0; 289 290 /* Disable bridge on full reconfiguration */ 291 if (bridge_disable) { 292 socfpga_bridges_disable(~0); 293 } 294 295 return INTEL_SIP_SMC_STATUS_OK; 296 } 297 298 static bool is_fpga_config_buffer_full(void) 299 { 300 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 301 if (!fpga_config_buffers[i].write_requested) { 302 return false; 303 } 304 } 305 return true; 306 } 307 308 bool is_address_in_ddr_range(uint64_t addr, uint64_t size) 309 { 310 uint128_t dram_max_sz = (uint128_t)DRAM_BASE + (uint128_t)DRAM_SIZE; 311 uint128_t dram_region_end = (uint128_t)addr + (uint128_t)size; 312 313 if (!addr && !size) { 314 return true; 315 } 316 if (size > (UINT64_MAX - addr)) { 317 return false; 318 } 319 if (addr < BL31_LIMIT) { 320 return false; 321 } 322 if (dram_region_end > dram_max_sz) { 323 return false; 324 } 325 326 return true; 327 } 328 329 static uint32_t intel_fpga_config_write(uint64_t mem, uint64_t size) 330 { 331 int i; 332 333 intel_fpga_sdm_write_all(); 334 335 if (!is_address_in_ddr_range(mem, size) || 336 is_fpga_config_buffer_full()) { 337 return INTEL_SIP_SMC_STATUS_REJECTED; 338 } 339 340 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 341 intel_smmu_hps_remapper_init(&mem); 342 #endif 343 344 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 345 int j = (i + current_buffer) % FPGA_CONFIG_BUFFER_SIZE; 346 347 if (!fpga_config_buffers[j].write_requested) { 348 fpga_config_buffers[j].addr = mem; 349 fpga_config_buffers[j].size = size; 350 fpga_config_buffers[j].size_written = 0; 351 fpga_config_buffers[j].write_requested = 1; 352 fpga_config_buffers[j].block_number = 353 blocks_submitted++; 354 fpga_config_buffers[j].subblocks_sent = 0; 355 break; 356 } 357 } 358 359 if (is_fpga_config_buffer_full()) { 360 return INTEL_SIP_SMC_STATUS_BUSY; 361 } 362 363 return INTEL_SIP_SMC_STATUS_OK; 364 } 365 366 static int is_out_of_sec_range(uint64_t reg_addr) 367 { 368 #if DEBUG 369 return 0; 370 #endif 371 372 #if PLATFORM_MODEL != PLAT_SOCFPGA_AGILEX5 373 switch (reg_addr) { 374 case(0xF8011100): /* ECCCTRL1 */ 375 case(0xF8011104): /* ECCCTRL2 */ 376 case(0xF8011110): /* ERRINTEN */ 377 case(0xF8011114): /* ERRINTENS */ 378 case(0xF8011118): /* ERRINTENR */ 379 case(0xF801111C): /* INTMODE */ 380 case(0xF8011120): /* INTSTAT */ 381 case(0xF8011124): /* DIAGINTTEST */ 382 case(0xF801112C): /* DERRADDRA */ 383 case(0xFA000000): /* SMMU SCR0 */ 384 case(0xFA000004): /* SMMU SCR1 */ 385 case(0xFA000400): /* SMMU NSCR0 */ 386 case(0xFA004000): /* SMMU SSD0_REG */ 387 case(0xFA000820): /* SMMU SMR8 */ 388 case(0xFA000c20): /* SMMU SCR8 */ 389 case(0xFA028000): /* SMMU CB8_SCTRL */ 390 case(0xFA001020): /* SMMU CBAR8 */ 391 case(0xFA028030): /* SMMU TCR_LPAE */ 392 case(0xFA028020): /* SMMU CB8_TTBR0_LOW */ 393 case(0xFA028024): /* SMMU CB8_PRRR_HIGH */ 394 case(0xFA028038): /* SMMU CB8_PRRR_MIR0 */ 395 case(0xFA02803C): /* SMMU CB8_PRRR_MIR1 */ 396 case(0xFA028010): /* SMMU_CB8)TCR2 */ 397 case(0xFFD080A4): /* SDM SMMU STREAM ID REG */ 398 case(0xFA001820): /* SMMU_CBA2R8 */ 399 case(0xFA000074): /* SMMU_STLBGSTATUS */ 400 case(0xFA0287F4): /* SMMU_CB8_TLBSTATUS */ 401 case(0xFA000060): /* SMMU_STLBIALL */ 402 case(0xFA000070): /* SMMU_STLBGSYNC */ 403 case(0xFA028618): /* CB8_TLBALL */ 404 case(0xFA0287F0): /* CB8_TLBSYNC */ 405 case(0xFFD12028): /* SDMMCGRP_CTRL */ 406 case(0xFFD12044): /* EMAC0 */ 407 case(0xFFD12048): /* EMAC1 */ 408 case(0xFFD1204C): /* EMAC2 */ 409 case(0xFFD12090): /* ECC_INT_MASK_VALUE */ 410 case(0xFFD12094): /* ECC_INT_MASK_SET */ 411 case(0xFFD12098): /* ECC_INT_MASK_CLEAR */ 412 case(0xFFD1209C): /* ECC_INTSTATUS_SERR */ 413 case(0xFFD120A0): /* ECC_INTSTATUS_DERR */ 414 case(0xFFD120C0): /* NOC_TIMEOUT */ 415 case(0xFFD120C4): /* NOC_IDLEREQ_SET */ 416 case(0xFFD120C8): /* NOC_IDLEREQ_CLR */ 417 case(0xFFD120D0): /* NOC_IDLEACK */ 418 case(0xFFD120D4): /* NOC_IDLESTATUS */ 419 case(0xFFD12200): /* BOOT_SCRATCH_COLD0 */ 420 case(0xFFD12204): /* BOOT_SCRATCH_COLD1 */ 421 case(0xFFD12220): /* BOOT_SCRATCH_COLD8 */ 422 case(0xFFD12224): /* BOOT_SCRATCH_COLD9 */ 423 return 0; 424 #else 425 switch (reg_addr) { 426 427 case(0xF8011104): /* ECCCTRL2 */ 428 case(0xFFD12028): /* SDMMCGRP_CTRL */ 429 case(0xFFD120C4): /* NOC_IDLEREQ_SET */ 430 case(0xFFD120C8): /* NOC_IDLEREQ_CLR */ 431 case(0xFFD120D0): /* NOC_IDLEACK */ 432 433 434 case(SOCFPGA_MEMCTRL(ECCCTRL1)): /* ECCCTRL1 */ 435 case(SOCFPGA_MEMCTRL(ERRINTEN)): /* ERRINTEN */ 436 case(SOCFPGA_MEMCTRL(ERRINTENS)): /* ERRINTENS */ 437 case(SOCFPGA_MEMCTRL(ERRINTENR)): /* ERRINTENR */ 438 case(SOCFPGA_MEMCTRL(INTMODE)): /* INTMODE */ 439 case(SOCFPGA_MEMCTRL(INTSTAT)): /* INTSTAT */ 440 case(SOCFPGA_MEMCTRL(DIAGINTTEST)): /* DIAGINTTEST */ 441 case(SOCFPGA_MEMCTRL(DERRADDRA)): /* DERRADDRA */ 442 443 case(SOCFPGA_ECC_QSPI(INITSTAT)): /* ECC_QSPI_INITSTAT */ 444 case(SOCFPGA_SYSMGR(EMAC_0)): /* EMAC0 */ 445 case(SOCFPGA_SYSMGR(EMAC_1)): /* EMAC1 */ 446 case(SOCFPGA_SYSMGR(EMAC_2)): /* EMAC2 */ 447 case(SOCFPGA_SYSMGR(ECC_INTMASK_VALUE)): /* ECC_INT_MASK_VALUE */ 448 case(SOCFPGA_SYSMGR(ECC_INTMASK_SET)): /* ECC_INT_MASK_SET */ 449 case(SOCFPGA_SYSMGR(ECC_INTMASK_CLR)): /* ECC_INT_MASK_CLEAR */ 450 case(SOCFPGA_SYSMGR(ECC_INTMASK_SERR)): /* ECC_INTSTATUS_SERR */ 451 case(SOCFPGA_SYSMGR(ECC_INTMASK_DERR)): /* ECC_INTSTATUS_DERR */ 452 case(SOCFPGA_SYSMGR(NOC_TIMEOUT)): /* NOC_TIMEOUT */ 453 case(SOCFPGA_SYSMGR(NOC_IDLESTATUS)): /* NOC_IDLESTATUS */ 454 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_0)): /* BOOT_SCRATCH_COLD0 */ 455 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_1)): /* BOOT_SCRATCH_COLD1 */ 456 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_8)): /* BOOT_SCRATCH_COLD8 */ 457 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_9)): /* BOOT_SCRATCH_COLD9 */ 458 #endif 459 case(SOCFPGA_ECC_QSPI(CTRL)): /* ECC_QSPI_CTRL */ 460 case(SOCFPGA_ECC_QSPI(ERRINTEN)): /* ECC_QSPI_ERRINTEN */ 461 case(SOCFPGA_ECC_QSPI(ERRINTENS)): /* ECC_QSPI_ERRINTENS */ 462 case(SOCFPGA_ECC_QSPI(ERRINTENR)): /* ECC_QSPI_ERRINTENR */ 463 case(SOCFPGA_ECC_QSPI(INTMODE)): /* ECC_QSPI_INTMODE */ 464 case(SOCFPGA_ECC_QSPI(ECC_ACCCTRL)): /* ECC_QSPI_ECC_ACCCTRL */ 465 case(SOCFPGA_ECC_QSPI(ECC_STARTACC)): /* ECC_QSPI_ECC_STARTACC */ 466 case(SOCFPGA_ECC_QSPI(ECC_WDCTRL)): /* ECC_QSPI_ECC_WDCTRL */ 467 case(SOCFPGA_ECC_QSPI(INTSTAT)): /* ECC_QSPI_INTSTAT */ 468 case(SOCFPGA_ECC_QSPI(INTTEST)): /* ECC_QSPI_INTMODE */ 469 return 0; 470 471 default: 472 break; 473 } 474 475 return -1; 476 } 477 478 /* Secure register access */ 479 uint32_t intel_secure_reg_read(uint64_t reg_addr, uint32_t *retval) 480 { 481 if (is_out_of_sec_range(reg_addr)) { 482 return INTEL_SIP_SMC_STATUS_ERROR; 483 } 484 485 *retval = mmio_read_32(reg_addr); 486 487 return INTEL_SIP_SMC_STATUS_OK; 488 } 489 490 uint32_t intel_secure_reg_write(uint64_t reg_addr, uint32_t val, 491 uint32_t *retval) 492 { 493 if (is_out_of_sec_range(reg_addr)) { 494 return INTEL_SIP_SMC_STATUS_ERROR; 495 } 496 497 switch (reg_addr) { 498 case(SOCFPGA_ECC_QSPI(INTSTAT)): /* ECC_QSPI_INTSTAT */ 499 case(SOCFPGA_ECC_QSPI(INTTEST)): /* ECC_QSPI_INTMODE */ 500 mmio_write_16(reg_addr, val); 501 break; 502 default: 503 mmio_write_32(reg_addr, val); 504 break; 505 } 506 507 return intel_secure_reg_read(reg_addr, retval); 508 } 509 510 uint32_t intel_secure_reg_update(uint64_t reg_addr, uint32_t mask, 511 uint32_t val, uint32_t *retval) 512 { 513 if (!intel_secure_reg_read(reg_addr, retval)) { 514 *retval &= ~mask; 515 *retval |= val & mask; 516 return intel_secure_reg_write(reg_addr, *retval, retval); 517 } 518 519 return INTEL_SIP_SMC_STATUS_ERROR; 520 } 521 522 /* Intel Remote System Update (RSU) services */ 523 uint64_t intel_rsu_update_address; 524 525 static uint32_t intel_rsu_status(uint64_t *respbuf, unsigned int respbuf_sz) 526 { 527 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) { 528 return INTEL_SIP_SMC_RSU_ERROR; 529 } 530 531 return INTEL_SIP_SMC_STATUS_OK; 532 } 533 534 static uint32_t intel_rsu_get_device_info(uint32_t *respbuf, 535 unsigned int respbuf_sz) 536 { 537 if (mailbox_rsu_get_device_info((uint32_t *)respbuf, respbuf_sz) < 0) { 538 return INTEL_SIP_SMC_RSU_ERROR; 539 } 540 541 return INTEL_SIP_SMC_STATUS_OK; 542 } 543 544 uint32_t intel_rsu_update(uint64_t update_address) 545 { 546 if (update_address > SIZE_MAX) { 547 return INTEL_SIP_SMC_STATUS_REJECTED; 548 } 549 550 intel_rsu_update_address = update_address; 551 return INTEL_SIP_SMC_STATUS_OK; 552 } 553 554 static uint32_t intel_rsu_notify(uint32_t execution_stage) 555 { 556 if (mailbox_hps_stage_notify(execution_stage) < 0) { 557 return INTEL_SIP_SMC_RSU_ERROR; 558 } 559 560 return INTEL_SIP_SMC_STATUS_OK; 561 } 562 563 static uint32_t intel_rsu_retry_counter(uint32_t *respbuf, uint32_t respbuf_sz, 564 uint32_t *ret_stat) 565 { 566 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) { 567 return INTEL_SIP_SMC_RSU_ERROR; 568 } 569 570 *ret_stat = respbuf[8]; 571 return INTEL_SIP_SMC_STATUS_OK; 572 } 573 574 static uint32_t intel_rsu_copy_dcmf_version(uint64_t dcmf_ver_1_0, 575 uint64_t dcmf_ver_3_2) 576 { 577 rsu_dcmf_ver[0] = dcmf_ver_1_0; 578 rsu_dcmf_ver[1] = dcmf_ver_1_0 >> 32; 579 rsu_dcmf_ver[2] = dcmf_ver_3_2; 580 rsu_dcmf_ver[3] = dcmf_ver_3_2 >> 32; 581 582 return INTEL_SIP_SMC_STATUS_OK; 583 } 584 585 static uint32_t intel_rsu_copy_dcmf_status(uint64_t dcmf_stat) 586 { 587 rsu_dcmf_stat[0] = 0xFFFF & (dcmf_stat >> (0 * 16)); 588 rsu_dcmf_stat[1] = 0xFFFF & (dcmf_stat >> (1 * 16)); 589 rsu_dcmf_stat[2] = 0xFFFF & (dcmf_stat >> (2 * 16)); 590 rsu_dcmf_stat[3] = 0xFFFF & (dcmf_stat >> (3 * 16)); 591 592 return INTEL_SIP_SMC_STATUS_OK; 593 } 594 595 /* Intel HWMON services */ 596 static uint32_t intel_hwmon_readtemp(uint32_t chan, uint32_t *retval) 597 { 598 if (mailbox_hwmon_readtemp(chan, retval) < 0) { 599 return INTEL_SIP_SMC_STATUS_ERROR; 600 } 601 602 return INTEL_SIP_SMC_STATUS_OK; 603 } 604 605 static uint32_t intel_hwmon_readvolt(uint32_t chan, uint32_t *retval) 606 { 607 if (mailbox_hwmon_readvolt(chan, retval) < 0) { 608 return INTEL_SIP_SMC_STATUS_ERROR; 609 } 610 611 return INTEL_SIP_SMC_STATUS_OK; 612 } 613 614 /* Mailbox services */ 615 static uint32_t intel_smc_fw_version(uint32_t *fw_version) 616 { 617 int status; 618 unsigned int resp_len = CONFIG_STATUS_WORD_SIZE; 619 uint32_t resp_data[CONFIG_STATUS_WORD_SIZE] = {0U}; 620 621 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CONFIG_STATUS, NULL, 0U, 622 CMD_CASUAL, resp_data, &resp_len); 623 624 if (status < 0) { 625 return INTEL_SIP_SMC_STATUS_ERROR; 626 } 627 628 if (resp_len <= CONFIG_STATUS_FW_VER_OFFSET) { 629 return INTEL_SIP_SMC_STATUS_ERROR; 630 } 631 632 *fw_version = resp_data[CONFIG_STATUS_FW_VER_OFFSET] & CONFIG_STATUS_FW_VER_MASK; 633 634 return INTEL_SIP_SMC_STATUS_OK; 635 } 636 637 static uint32_t intel_mbox_send_cmd(uint32_t cmd, uint32_t *args, 638 unsigned int len, uint32_t urgent, uint64_t response, 639 unsigned int resp_len, int *mbox_status, 640 unsigned int *len_in_resp) 641 { 642 *len_in_resp = 0; 643 *mbox_status = GENERIC_RESPONSE_ERROR; 644 645 if (!is_address_in_ddr_range((uint64_t)args, sizeof(uint32_t) * len)) { 646 return INTEL_SIP_SMC_STATUS_REJECTED; 647 } 648 649 int status = mailbox_send_cmd(MBOX_JOB_ID, cmd, args, len, urgent, 650 (uint32_t *) response, &resp_len); 651 652 if (status < 0) { 653 *mbox_status = -status; 654 return INTEL_SIP_SMC_STATUS_ERROR; 655 } 656 657 *mbox_status = 0; 658 *len_in_resp = resp_len; 659 660 flush_dcache_range(response, resp_len * MBOX_WORD_BYTE); 661 662 return INTEL_SIP_SMC_STATUS_OK; 663 } 664 665 static int intel_smc_get_usercode(uint32_t *user_code) 666 { 667 int status; 668 unsigned int resp_len = sizeof(user_code) / MBOX_WORD_BYTE; 669 670 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_GET_USERCODE, NULL, 671 0U, CMD_CASUAL, user_code, &resp_len); 672 673 if (status < 0) { 674 return INTEL_SIP_SMC_STATUS_ERROR; 675 } 676 677 return INTEL_SIP_SMC_STATUS_OK; 678 } 679 680 uint32_t intel_smc_service_completed(uint64_t addr, uint32_t size, 681 uint32_t mode, uint32_t *job_id, 682 uint32_t *ret_size, uint32_t *mbox_error) 683 { 684 int status = 0; 685 uint32_t resp_len = size / MBOX_WORD_BYTE; 686 687 if (resp_len > MBOX_DATA_MAX_LEN) { 688 return INTEL_SIP_SMC_STATUS_REJECTED; 689 } 690 691 if (!is_address_in_ddr_range(addr, size)) { 692 return INTEL_SIP_SMC_STATUS_REJECTED; 693 } 694 695 if (mode == SERVICE_COMPLETED_MODE_ASYNC) { 696 status = mailbox_read_response_async(job_id, 697 NULL, (uint32_t *) addr, &resp_len, 0); 698 } else { 699 status = mailbox_read_response(job_id, 700 (uint32_t *) addr, &resp_len); 701 702 if (status == MBOX_NO_RESPONSE) { 703 status = MBOX_BUSY; 704 } 705 } 706 707 if (status == MBOX_NO_RESPONSE) { 708 return INTEL_SIP_SMC_STATUS_NO_RESPONSE; 709 } 710 711 if (status == MBOX_BUSY) { 712 return INTEL_SIP_SMC_STATUS_BUSY; 713 } 714 715 *ret_size = resp_len * MBOX_WORD_BYTE; 716 flush_dcache_range(addr, *ret_size); 717 718 if (status == MBOX_RET_SDOS_DECRYPTION_ERROR_102 || 719 status == MBOX_RET_SDOS_DECRYPTION_ERROR_103) { 720 *mbox_error = -status; 721 } else if (status != MBOX_RET_OK) { 722 *mbox_error = -status; 723 return INTEL_SIP_SMC_STATUS_ERROR; 724 } 725 726 return INTEL_SIP_SMC_STATUS_OK; 727 } 728 729 /* Miscellaneous HPS services */ 730 uint32_t intel_hps_set_bridges(uint64_t enable, uint64_t mask) 731 { 732 int status = 0; 733 734 if ((enable & SOCFPGA_BRIDGE_ENABLE) != 0U) { 735 if ((enable & SOCFPGA_BRIDGE_HAS_MASK) != 0U) { 736 status = socfpga_bridges_enable((uint32_t)mask); 737 } else { 738 status = socfpga_bridges_enable(~0); 739 } 740 } else { 741 if ((enable & SOCFPGA_BRIDGE_HAS_MASK) != 0U) { 742 status = socfpga_bridges_disable((uint32_t)mask); 743 } else { 744 status = socfpga_bridges_disable(~0); 745 } 746 } 747 748 if (status < 0) { 749 return INTEL_SIP_SMC_STATUS_ERROR; 750 } 751 752 return INTEL_SIP_SMC_STATUS_OK; 753 } 754 755 /* SDM SEU Error services */ 756 static uint32_t intel_sdm_seu_err_read(uint32_t *respbuf, unsigned int respbuf_sz) 757 { 758 if (mailbox_seu_err_status(respbuf, respbuf_sz) < 0) { 759 return INTEL_SIP_SMC_SEU_ERR_READ_ERROR; 760 } 761 762 return INTEL_SIP_SMC_STATUS_OK; 763 } 764 765 /* SDM SAFE SEU Error inject services */ 766 static uint32_t intel_sdm_safe_inject_seu_err(uint32_t *command, uint32_t len) 767 { 768 if (mailbox_safe_inject_seu_err(command, len) < 0) { 769 return INTEL_SIP_SMC_SEU_ERR_READ_ERROR; 770 } 771 772 return INTEL_SIP_SMC_STATUS_OK; 773 } 774 775 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 776 /* SMMU HPS Remapper */ 777 void intel_smmu_hps_remapper_init(uint64_t *mem) 778 { 779 /* Read out Bit 1 value */ 780 uint32_t remap = (mmio_read_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_POR_1)) & 0x02); 781 782 if ((remap == 0x00) && (g_remapper_bypass == 0x00)) { 783 /* Update DRAM Base address for SDM SMMU */ 784 mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_ARADDR_REMAP), DRAM_BASE); 785 mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_AWADDR_REMAP), DRAM_BASE); 786 *mem = *mem - DRAM_BASE; 787 } else { 788 *mem = *mem - DRAM_BASE; 789 } 790 } 791 792 int intel_smmu_hps_remapper_config(uint32_t remapper_bypass) 793 { 794 /* Read out the JTAG-ID from boot scratch register */ 795 if (is_agilex5_A5F0() || is_agilex5_A5F4()) { 796 if (remapper_bypass == 0x01) { 797 g_remapper_bypass = remapper_bypass; 798 mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_ARADDR_REMAP), 0); 799 mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_AWADDR_REMAP), 0); 800 } 801 } 802 return INTEL_SIP_SMC_STATUS_OK; 803 } 804 805 static void intel_inject_io96b_ecc_err(const uint32_t *syndrome, const uint32_t command) 806 { 807 volatile uint64_t atf_ddr_buffer; 808 volatile uint64_t val; 809 810 mmio_write_32(IOSSM_CMD_PARAM, *syndrome); 811 mmio_write_32(IOSSM_CMD_TRIG_OP, command); 812 udelay(IOSSM_ECC_ERR_INJ_DELAY_USECS); 813 atf_ddr_buffer = 0xCAFEBABEFEEDFACE; /* Write data */ 814 memcpy_s((void *)&val, sizeof(val), 815 (void *)&atf_ddr_buffer, sizeof(atf_ddr_buffer)); 816 817 /* Clear response_ready BIT0 of status_register before sending next command. */ 818 mmio_clrbits_32(IOSSM_CMD_RESP_STATUS, IOSSM_CMD_STATUS_RESP_READY); 819 } 820 #endif 821 822 #if SIP_SVC_V3 823 uint8_t sip_smc_cmd_cb_ret2(void *resp_desc, void *cmd_desc, uint64_t *ret_args) 824 { 825 uint8_t ret_args_len = 0U; 826 sdm_response_t *resp = (sdm_response_t *)resp_desc; 827 sdm_command_t *cmd = (sdm_command_t *)cmd_desc; 828 829 (void)cmd; 830 /* Returns 3 SMC arguments for SMC_RET3 */ 831 ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK; 832 ret_args[ret_args_len++] = resp->err_code; 833 834 return ret_args_len; 835 } 836 837 uint8_t sip_smc_cmd_cb_ret3(void *resp_desc, void *cmd_desc, uint64_t *ret_args) 838 { 839 uint8_t ret_args_len = 0U; 840 sdm_response_t *resp = (sdm_response_t *)resp_desc; 841 sdm_command_t *cmd = (sdm_command_t *)cmd_desc; 842 843 (void)cmd; 844 /* Returns 3 SMC arguments for SMC_RET3 */ 845 ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK; 846 ret_args[ret_args_len++] = resp->err_code; 847 ret_args[ret_args_len++] = resp->resp_data[0]; 848 849 return ret_args_len; 850 } 851 852 uint8_t sip_smc_ret_nbytes_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args) 853 { 854 uint8_t ret_args_len = 0U; 855 sdm_response_t *resp = (sdm_response_t *)resp_desc; 856 sdm_command_t *cmd = (sdm_command_t *)cmd_desc; 857 858 (void)cmd; 859 INFO("MBOX: %s: mailbox_err 0%x, nbytes_ret %d\n", 860 __func__, resp->err_code, resp->rcvd_resp_len * MBOX_WORD_BYTE); 861 862 ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK; 863 ret_args[ret_args_len++] = resp->err_code; 864 ret_args[ret_args_len++] = resp->rcvd_resp_len * MBOX_WORD_BYTE; 865 866 return ret_args_len; 867 } 868 869 uint8_t sip_smc_get_chipid_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args) 870 { 871 uint8_t ret_args_len = 0U; 872 sdm_response_t *resp = (sdm_response_t *)resp_desc; 873 sdm_command_t *cmd = (sdm_command_t *)cmd_desc; 874 875 (void)cmd; 876 INFO("MBOX: %s: mailbox_err 0%x, data[0] 0x%x, data[1] 0x%x\n", 877 __func__, resp->err_code, resp->resp_data[0], resp->resp_data[1]); 878 879 ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK; 880 ret_args[ret_args_len++] = resp->err_code; 881 ret_args[ret_args_len++] = resp->resp_data[0]; 882 ret_args[ret_args_len++] = resp->resp_data[1]; 883 884 return ret_args_len; 885 } 886 887 uint8_t sip_smc_cmd_cb_rsu_status(void *resp_desc, void *cmd_desc, uint64_t *ret_args) 888 { 889 uint8_t ret_args_len = 0U; 890 uint32_t retry_counter = ~0U; 891 uint32_t failure_source = 0U; 892 sdm_response_t *resp = (sdm_response_t *)resp_desc; 893 sdm_command_t *cmd = (sdm_command_t *)cmd_desc; 894 895 (void)cmd; 896 /* Get the failure source and current image retry counter value from the response. */ 897 failure_source = resp->resp_data[5] & RSU_VERSION_ACMF_MASK; 898 retry_counter = resp->resp_data[8]; 899 900 if ((retry_counter != ~0U) && (failure_source == 0U)) 901 resp->resp_data[5] |= RSU_VERSION_ACMF; 902 903 ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK; 904 ret_args[ret_args_len++] = resp->err_code; 905 /* Current CMF */ 906 ret_args[ret_args_len++] = GET_ADDR64(resp->resp_data[1], resp->resp_data[0]); 907 /* Last Failing CMF Address */ 908 ret_args[ret_args_len++] = GET_ADDR64(resp->resp_data[3], resp->resp_data[2]); 909 /* Config State */ 910 ret_args[ret_args_len++] = resp->resp_data[4]; 911 /* Version */ 912 ret_args[ret_args_len++] = (GENMASK(16, 0) & resp->resp_data[5]); 913 /* Failure Source */ 914 ret_args[ret_args_len++] = ((GENMASK(32, 17) & resp->resp_data[5]) >> 16); 915 /* Error location */ 916 ret_args[ret_args_len++] = resp->resp_data[6]; 917 /* Error details */ 918 ret_args[ret_args_len++] = resp->resp_data[7]; 919 /* Current image retry counter */ 920 ret_args[ret_args_len++] = resp->resp_data[8]; 921 922 return ret_args_len; 923 } 924 925 uint8_t sip_smc_cmd_cb_rsu_spt(void *resp_desc, void *cmd_desc, uint64_t *ret_args) 926 { 927 uint8_t ret_args_len = 0U; 928 sdm_response_t *resp = (sdm_response_t *)resp_desc; 929 sdm_command_t *cmd = (sdm_command_t *)cmd_desc; 930 931 (void)cmd; 932 933 ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK; 934 ret_args[ret_args_len++] = resp->err_code; 935 /* Sub Partition Table (SPT) 0 address */ 936 ret_args[ret_args_len++] = GET_ADDR64(resp->resp_data[0], resp->resp_data[1]); 937 /* Sub Partition Table (SPT) 1 address */ 938 ret_args[ret_args_len++] = GET_ADDR64(resp->resp_data[2], resp->resp_data[3]); 939 940 return ret_args_len; 941 } 942 943 static uintptr_t smc_ret(void *handle, uint64_t *ret_args, uint32_t ret_args_len) 944 { 945 946 switch (ret_args_len) { 947 case SMC_RET_ARGS_ONE: 948 VERBOSE("SVC V3: %s: x0 0x%lx\n", __func__, ret_args[0]); 949 SMC_RET1(handle, ret_args[0]); 950 break; 951 952 case SMC_RET_ARGS_TWO: 953 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx\n", __func__, ret_args[0], ret_args[1]); 954 SMC_RET2(handle, ret_args[0], ret_args[1]); 955 break; 956 957 case SMC_RET_ARGS_THREE: 958 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx, x2 0x%lx\n", 959 __func__, ret_args[0], ret_args[1], ret_args[2]); 960 SMC_RET3(handle, ret_args[0], ret_args[1], ret_args[2]); 961 break; 962 963 case SMC_RET_ARGS_FOUR: 964 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx, x2 0x%lx, x3 0x%lx\n", 965 __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3]); 966 SMC_RET4(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3]); 967 break; 968 969 case SMC_RET_ARGS_FIVE: 970 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx, x2 0x%lx, x3 0x%lx, x4 0x%lx\n", 971 __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4]); 972 SMC_RET5(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4]); 973 break; 974 975 case SMC_RET_ARGS_SIX: 976 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx x2 0x%lx x3 0x%lx, x4 0x%lx x5 0x%lx\n", 977 __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4], 978 ret_args[5]); 979 SMC_RET6(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4], 980 ret_args[5]); 981 break; 982 983 case SMC_RET_ARGS_SEVEN: 984 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx x2 0x%lx, x3 0x%lx, x4 0x%lx, x5 0x%lx\t" 985 "x6 0x%lx\n", 986 __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4], 987 ret_args[5], ret_args[6]); 988 SMC_RET7(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4], 989 ret_args[5], ret_args[6]); 990 break; 991 992 case SMC_RET_ARGS_EIGHT: 993 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx x2 0x%lx, x3 0x%lx, x4 0x%lx x5 0x%lx\t" 994 "x6 0x%lx, x7 0x%lx\n", 995 __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4], 996 ret_args[5], ret_args[6], ret_args[7]); 997 SMC_RET8(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4], 998 ret_args[5], ret_args[6], ret_args[7]); 999 break; 1000 1001 case SMC_RET_ARGS_NINE: 1002 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx x2 0x%lx, x3 0x%lx, x4 0x%lx, x5 0x%lx\t" 1003 "x6 0x%lx, x7 0x%lx, x8 0x%lx\n", 1004 __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4], 1005 ret_args[5], ret_args[6], ret_args[7], ret_args[8]); 1006 SMC_RET18(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4], 1007 ret_args[5], ret_args[6], ret_args[7], ret_args[8], 1008 0, 0, 0, 0, 0, 0, 0, 0, 0); 1009 break; 1010 1011 case SMC_RET_ARGS_TEN: 1012 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx, x2 0x%lx, x3 0x%lx, x4 0x%lx x5 0x%lx\t" 1013 "x6 0x%lx, x7 0x%lx x8 0x%lx, x9 0x%lx, x10 0x%lx\n", 1014 __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], 1015 ret_args[4], ret_args[5], ret_args[6], ret_args[7], ret_args[8], 1016 ret_args[9], ret_args[10]); 1017 SMC_RET18(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4], 1018 ret_args[5], ret_args[6], ret_args[7], ret_args[8], ret_args[9], 1019 0, 0, 0, 0, 0, 0, 0, 0); 1020 break; 1021 1022 default: 1023 VERBOSE("SVC V3: %s ret_args_len is wrong, please check %d\n ", 1024 __func__, ret_args_len); 1025 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR); 1026 break; 1027 } 1028 } 1029 1030 static inline bool is_gen_mbox_cmd_allowed(uint32_t cmd) 1031 { 1032 /* Check if the command is allowed to be executed in generic mbox format */ 1033 bool is_cmd_allowed = false; 1034 1035 switch (cmd) { 1036 case ALTERA_SIP_SMC_ASYNC_FCS_OPEN_CS_SESSION: 1037 case ALTERA_SIP_SMC_ASYNC_FCS_CLOSE_CS_SESSION: 1038 case ALTERA_SIP_SMC_ASYNC_FCS_IMPORT_CS_KEY: 1039 case ALTERA_SIP_SMC_ASYNC_FCS_EXPORT_CS_KEY: 1040 case ALTERA_SIP_SMC_ASYNC_FCS_REMOVE_CS_KEY: 1041 case ALTERA_SIP_SMC_ASYNC_FCS_GET_CS_KEY_INFO: 1042 case ALTERA_SIP_SMC_ASYNC_FCS_CREATE_CS_KEY: 1043 case ALTERA_SIP_SMC_ASYNC_FCS_RANDOM_NUMBER_EXT: 1044 case ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_INIT: 1045 case ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_UPDATE: 1046 case ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_FINALIZE: 1047 case ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_INIT: 1048 case ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_UPDATE: 1049 case ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_FINALIZE: 1050 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIGN_INIT: 1051 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIGN_FINALIZE: 1052 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_INIT: 1053 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_UPDATE: 1054 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE: 1055 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_UPDATE: 1056 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_FINALIZE: 1057 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIG_VERIFY_INIT: 1058 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIG_VERIFY_FINALIZE: 1059 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_INIT: 1060 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_UPDATE: 1061 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE: 1062 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_UPDATE: 1063 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_FINALIZE: 1064 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_GET_PUBKEY_INIT: 1065 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_GET_PUBKEY_FINALIZE: 1066 case ALTERA_SIP_SMC_ASYNC_FCS_ECDH_REQUEST_INIT: 1067 case ALTERA_SIP_SMC_ASYNC_FCS_ECDH_REQUEST_FINALIZE: 1068 case ALTERA_SIP_SMC_ASYNC_FCS_HKDF_REQUEST: 1069 case ALTERA_SIP_SMC_ASYNC_FCS_CRYPTION_EXT: 1070 case ALTERA_SIP_SMC_ASYNC_FCS_CRYPTION: 1071 /* These commands are not supported in the generic mailbox format. */ 1072 break; 1073 1074 default: 1075 is_cmd_allowed = true; 1076 break; 1077 } /* switch */ 1078 1079 return is_cmd_allowed; 1080 } 1081 1082 /* 1083 * This function is responsible for handling all SiP SVC V3 calls from the 1084 * non-secure world. 1085 */ 1086 static uintptr_t sip_smc_handler_v3(uint32_t smc_fid, 1087 u_register_t x1, 1088 u_register_t x2, 1089 u_register_t x3, 1090 u_register_t x4, 1091 void *cookie, 1092 void *handle, 1093 u_register_t flags) 1094 { 1095 int status = 0; 1096 uint32_t mbox_error = 0U; 1097 u_register_t x5, x6, x7, x8, x9, x10, x11; 1098 1099 /* Get all the SMC call arguments */ 1100 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1101 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1102 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1103 x8 = SMC_GET_GP(handle, CTX_GPREG_X8); 1104 x9 = SMC_GET_GP(handle, CTX_GPREG_X9); 1105 x10 = SMC_GET_GP(handle, CTX_GPREG_X10); 1106 x11 = SMC_GET_GP(handle, CTX_GPREG_X11); 1107 1108 INFO("MBOX: SVC_V3: x0 0x%x, x1 0x%lx, x2 0x%lx, x3 0x%lx, x4 0x%lx, x5 0x%lx\n", 1109 smc_fid, x1, x2, x3, x4, x5); 1110 INFO("MBOX: SVC_V3: x6 0x%lx, x7 0x%lx, x8 0x%lx, x9 0x%lx, x10 0x%lx x11 0x%lx\n", 1111 x6, x7, x8, x9, x10, x11); 1112 1113 switch (smc_fid) { 1114 case ALTERA_SIP_SMC_ASYNC_RESP_POLL: 1115 { 1116 uint64_t ret_args[16] = {0}; 1117 uint32_t ret_args_len = 0; 1118 1119 status = mailbox_response_poll_v3(GET_CLIENT_ID(x1), 1120 GET_JOB_ID(x1), 1121 ret_args, 1122 &ret_args_len); 1123 /* Always reserve [0] index for command status. */ 1124 ret_args[0] = status; 1125 1126 /* Return SMC call based on the number of return arguments */ 1127 return smc_ret(handle, ret_args, ret_args_len); 1128 } 1129 1130 case ALTERA_SIP_SMC_ASYNC_RESP_POLL_ON_INTR: 1131 { 1132 /* TBD: Here now we don't need these CID and JID?? */ 1133 uint8_t client_id = 0U; 1134 uint8_t job_id = 0U; 1135 uint64_t trans_id_bitmap[4] = {0U}; 1136 1137 status = mailbox_response_poll_on_intr_v3(&client_id, 1138 &job_id, 1139 trans_id_bitmap); 1140 1141 SMC_RET5(handle, status, trans_id_bitmap[0], trans_id_bitmap[1], 1142 trans_id_bitmap[2], trans_id_bitmap[3]); 1143 break; 1144 } 1145 1146 case ALTERA_SIP_SMC_ASYNC_GET_DEVICE_IDENTITY: 1147 { 1148 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1149 GET_JOB_ID(x1), 1150 MBOX_CMD_GET_DEVICEID, 1151 NULL, 1152 0U, 1153 MBOX_CMD_FLAG_CASUAL, 1154 sip_smc_ret_nbytes_cb, 1155 (uint32_t *)x2, 1156 2); 1157 1158 SMC_RET1(handle, status); 1159 } 1160 1161 case ALTERA_SIP_SMC_ASYNC_GET_IDCODE: 1162 { 1163 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1164 GET_JOB_ID(x1), 1165 MBOX_CMD_GET_IDCODE, 1166 NULL, 1167 0U, 1168 MBOX_CMD_FLAG_CASUAL, 1169 sip_smc_cmd_cb_ret3, 1170 NULL, 1171 0); 1172 1173 SMC_RET1(handle, status); 1174 } 1175 1176 case ALTERA_SIP_SMC_ASYNC_QSPI_OPEN: 1177 { 1178 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1179 GET_JOB_ID(x1), 1180 MBOX_CMD_QSPI_OPEN, 1181 NULL, 1182 0U, 1183 MBOX_CMD_FLAG_CASUAL, 1184 sip_smc_cmd_cb_ret2, 1185 NULL, 1186 0U); 1187 1188 SMC_RET1(handle, status); 1189 } 1190 1191 case ALTERA_SIP_SMC_ASYNC_QSPI_CLOSE: 1192 { 1193 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1194 GET_JOB_ID(x1), 1195 MBOX_CMD_QSPI_CLOSE, 1196 NULL, 1197 0U, 1198 MBOX_CMD_FLAG_CASUAL, 1199 sip_smc_cmd_cb_ret2, 1200 NULL, 1201 0U); 1202 1203 SMC_RET1(handle, status); 1204 } 1205 1206 case ALTERA_SIP_SMC_ASYNC_QSPI_SET_CS: 1207 { 1208 uint32_t cmd_data = 0U; 1209 uint32_t chip_sel = (uint32_t)x2; 1210 uint32_t comb_addr_mode = (uint32_t)x3; 1211 uint32_t ext_dec_mode = (uint32_t)x4; 1212 1213 cmd_data = (chip_sel << MBOX_QSPI_SET_CS_OFFSET) | 1214 (comb_addr_mode << MBOX_QSPI_SET_CS_CA_OFFSET) | 1215 (ext_dec_mode << MBOX_QSPI_SET_CS_MODE_OFFSET); 1216 1217 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1218 GET_JOB_ID(x1), 1219 MBOX_CMD_QSPI_SET_CS, 1220 &cmd_data, 1221 1U, 1222 MBOX_CMD_FLAG_CASUAL, 1223 sip_smc_cmd_cb_ret2, 1224 NULL, 1225 0U); 1226 1227 SMC_RET1(handle, status); 1228 } 1229 1230 case ALTERA_SIP_SMC_ASYNC_QSPI_ERASE: 1231 { 1232 uint32_t qspi_addr = (uint32_t)x2; 1233 uint32_t qspi_nwords = (uint32_t)x3; 1234 1235 /* QSPI address offset to start erase, must be 4K aligned */ 1236 if (MBOX_IS_4K_ALIGNED(qspi_addr)) { 1237 ERROR("MBOX: 0x%x: QSPI address not 4K aligned\n", 1238 smc_fid); 1239 status = INTEL_SIP_SMC_STATUS_REJECTED; 1240 SMC_RET1(handle, status); 1241 } 1242 1243 /* Number of words to erase, multiples of 0x400 or 4K */ 1244 if (qspi_nwords % MBOX_QSPI_ERASE_SIZE_GRAN) { 1245 ERROR("MBOX: 0x%x: Given words not in multiples of 4K\n", 1246 smc_fid); 1247 status = INTEL_SIP_SMC_STATUS_REJECTED; 1248 SMC_RET1(handle, status); 1249 } 1250 1251 uint32_t cmd_data[2] = {qspi_addr, qspi_nwords}; 1252 1253 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1254 GET_JOB_ID(x1), 1255 MBOX_CMD_QSPI_ERASE, 1256 cmd_data, 1257 sizeof(cmd_data) / MBOX_WORD_BYTE, 1258 MBOX_CMD_FLAG_CASUAL, 1259 sip_smc_cmd_cb_ret2, 1260 NULL, 1261 0U); 1262 1263 SMC_RET1(handle, status); 1264 } 1265 1266 case ALTERA_SIP_SMC_ASYNC_QSPI_WRITE: 1267 { 1268 uint32_t *qspi_payload = (uint32_t *)x2; 1269 uint32_t qspi_total_nwords = (((uint32_t)x3) / MBOX_WORD_BYTE); 1270 uint32_t qspi_addr = qspi_payload[0]; 1271 uint32_t qspi_nwords = qspi_payload[1]; 1272 1273 if (!MBOX_IS_WORD_ALIGNED(qspi_addr)) { 1274 ERROR("MBOX: 0x%x: Given address is not WORD aligned\n", 1275 smc_fid); 1276 status = INTEL_SIP_SMC_STATUS_REJECTED; 1277 SMC_RET1(handle, status); 1278 } 1279 1280 if (qspi_nwords > MBOX_QSPI_RW_MAX_WORDS) { 1281 ERROR("MBOX: 0x%x: Number of words exceeds max limit\n", 1282 smc_fid); 1283 status = INTEL_SIP_SMC_STATUS_REJECTED; 1284 SMC_RET1(handle, status); 1285 } 1286 1287 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1288 GET_JOB_ID(x1), 1289 MBOX_CMD_QSPI_WRITE, 1290 qspi_payload, 1291 qspi_total_nwords, 1292 MBOX_CMD_FLAG_CASUAL, 1293 sip_smc_cmd_cb_ret2, 1294 NULL, 1295 0U); 1296 1297 SMC_RET1(handle, status); 1298 } 1299 1300 case ALTERA_SIP_SMC_ASYNC_QSPI_READ: 1301 { 1302 uint32_t qspi_addr = (uint32_t)x2; 1303 uint32_t qspi_nwords = (((uint32_t)x4) / MBOX_WORD_BYTE); 1304 1305 if (qspi_nwords > MBOX_QSPI_RW_MAX_WORDS) { 1306 ERROR("MBOX: 0x%x: Number of words exceeds max limit\n", 1307 smc_fid); 1308 status = INTEL_SIP_SMC_STATUS_REJECTED; 1309 SMC_RET1(handle, status); 1310 } 1311 1312 uint32_t cmd_data[2] = {qspi_addr, qspi_nwords}; 1313 1314 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1315 GET_JOB_ID(x1), 1316 MBOX_CMD_QSPI_READ, 1317 cmd_data, 1318 sizeof(cmd_data) / MBOX_WORD_BYTE, 1319 MBOX_CMD_FLAG_CASUAL, 1320 sip_smc_ret_nbytes_cb, 1321 (uint32_t *)x3, 1322 2); 1323 1324 SMC_RET1(handle, status); 1325 } 1326 1327 case ALTERA_SIP_SMC_ASYNC_QSPI_GET_DEV_INFO: 1328 { 1329 uint32_t *dst_addr = (uint32_t *)x2; 1330 1331 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1332 GET_JOB_ID(x1), 1333 MBOX_CMD_QSPI_GET_DEV_INFO, 1334 NULL, 1335 0U, 1336 MBOX_CMD_FLAG_CASUAL, 1337 sip_smc_ret_nbytes_cb, 1338 (uint32_t *)dst_addr, 1339 2); 1340 1341 SMC_RET1(handle, status); 1342 } 1343 1344 case ALTERA_SIP_SMC_ASYNC_HWMON_READVOLT: 1345 case ALTERA_SIP_SMC_ASYNC_HWMON_READTEMP: 1346 { 1347 uint32_t channel = (uint32_t)x2; 1348 uint32_t mbox_cmd = ((smc_fid == ALTERA_SIP_SMC_ASYNC_HWMON_READVOLT) ? 1349 MBOX_HWMON_READVOLT : MBOX_HWMON_READTEMP); 1350 1351 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1352 GET_JOB_ID(x1), 1353 mbox_cmd, 1354 &channel, 1355 1U, 1356 MBOX_CMD_FLAG_CASUAL, 1357 sip_smc_cmd_cb_ret3, 1358 NULL, 1359 0); 1360 1361 SMC_RET1(handle, status); 1362 } 1363 1364 case ALTERA_SIP_SMC_ASYNC_RSU_GET_SPT: 1365 { 1366 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1367 GET_JOB_ID(x1), 1368 MBOX_GET_SUBPARTITION_TABLE, 1369 NULL, 1370 0, 1371 MBOX_CMD_FLAG_CASUAL, 1372 sip_smc_cmd_cb_rsu_spt, 1373 NULL, 1374 0); 1375 1376 SMC_RET1(handle, status); 1377 } 1378 1379 case ALTERA_SIP_SMC_ASYNC_RSU_GET_STATUS: 1380 { 1381 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1382 GET_JOB_ID(x1), 1383 MBOX_RSU_STATUS, 1384 NULL, 1385 0, 1386 MBOX_CMD_FLAG_CASUAL, 1387 sip_smc_cmd_cb_rsu_status, 1388 NULL, 1389 0); 1390 1391 SMC_RET1(handle, status); 1392 } 1393 1394 case ALTERA_SIP_SMC_ASYNC_RSU_NOTIFY: 1395 { 1396 uint32_t notify_code = (uint32_t)x2; 1397 1398 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1399 GET_JOB_ID(x1), 1400 MBOX_HPS_STAGE_NOTIFY, 1401 ¬ify_code, 1402 1U, 1403 MBOX_CMD_FLAG_CASUAL, 1404 sip_smc_cmd_cb_ret2, 1405 NULL, 1406 0); 1407 1408 SMC_RET1(handle, status); 1409 } 1410 1411 case ALTERA_SIP_SMC_ASYNC_GEN_MBOX_CMD: 1412 { 1413 /* Filter the required commands here. */ 1414 if (!is_gen_mbox_cmd_allowed(smc_fid)) { 1415 status = INTEL_SIP_SMC_STATUS_REJECTED; 1416 SMC_RET1(handle, status); 1417 } 1418 1419 /* Collect all the args passed in, and send the mailbox command. */ 1420 uint32_t mbox_cmd = (uint32_t)x2; 1421 uint32_t *cmd_payload_addr = NULL; 1422 uint32_t cmd_payload_len = (uint32_t)x4 / MBOX_WORD_BYTE; 1423 uint32_t *resp_payload_addr = NULL; 1424 uint32_t resp_payload_len = (uint32_t)x6 / MBOX_WORD_BYTE; 1425 1426 if ((cmd_payload_len > MBOX_GEN_CMD_MAX_WORDS) || 1427 (resp_payload_len > MBOX_GEN_CMD_MAX_WORDS)) { 1428 ERROR("MBOX: 0x%x: Command/Response payload length exceeds max limit\n", 1429 smc_fid); 1430 status = INTEL_SIP_SMC_STATUS_REJECTED; 1431 SMC_RET1(handle, status); 1432 } 1433 1434 /* Make sure we have valid command payload length and buffer */ 1435 if (cmd_payload_len != 0U) { 1436 cmd_payload_addr = (uint32_t *)x3; 1437 if (cmd_payload_addr == NULL) { 1438 ERROR("MBOX: 0x%x: Command payload address is NULL\n", 1439 smc_fid); 1440 status = INTEL_SIP_SMC_STATUS_REJECTED; 1441 SMC_RET1(handle, status); 1442 } 1443 } 1444 1445 /* Make sure we have valid response payload length and buffer */ 1446 if (resp_payload_len != 0U) { 1447 resp_payload_addr = (uint32_t *)x5; 1448 if (resp_payload_addr == NULL) { 1449 ERROR("MBOX: 0x%x: Response payload address is NULL\n", 1450 smc_fid); 1451 status = INTEL_SIP_SMC_STATUS_REJECTED; 1452 SMC_RET1(handle, status); 1453 } 1454 } 1455 1456 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1457 GET_JOB_ID(x1), 1458 mbox_cmd, 1459 (uint32_t *)cmd_payload_addr, 1460 cmd_payload_len, 1461 MBOX_CMD_FLAG_CASUAL, 1462 sip_smc_ret_nbytes_cb, 1463 (uint32_t *)resp_payload_addr, 1464 resp_payload_len); 1465 1466 SMC_RET1(handle, status); 1467 } 1468 1469 case ALTERA_SIP_SMC_ASYNC_FCS_RANDOM_NUMBER_EXT: 1470 { 1471 uint32_t session_id = (uint32_t)x2; 1472 uint32_t context_id = (uint32_t)x3; 1473 uint64_t ret_random_addr = (uint64_t)x4; 1474 uint32_t random_len = (uint32_t)SMC_GET_GP(handle, CTX_GPREG_X5); 1475 uint32_t crypto_header = 0U; 1476 1477 if ((random_len > (FCS_RANDOM_EXT_MAX_WORD_SIZE * MBOX_WORD_BYTE)) || 1478 (random_len == 0U) || 1479 (!is_size_4_bytes_aligned(random_len))) { 1480 ERROR("MBOX: 0x%x is rejected\n", smc_fid); 1481 status = INTEL_SIP_SMC_STATUS_REJECTED; 1482 SMC_RET1(handle, status); 1483 } 1484 1485 crypto_header = ((FCS_CS_FIELD_FLAG_INIT | FCS_CS_FIELD_FLAG_FINALIZE) << 1486 FCS_CS_FIELD_FLAG_OFFSET); 1487 fcs_rng_payload payload = {session_id, context_id, 1488 crypto_header, random_len}; 1489 1490 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1491 GET_JOB_ID(x1), 1492 MBOX_FCS_RANDOM_GEN, 1493 (uint32_t *)&payload, 1494 sizeof(payload) / MBOX_WORD_BYTE, 1495 MBOX_CMD_FLAG_CASUAL, 1496 sip_smc_ret_nbytes_cb, 1497 (uint32_t *)ret_random_addr, 1498 2); 1499 SMC_RET1(handle, status); 1500 } 1501 1502 case ALTERA_SIP_SMC_ASYNC_FCS_GET_PROVISION_DATA: 1503 { 1504 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1505 GET_JOB_ID(x1), 1506 MBOX_FCS_GET_PROVISION, 1507 NULL, 1508 0U, 1509 MBOX_CMD_FLAG_CASUAL, 1510 sip_smc_ret_nbytes_cb, 1511 (uint32_t *)x2, 1512 2); 1513 SMC_RET1(handle, status); 1514 } 1515 1516 case ALTERA_SIP_SMC_ASYNC_FCS_CNTR_SET_PREAUTH: 1517 { 1518 status = intel_fcs_cntr_set_preauth(smc_fid, x1, x2, x3, 1519 x4, &mbox_error); 1520 SMC_RET1(handle, status); 1521 } 1522 1523 case ALTERA_SIP_SMC_ASYNC_FCS_CHIP_ID: 1524 { 1525 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1526 GET_JOB_ID(x1), 1527 MBOX_CMD_GET_CHIPID, 1528 NULL, 1529 0U, 1530 MBOX_CMD_FLAG_CASUAL, 1531 sip_smc_get_chipid_cb, 1532 NULL, 1533 0); 1534 SMC_RET1(handle, status); 1535 } 1536 1537 case ALTERA_SIP_SMC_ASYNC_FCS_GET_ATTESTATION_CERT: 1538 { 1539 status = intel_fcs_get_attestation_cert(smc_fid, x1, x2, x3, 1540 (uint32_t *) &x4, &mbox_error); 1541 SMC_RET1(handle, status); 1542 } 1543 1544 case ALTERA_SIP_SMC_ASYNC_FCS_CREATE_CERT_ON_RELOAD: 1545 { 1546 status = intel_fcs_create_cert_on_reload(smc_fid, x1, 1547 x2, &mbox_error); 1548 SMC_RET1(handle, status); 1549 } 1550 1551 case ALTERA_SIP_SMC_ASYNC_FCS_CRYPTION_EXT: 1552 { 1553 if (x4 == FCS_MODE_ENCRYPT) { 1554 status = intel_fcs_encryption_ext(smc_fid, x1, x2, x3, 1555 x5, x6, x7, (uint32_t *) &x8, 1556 &mbox_error, x10, x11); 1557 } else if (x4 == FCS_MODE_DECRYPT) { 1558 status = intel_fcs_decryption_ext(smc_fid, x1, x2, x3, 1559 x5, x6, x7, (uint32_t *) &x8, 1560 &mbox_error, x9, x10, x11); 1561 } else { 1562 ERROR("MBOX: 0x%x: Wrong crypto mode\n", smc_fid); 1563 status = INTEL_SIP_SMC_STATUS_REJECTED; 1564 } 1565 SMC_RET1(handle, status); 1566 } 1567 1568 case ALTERA_SIP_SMC_ASYNC_FCS_SEND_CERTIFICATE: 1569 { 1570 status = intel_fcs_send_cert(smc_fid, x1, x2, x3, &mbox_error); 1571 SMC_RET1(handle, status); 1572 } 1573 1574 case ALTERA_SIP_SMC_ASYNC_FCS_OPEN_CS_SESSION: 1575 { 1576 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1577 GET_JOB_ID(x1), 1578 MBOX_FCS_OPEN_CS_SESSION, 1579 NULL, 1580 0U, 1581 MBOX_CMD_FLAG_CASUAL, 1582 sip_smc_cmd_cb_ret3, 1583 NULL, 1584 0); 1585 SMC_RET1(handle, status); 1586 } 1587 1588 case ALTERA_SIP_SMC_ASYNC_FCS_CLOSE_CS_SESSION: 1589 { 1590 uint32_t session_id = (uint32_t)x2; 1591 1592 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1593 GET_JOB_ID(x1), 1594 MBOX_FCS_CLOSE_CS_SESSION, 1595 &session_id, 1596 1U, 1597 MBOX_CMD_FLAG_CASUAL, 1598 sip_smc_cmd_cb_ret2, 1599 NULL, 1600 0); 1601 SMC_RET1(handle, status); 1602 } 1603 1604 case ALTERA_SIP_SMC_ASYNC_FCS_IMPORT_CS_KEY: 1605 { 1606 uint64_t key_addr = x2; 1607 uint32_t key_len_words = (uint32_t)x3 / MBOX_WORD_BYTE; 1608 1609 if ((key_len_words > FCS_CS_KEY_OBJ_MAX_WORD_SIZE) || 1610 (!is_address_in_ddr_range(key_addr, key_len_words * 4))) { 1611 ERROR("MBOX: 0x%x: Addr not in DDR range or key len exceeds\n", 1612 smc_fid); 1613 status = INTEL_SIP_SMC_STATUS_REJECTED; 1614 SMC_RET1(handle, status); 1615 } 1616 1617 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1618 GET_JOB_ID(x1), 1619 MBOX_FCS_IMPORT_CS_KEY, 1620 (uint32_t *)key_addr, 1621 key_len_words, 1622 MBOX_CMD_FLAG_CASUAL, 1623 sip_smc_cmd_cb_ret3, 1624 NULL, 1625 0); 1626 SMC_RET1(handle, status); 1627 } 1628 1629 case ALTERA_SIP_SMC_ASYNC_FCS_CREATE_CS_KEY: 1630 { 1631 uint64_t key_addr = x2; 1632 uint32_t key_len_words = (uint32_t)x3 / MBOX_WORD_BYTE; 1633 1634 if (!is_address_in_ddr_range(key_addr, key_len_words * 4)) { 1635 ERROR("MBOX: 0x%x: Addr not in DDR range\n", smc_fid); 1636 status = INTEL_SIP_SMC_STATUS_REJECTED; 1637 SMC_RET1(handle, status); 1638 } 1639 1640 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1641 GET_JOB_ID(x1), 1642 MBOX_FCS_CREATE_CS_KEY, 1643 (uint32_t *)key_addr, 1644 key_len_words, 1645 MBOX_CMD_FLAG_CASUAL, 1646 sip_smc_cmd_cb_ret3, 1647 NULL, 1648 0); 1649 SMC_RET1(handle, status); 1650 } 1651 1652 case ALTERA_SIP_SMC_ASYNC_FCS_EXPORT_CS_KEY: 1653 { 1654 uint32_t session_id = (uint32_t)x2; 1655 uint32_t key_uid = (uint32_t)x3; 1656 uint64_t ret_key_addr = (uint64_t)x4; 1657 uint32_t key_len = (uint32_t)SMC_GET_GP(handle, CTX_GPREG_X5); 1658 1659 if (!is_address_in_ddr_range(ret_key_addr, key_len)) { 1660 ERROR("MBOX: 0x%x: Addr not in DDR range\n", smc_fid); 1661 status = INTEL_SIP_SMC_STATUS_REJECTED; 1662 SMC_RET1(handle, status); 1663 } 1664 1665 fcs_cs_key_payload payload = {session_id, RESERVED_AS_ZERO, 1666 RESERVED_AS_ZERO, key_uid}; 1667 1668 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1669 GET_JOB_ID(x1), 1670 MBOX_FCS_EXPORT_CS_KEY, 1671 (uint32_t *)&payload, 1672 sizeof(payload) / MBOX_WORD_BYTE, 1673 MBOX_CMD_FLAG_CASUAL, 1674 sip_smc_ret_nbytes_cb, 1675 (uint32_t *)ret_key_addr, 1676 2); 1677 SMC_RET1(handle, status); 1678 } 1679 1680 case ALTERA_SIP_SMC_ASYNC_FCS_REMOVE_CS_KEY: 1681 { 1682 uint32_t session_id = (uint32_t)x2; 1683 uint32_t key_uid = (uint32_t)x3; 1684 1685 fcs_cs_key_payload payload = {session_id, RESERVED_AS_ZERO, 1686 RESERVED_AS_ZERO, key_uid}; 1687 1688 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1689 GET_JOB_ID(x1), 1690 MBOX_FCS_REMOVE_CS_KEY, 1691 (uint32_t *)&payload, 1692 sizeof(payload) / MBOX_WORD_BYTE, 1693 MBOX_CMD_FLAG_CASUAL, 1694 sip_smc_cmd_cb_ret3, 1695 NULL, 1696 0); 1697 SMC_RET1(handle, status); 1698 } 1699 1700 case ALTERA_SIP_SMC_ASYNC_FCS_GET_CS_KEY_INFO: 1701 { 1702 uint32_t session_id = (uint32_t)x2; 1703 uint32_t key_uid = (uint32_t)x3; 1704 uint64_t ret_key_addr = (uint64_t)x4; 1705 uint32_t key_len = (uint32_t)SMC_GET_GP(handle, CTX_GPREG_X5); 1706 1707 if (!is_address_in_ddr_range(ret_key_addr, key_len)) { 1708 ERROR("MBOX: 0x%x: Addr not in DDR range\n", smc_fid); 1709 status = INTEL_SIP_SMC_STATUS_REJECTED; 1710 SMC_RET1(handle, status); 1711 } 1712 1713 fcs_cs_key_payload payload = {session_id, RESERVED_AS_ZERO, 1714 RESERVED_AS_ZERO, key_uid}; 1715 1716 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1717 GET_JOB_ID(x1), 1718 MBOX_FCS_GET_CS_KEY_INFO, 1719 (uint32_t *)&payload, 1720 sizeof(payload) / MBOX_WORD_BYTE, 1721 MBOX_CMD_FLAG_CASUAL, 1722 sip_smc_ret_nbytes_cb, 1723 (uint32_t *)ret_key_addr, 1724 2); 1725 SMC_RET1(handle, status); 1726 } 1727 1728 case ALTERA_SIP_SMC_ASYNC_FCS_AES_CRYPT_INIT: 1729 { 1730 status = intel_fcs_aes_crypt_init(x2, x3, x4, x5, 1731 x6, &mbox_error); 1732 SMC_RET1(handle, status); 1733 } 1734 1735 case ALTERA_SIP_SMC_ASYNC_FCS_AES_CRYPT_UPDATE: 1736 case ALTERA_SIP_SMC_ASYNC_FCS_AES_CRYPT_FINALIZE: 1737 { 1738 uint32_t job_id = 0U; 1739 bool is_final = (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_AES_CRYPT_FINALIZE) ? 1740 true : false; 1741 1742 status = intel_fcs_aes_crypt_update_finalize(smc_fid, x1, x2, 1743 x3, x4, x5, x6, x7, x8, is_final, 1744 &job_id, x9, x10); 1745 SMC_RET1(handle, status); 1746 } 1747 1748 case ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_INIT: 1749 { 1750 status = intel_fcs_get_digest_init(x2, x3, x4, x5, x6, 1751 &mbox_error); 1752 SMC_RET1(handle, status); 1753 } 1754 1755 case ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_UPDATE: 1756 case ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_FINALIZE: 1757 { 1758 bool is_final = (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_FINALIZE) ? 1759 true : false; 1760 1761 status = intel_fcs_get_digest_update_finalize(smc_fid, x1, x2, 1762 x3, x4, x5, x6, (uint32_t *) &x7, 1763 is_final, &mbox_error, x8); 1764 1765 SMC_RET1(handle, status); 1766 } 1767 1768 case ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_INIT: 1769 { 1770 status = intel_fcs_mac_verify_init(x2, x3, x4, x5, x6, 1771 &mbox_error); 1772 SMC_RET1(handle, status); 1773 } 1774 1775 case ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_UPDATE: 1776 case ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_FINALIZE: 1777 { 1778 bool is_final = (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_FINALIZE) ? 1779 true : false; 1780 1781 status = intel_fcs_mac_verify_update_finalize(smc_fid, x1, x2, 1782 x3, x4, x5, x6, (uint32_t *) &x7, x8, 1783 is_final, &mbox_error, x9); 1784 SMC_RET1(handle, status); 1785 } 1786 1787 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIGN_INIT: 1788 { 1789 status = intel_fcs_ecdsa_hash_sign_init(x2, x3, x4, x5, x6, 1790 &mbox_error); 1791 SMC_RET1(handle, status); 1792 } 1793 1794 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIGN_FINALIZE: 1795 { 1796 status = intel_fcs_ecdsa_hash_sign_finalize(smc_fid, x1, x2, x3, 1797 x4, x5, x6, (uint32_t *) &x7, 1798 &mbox_error); 1799 SMC_RET1(handle, status); 1800 } 1801 1802 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_INIT: 1803 { 1804 status = intel_fcs_ecdsa_sha2_data_sign_init(x2, x3, x4, x5, x6, 1805 &mbox_error); 1806 SMC_RET1(handle, status); 1807 } 1808 1809 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_UPDATE: 1810 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE: 1811 { 1812 bool is_final = (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE) 1813 ? true : false; 1814 1815 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(smc_fid, 1816 x1, x2, x3, x4, x5, x6, (uint32_t *) &x7, 1817 is_final, &mbox_error, x8); 1818 SMC_RET1(handle, status); 1819 } 1820 1821 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIG_VERIFY_INIT: 1822 { 1823 status = intel_fcs_ecdsa_hash_sig_verify_init(x2, x3, x4, x5, 1824 x6, &mbox_error); 1825 SMC_RET1(handle, status); 1826 } 1827 1828 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIG_VERIFY_FINALIZE: 1829 { 1830 status = intel_fcs_ecdsa_hash_sig_verify_finalize(smc_fid, x1, 1831 x2, x3, x4, x5, x6, (uint32_t *) &x7, 1832 &mbox_error); 1833 SMC_RET1(handle, status); 1834 } 1835 1836 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_INIT: 1837 { 1838 status = intel_fcs_ecdsa_sha2_data_sig_verify_init(x2, x3, x4, 1839 x5, x6, &mbox_error); 1840 SMC_RET1(handle, status); 1841 } 1842 1843 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_UPDATE: 1844 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE: 1845 { 1846 bool is_final = (smc_fid == 1847 ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE) ? 1848 true : false; 1849 1850 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize( 1851 smc_fid, x1, x2, x3, x4, x5, x6, 1852 (uint32_t *) &x7, x8, is_final, 1853 &mbox_error, x9); 1854 SMC_RET1(handle, status); 1855 } 1856 1857 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_GET_PUBKEY_INIT: 1858 { 1859 status = intel_fcs_ecdsa_get_pubkey_init(x2, x3, x4, x5, x6, 1860 &mbox_error); 1861 SMC_RET1(handle, status); 1862 } 1863 1864 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_GET_PUBKEY_FINALIZE: 1865 { 1866 status = intel_fcs_ecdsa_get_pubkey_finalize(smc_fid, x1, x2, x3, 1867 x4, (uint32_t *) &x5, &mbox_error); 1868 SMC_RET1(handle, status); 1869 } 1870 1871 case ALTERA_SIP_SMC_ASYNC_FCS_ECDH_REQUEST_INIT: 1872 { 1873 status = intel_fcs_ecdh_request_init(x2, x3, x4, x5, x6, 1874 &mbox_error); 1875 SMC_RET1(handle, status); 1876 } 1877 1878 case ALTERA_SIP_SMC_ASYNC_FCS_ECDH_REQUEST_FINALIZE: 1879 { 1880 uint32_t dest_size = (uint32_t)x7; 1881 1882 NOTICE("MBOX: %s, %d: x7 0x%x, dest_size 0x%x\n", 1883 __func__, __LINE__, (uint32_t)x7, dest_size); 1884 1885 status = intel_fcs_ecdh_request_finalize(smc_fid, x1, x2, x3, 1886 x4, x5, x6, (uint32_t *) &dest_size, 1887 &mbox_error); 1888 SMC_RET1(handle, status); 1889 } 1890 1891 case ALTERA_SIP_SMC_ASYNC_MCTP_MSG: 1892 { 1893 uint32_t *src_addr = (uint32_t *)x2; 1894 uint32_t src_size = (uint32_t)x3; 1895 uint32_t *dst_addr = (uint32_t *)x4; 1896 1897 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1898 GET_JOB_ID(x1), 1899 MBOX_CMD_MCTP_MSG, 1900 src_addr, 1901 src_size / MBOX_WORD_BYTE, 1902 MBOX_CMD_FLAG_CASUAL, 1903 sip_smc_ret_nbytes_cb, 1904 dst_addr, 1905 2); 1906 1907 SMC_RET1(handle, status); 1908 } 1909 1910 case ALTERA_SIP_SMC_ASYNC_FCS_HKDF_REQUEST: 1911 { 1912 status = intel_fcs_hkdf_request(smc_fid, x1, x2, x3, x4, x5, x6, 1913 x7); 1914 SMC_RET1(handle, status); 1915 } 1916 1917 default: 1918 return socfpga_sip_handler(smc_fid, x1, x2, x3, x4, 1919 cookie, handle, flags); 1920 } /* switch (smc_fid) */ 1921 } 1922 #endif 1923 1924 /* 1925 * This function is responsible for handling all SiP calls from the NS world 1926 */ 1927 1928 uintptr_t sip_smc_handler_v1(uint32_t smc_fid, 1929 u_register_t x1, 1930 u_register_t x2, 1931 u_register_t x3, 1932 u_register_t x4, 1933 void *cookie, 1934 void *handle, 1935 u_register_t flags) 1936 { 1937 uint32_t retval = 0, completed_addr[3]; 1938 uint32_t retval2 = 0; 1939 uint32_t mbox_error = 0; 1940 uint32_t err_states = 0; 1941 uint64_t retval64, rsu_respbuf[9]; 1942 uint32_t seu_respbuf[3]; 1943 int status = INTEL_SIP_SMC_STATUS_OK; 1944 int mbox_status; 1945 unsigned int len_in_resp = 0; 1946 u_register_t x5, x6, x7; 1947 1948 switch (smc_fid) { 1949 case SIP_SVC_UID: 1950 /* Return UID to the caller */ 1951 SMC_UUID_RET(handle, intl_svc_uid); 1952 1953 case INTEL_SIP_SMC_FPGA_CONFIG_ISDONE: 1954 status = intel_mailbox_fpga_config_isdone(&err_states); 1955 SMC_RET4(handle, status, err_states, 0, 0); 1956 1957 case INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM: 1958 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 1959 INTEL_SIP_SMC_FPGA_CONFIG_ADDR, 1960 INTEL_SIP_SMC_FPGA_CONFIG_SIZE - 1961 INTEL_SIP_SMC_FPGA_CONFIG_ADDR); 1962 1963 case INTEL_SIP_SMC_FPGA_CONFIG_START: 1964 status = intel_fpga_config_start(x1); 1965 SMC_RET4(handle, status, 0, 0, 0); 1966 1967 case INTEL_SIP_SMC_FPGA_CONFIG_WRITE: 1968 status = intel_fpga_config_write(x1, x2); 1969 SMC_RET4(handle, status, 0, 0, 0); 1970 1971 case INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE: 1972 status = intel_fpga_config_completed_write(completed_addr, 1973 &retval, &rcv_id); 1974 switch (retval) { 1975 case 1: 1976 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 1977 completed_addr[0], 0, 0); 1978 1979 case 2: 1980 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 1981 completed_addr[0], 1982 completed_addr[1], 0); 1983 1984 case 3: 1985 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 1986 completed_addr[0], 1987 completed_addr[1], 1988 completed_addr[2]); 1989 1990 case 0: 1991 SMC_RET4(handle, status, 0, 0, 0); 1992 1993 default: 1994 mailbox_clear_response(); 1995 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR); 1996 } 1997 1998 case INTEL_SIP_SMC_REG_READ: 1999 status = intel_secure_reg_read(x1, &retval); 2000 SMC_RET3(handle, status, retval, x1); 2001 2002 case INTEL_SIP_SMC_REG_WRITE: 2003 status = intel_secure_reg_write(x1, (uint32_t)x2, &retval); 2004 SMC_RET3(handle, status, retval, x1); 2005 2006 case INTEL_SIP_SMC_REG_UPDATE: 2007 status = intel_secure_reg_update(x1, (uint32_t)x2, 2008 (uint32_t)x3, &retval); 2009 SMC_RET3(handle, status, retval, x1); 2010 2011 case INTEL_SIP_SMC_RSU_STATUS: 2012 status = intel_rsu_status(rsu_respbuf, 2013 ARRAY_SIZE(rsu_respbuf)); 2014 if (status) { 2015 SMC_RET1(handle, status); 2016 } else { 2017 SMC_RET4(handle, rsu_respbuf[0], rsu_respbuf[1], 2018 rsu_respbuf[2], rsu_respbuf[3]); 2019 } 2020 2021 case INTEL_SIP_SMC_RSU_UPDATE: 2022 status = intel_rsu_update(x1); 2023 SMC_RET1(handle, status); 2024 2025 case INTEL_SIP_SMC_RSU_NOTIFY: 2026 status = intel_rsu_notify(x1); 2027 SMC_RET1(handle, status); 2028 2029 case INTEL_SIP_SMC_RSU_RETRY_COUNTER: 2030 status = intel_rsu_retry_counter((uint32_t *)rsu_respbuf, 2031 ARRAY_SIZE(rsu_respbuf), &retval); 2032 if (status) { 2033 SMC_RET1(handle, status); 2034 } else { 2035 SMC_RET2(handle, status, retval); 2036 } 2037 2038 case INTEL_SIP_SMC_RSU_DCMF_VERSION: 2039 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 2040 ((uint64_t)rsu_dcmf_ver[1] << 32) | rsu_dcmf_ver[0], 2041 ((uint64_t)rsu_dcmf_ver[3] << 32) | rsu_dcmf_ver[2]); 2042 2043 case INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION: 2044 status = intel_rsu_copy_dcmf_version(x1, x2); 2045 SMC_RET1(handle, status); 2046 2047 case INTEL_SIP_SMC_RSU_GET_DEVICE_INFO: 2048 status = intel_rsu_get_device_info((uint32_t *)rsu_respbuf, 2049 ARRAY_SIZE(rsu_respbuf)); 2050 if (status) { 2051 SMC_RET1(handle, status); 2052 } else { 2053 SMC_RET5(handle, status, rsu_respbuf[0], rsu_respbuf[1], 2054 rsu_respbuf[2], rsu_respbuf[3]); 2055 } 2056 2057 case INTEL_SIP_SMC_RSU_DCMF_STATUS: 2058 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, 2059 ((uint64_t)rsu_dcmf_stat[3] << 48) | 2060 ((uint64_t)rsu_dcmf_stat[2] << 32) | 2061 ((uint64_t)rsu_dcmf_stat[1] << 16) | 2062 rsu_dcmf_stat[0]); 2063 2064 case INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS: 2065 status = intel_rsu_copy_dcmf_status(x1); 2066 SMC_RET1(handle, status); 2067 2068 case INTEL_SIP_SMC_RSU_MAX_RETRY: 2069 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, rsu_max_retry); 2070 2071 case INTEL_SIP_SMC_RSU_COPY_MAX_RETRY: 2072 rsu_max_retry = x1; 2073 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_OK); 2074 2075 case INTEL_SIP_SMC_ECC_DBE: 2076 status = intel_ecc_dbe_notification(x1); 2077 SMC_RET1(handle, status); 2078 2079 case INTEL_SIP_SMC_SERVICE_COMPLETED: 2080 status = intel_smc_service_completed(x1, x2, x3, &rcv_id, 2081 &len_in_resp, &mbox_error); 2082 SMC_RET4(handle, status, mbox_error, x1, len_in_resp); 2083 2084 case INTEL_SIP_SMC_FIRMWARE_VERSION: 2085 status = intel_smc_fw_version(&retval); 2086 SMC_RET2(handle, status, retval); 2087 2088 case INTEL_SIP_SMC_MBOX_SEND_CMD: 2089 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2090 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2091 status = intel_mbox_send_cmd(x1, (uint32_t *)x2, x3, x4, x5, x6, 2092 &mbox_status, &len_in_resp); 2093 SMC_RET3(handle, status, mbox_status, len_in_resp); 2094 2095 case INTEL_SIP_SMC_GET_USERCODE: 2096 status = intel_smc_get_usercode(&retval); 2097 SMC_RET2(handle, status, retval); 2098 2099 case INTEL_SIP_SMC_FCS_CRYPTION: 2100 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2101 2102 if (x1 == FCS_MODE_DECRYPT) { 2103 status = intel_fcs_decryption(x2, x3, x4, x5, &send_id); 2104 } else if (x1 == FCS_MODE_ENCRYPT) { 2105 status = intel_fcs_encryption(x2, x3, x4, x5, &send_id); 2106 } else { 2107 status = INTEL_SIP_SMC_STATUS_REJECTED; 2108 } 2109 2110 SMC_RET3(handle, status, x4, x5); 2111 2112 case INTEL_SIP_SMC_FCS_CRYPTION_EXT: 2113 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2114 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2115 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2116 2117 if (x3 == FCS_MODE_DECRYPT) { 2118 status = intel_fcs_decryption_ext(smc_fid, 0, x1, x2, x4, x5, x6, 2119 (uint32_t *) &x7, &mbox_error, 0, 0, 0); 2120 } else if (x3 == FCS_MODE_ENCRYPT) { 2121 status = intel_fcs_encryption_ext(smc_fid, 0, x1, x2, x4, x5, x6, 2122 (uint32_t *) &x7, &mbox_error, 0, 0); 2123 } else { 2124 status = INTEL_SIP_SMC_STATUS_REJECTED; 2125 } 2126 2127 SMC_RET4(handle, status, mbox_error, x6, x7); 2128 2129 case INTEL_SIP_SMC_FCS_RANDOM_NUMBER: 2130 status = intel_fcs_random_number_gen(x1, &retval64, 2131 &mbox_error); 2132 SMC_RET4(handle, status, mbox_error, x1, retval64); 2133 2134 case INTEL_SIP_SMC_FCS_RANDOM_NUMBER_EXT: 2135 status = intel_fcs_random_number_gen_ext(x1, x2, x3, 2136 &send_id); 2137 SMC_RET1(handle, status); 2138 2139 case INTEL_SIP_SMC_FCS_SEND_CERTIFICATE: 2140 status = intel_fcs_send_cert(smc_fid, 0, x1, x2, &send_id); 2141 SMC_RET1(handle, status); 2142 2143 case INTEL_SIP_SMC_FCS_GET_PROVISION_DATA: 2144 status = intel_fcs_get_provision_data(&send_id); 2145 SMC_RET1(handle, status); 2146 2147 case INTEL_SIP_SMC_FCS_CNTR_SET_PREAUTH: 2148 status = intel_fcs_cntr_set_preauth(smc_fid, 0, x1, x2, x3, 2149 &mbox_error); 2150 SMC_RET2(handle, status, mbox_error); 2151 2152 case INTEL_SIP_SMC_HPS_SET_BRIDGES: 2153 status = intel_hps_set_bridges(x1, x2); 2154 SMC_RET1(handle, status); 2155 2156 case INTEL_SIP_SMC_HWMON_READTEMP: 2157 status = intel_hwmon_readtemp(x1, &retval); 2158 SMC_RET2(handle, status, retval); 2159 2160 case INTEL_SIP_SMC_HWMON_READVOLT: 2161 status = intel_hwmon_readvolt(x1, &retval); 2162 SMC_RET2(handle, status, retval); 2163 2164 case INTEL_SIP_SMC_FCS_PSGSIGMA_TEARDOWN: 2165 status = intel_fcs_sigma_teardown(x1, &mbox_error); 2166 SMC_RET2(handle, status, mbox_error); 2167 2168 case INTEL_SIP_SMC_FCS_CHIP_ID: 2169 status = intel_fcs_chip_id(&retval, &retval2, &mbox_error); 2170 SMC_RET4(handle, status, mbox_error, retval, retval2); 2171 2172 case INTEL_SIP_SMC_FCS_ATTESTATION_SUBKEY: 2173 status = intel_fcs_attestation_subkey(x1, x2, x3, 2174 (uint32_t *) &x4, &mbox_error); 2175 SMC_RET4(handle, status, mbox_error, x3, x4); 2176 2177 case INTEL_SIP_SMC_FCS_ATTESTATION_MEASUREMENTS: 2178 status = intel_fcs_get_measurement(x1, x2, x3, 2179 (uint32_t *) &x4, &mbox_error); 2180 SMC_RET4(handle, status, mbox_error, x3, x4); 2181 2182 case INTEL_SIP_SMC_FCS_GET_ATTESTATION_CERT: 2183 status = intel_fcs_get_attestation_cert(smc_fid, 0, x1, x2, 2184 (uint32_t *) &x3, &mbox_error); 2185 SMC_RET4(handle, status, mbox_error, x2, x3); 2186 2187 case INTEL_SIP_SMC_FCS_CREATE_CERT_ON_RELOAD: 2188 status = intel_fcs_create_cert_on_reload(smc_fid, 0, x1, &mbox_error); 2189 SMC_RET2(handle, status, mbox_error); 2190 2191 case INTEL_SIP_SMC_FCS_OPEN_CS_SESSION: 2192 status = intel_fcs_open_crypto_service_session(&retval, &mbox_error); 2193 SMC_RET3(handle, status, mbox_error, retval); 2194 2195 case INTEL_SIP_SMC_FCS_CLOSE_CS_SESSION: 2196 status = intel_fcs_close_crypto_service_session(x1, &mbox_error); 2197 SMC_RET2(handle, status, mbox_error); 2198 2199 case INTEL_SIP_SMC_FCS_IMPORT_CS_KEY: 2200 status = intel_fcs_import_crypto_service_key(x1, x2, &send_id); 2201 SMC_RET1(handle, status); 2202 2203 case INTEL_SIP_SMC_FCS_EXPORT_CS_KEY: 2204 status = intel_fcs_export_crypto_service_key(x1, x2, x3, 2205 (uint32_t *) &x4, &mbox_error); 2206 SMC_RET4(handle, status, mbox_error, x3, x4); 2207 2208 case INTEL_SIP_SMC_FCS_REMOVE_CS_KEY: 2209 status = intel_fcs_remove_crypto_service_key(x1, x2, 2210 &mbox_error); 2211 SMC_RET2(handle, status, mbox_error); 2212 2213 case INTEL_SIP_SMC_FCS_GET_CS_KEY_INFO: 2214 status = intel_fcs_get_crypto_service_key_info(x1, x2, x3, 2215 (uint32_t *) &x4, &mbox_error); 2216 SMC_RET4(handle, status, mbox_error, x3, x4); 2217 2218 case INTEL_SIP_SMC_FCS_GET_DIGEST_INIT: 2219 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2220 status = intel_fcs_get_digest_init(x1, x2, x3, 2221 x4, x5, &mbox_error); 2222 SMC_RET2(handle, status, mbox_error); 2223 2224 case INTEL_SIP_SMC_FCS_GET_DIGEST_UPDATE: 2225 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2226 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2227 status = intel_fcs_get_digest_update_finalize(smc_fid, 0, x1, x2, 2228 x3, x4, x5, (uint32_t *) &x6, false, 2229 &mbox_error, 0); 2230 SMC_RET4(handle, status, mbox_error, x5, x6); 2231 2232 case INTEL_SIP_SMC_FCS_GET_DIGEST_FINALIZE: 2233 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2234 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2235 status = intel_fcs_get_digest_update_finalize(smc_fid, 0, x1, x2, 2236 x3, x4, x5, (uint32_t *) &x6, true, 2237 &mbox_error, 0); 2238 SMC_RET4(handle, status, mbox_error, x5, x6); 2239 2240 case INTEL_SIP_SMC_FCS_GET_DIGEST_SMMU_UPDATE: 2241 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2242 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2243 status = intel_fcs_get_digest_smmu_update_finalize(x1, x2, x3, 2244 x4, x5, (uint32_t *) &x6, false, 2245 &mbox_error, &send_id); 2246 SMC_RET4(handle, status, mbox_error, x5, x6); 2247 2248 case INTEL_SIP_SMC_FCS_GET_DIGEST_SMMU_FINALIZE: 2249 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2250 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2251 status = intel_fcs_get_digest_smmu_update_finalize(x1, x2, x3, 2252 x4, x5, (uint32_t *) &x6, true, 2253 &mbox_error, &send_id); 2254 SMC_RET4(handle, status, mbox_error, x5, x6); 2255 2256 case INTEL_SIP_SMC_FCS_MAC_VERIFY_INIT: 2257 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2258 status = intel_fcs_mac_verify_init(x1, x2, x3, 2259 x4, x5, &mbox_error); 2260 SMC_RET2(handle, status, mbox_error); 2261 2262 case INTEL_SIP_SMC_FCS_MAC_VERIFY_UPDATE: 2263 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2264 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2265 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2266 status = intel_fcs_mac_verify_update_finalize(smc_fid, 0, x1, x2, 2267 x3, x4, x5, (uint32_t *) &x6, x7, false, 2268 &mbox_error, 0); 2269 SMC_RET4(handle, status, mbox_error, x5, x6); 2270 2271 case INTEL_SIP_SMC_FCS_MAC_VERIFY_FINALIZE: 2272 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2273 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2274 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2275 status = intel_fcs_mac_verify_update_finalize(smc_fid, 0, x1, x2, 2276 x3, x4, x5, (uint32_t *) &x6, x7, true, 2277 &mbox_error, 0); 2278 SMC_RET4(handle, status, mbox_error, x5, x6); 2279 2280 case INTEL_SIP_SMC_FCS_MAC_VERIFY_SMMU_UPDATE: 2281 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2282 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2283 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2284 status = intel_fcs_mac_verify_smmu_update_finalize(x1, x2, x3, 2285 x4, x5, (uint32_t *) &x6, x7, 2286 false, &mbox_error, &send_id); 2287 SMC_RET4(handle, status, mbox_error, x5, x6); 2288 2289 case INTEL_SIP_SMC_FCS_MAC_VERIFY_SMMU_FINALIZE: 2290 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2291 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2292 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2293 status = intel_fcs_mac_verify_smmu_update_finalize(x1, x2, x3, 2294 x4, x5, (uint32_t *) &x6, x7, 2295 true, &mbox_error, &send_id); 2296 SMC_RET4(handle, status, mbox_error, x5, x6); 2297 2298 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_INIT: 2299 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2300 status = intel_fcs_ecdsa_sha2_data_sign_init(x1, x2, x3, 2301 x4, x5, &mbox_error); 2302 SMC_RET2(handle, status, mbox_error); 2303 2304 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_UPDATE: 2305 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2306 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2307 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(smc_fid, 2308 0, x1, x2, x3, x4, x5, (uint32_t *) &x6, 2309 false, &mbox_error, 0); 2310 SMC_RET4(handle, status, mbox_error, x5, x6); 2311 2312 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE: 2313 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2314 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2315 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(smc_fid, 2316 0, x1, x2, x3, x4, x5, (uint32_t *) &x6, 2317 true, &mbox_error, 0); 2318 SMC_RET4(handle, status, mbox_error, x5, x6); 2319 2320 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_UPDATE: 2321 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2322 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2323 status = intel_fcs_ecdsa_sha2_data_sign_smmu_update_finalize(x1, 2324 x2, x3, x4, x5, (uint32_t *) &x6, false, 2325 &mbox_error, &send_id); 2326 SMC_RET4(handle, status, mbox_error, x5, x6); 2327 2328 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_FINALIZE: 2329 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2330 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2331 status = intel_fcs_ecdsa_sha2_data_sign_smmu_update_finalize(x1, 2332 x2, x3, x4, x5, (uint32_t *) &x6, true, 2333 &mbox_error, &send_id); 2334 SMC_RET4(handle, status, mbox_error, x5, x6); 2335 2336 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_INIT: 2337 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2338 status = intel_fcs_ecdsa_hash_sign_init(x1, x2, x3, 2339 x4, x5, &mbox_error); 2340 SMC_RET2(handle, status, mbox_error); 2341 2342 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_FINALIZE: 2343 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2344 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2345 status = intel_fcs_ecdsa_hash_sign_finalize(smc_fid, 0, x1, x2, 2346 x3, x4, x5, (uint32_t *) &x6, 2347 &mbox_error); 2348 SMC_RET4(handle, status, mbox_error, x5, x6); 2349 2350 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_INIT: 2351 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2352 status = intel_fcs_ecdsa_hash_sig_verify_init(x1, x2, x3, 2353 x4, x5, &mbox_error); 2354 SMC_RET2(handle, status, mbox_error); 2355 2356 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_FINALIZE: 2357 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2358 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2359 status = intel_fcs_ecdsa_hash_sig_verify_finalize(smc_fid, 0, x1, 2360 x2, x3, x4, x5, (uint32_t *) &x6, 2361 &mbox_error); 2362 SMC_RET4(handle, status, mbox_error, x5, x6); 2363 2364 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_INIT: 2365 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2366 status = intel_fcs_ecdsa_sha2_data_sig_verify_init(x1, x2, x3, 2367 x4, x5, &mbox_error); 2368 SMC_RET2(handle, status, mbox_error); 2369 2370 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_UPDATE: 2371 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2372 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2373 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2374 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize( 2375 smc_fid, 0, x1, x2, x3, x4, x5, 2376 (uint32_t *) &x6, x7, false, 2377 &mbox_error, 0); 2378 SMC_RET4(handle, status, mbox_error, x5, x6); 2379 2380 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_UPDATE: 2381 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2382 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2383 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2384 status = intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize( 2385 x1, x2, x3, x4, x5, (uint32_t *) &x6, 2386 x7, false, &mbox_error, &send_id); 2387 SMC_RET4(handle, status, mbox_error, x5, x6); 2388 2389 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_FINALIZE: 2390 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2391 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2392 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2393 status = intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize( 2394 x1, x2, x3, x4, x5, (uint32_t *) &x6, 2395 x7, true, &mbox_error, &send_id); 2396 SMC_RET4(handle, status, mbox_error, x5, x6); 2397 2398 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE: 2399 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2400 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2401 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2402 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize( 2403 smc_fid, 0, x1, x2, x3, x4, x5, 2404 (uint32_t *) &x6, x7, true, 2405 &mbox_error, 0); 2406 SMC_RET4(handle, status, mbox_error, x5, x6); 2407 2408 case INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_INIT: 2409 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2410 status = intel_fcs_ecdsa_get_pubkey_init(x1, x2, x3, 2411 x4, x5, &mbox_error); 2412 SMC_RET2(handle, status, mbox_error); 2413 2414 case INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_FINALIZE: 2415 status = intel_fcs_ecdsa_get_pubkey_finalize( 2416 INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_FINALIZE, 0, 2417 x1, x2, x3, (uint32_t *) &x4, &mbox_error); 2418 SMC_RET4(handle, status, mbox_error, x3, x4); 2419 2420 case INTEL_SIP_SMC_FCS_ECDH_REQUEST_INIT: 2421 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2422 status = intel_fcs_ecdh_request_init(x1, x2, x3, 2423 x4, x5, &mbox_error); 2424 SMC_RET2(handle, status, mbox_error); 2425 2426 case INTEL_SIP_SMC_FCS_ECDH_REQUEST_FINALIZE: 2427 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2428 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2429 status = intel_fcs_ecdh_request_finalize(smc_fid, 0, x1, x2, x3, 2430 x4, x5, (uint32_t *) &x6, &mbox_error); 2431 SMC_RET4(handle, status, mbox_error, x5, x6); 2432 2433 case INTEL_SIP_SMC_FCS_AES_CRYPT_INIT: 2434 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2435 status = intel_fcs_aes_crypt_init(x1, x2, x3, x4, x5, 2436 &mbox_error); 2437 SMC_RET2(handle, status, mbox_error); 2438 2439 case INTEL_SIP_SMC_FCS_AES_CRYPT_UPDATE: 2440 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2441 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2442 status = intel_fcs_aes_crypt_update_finalize(smc_fid, 0, x1, x2, 2443 x3, x4, x5, x6, 0, false, &send_id, 0, 0); 2444 SMC_RET1(handle, status); 2445 2446 case INTEL_SIP_SMC_FCS_AES_CRYPT_FINALIZE: 2447 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2448 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2449 status = intel_fcs_aes_crypt_update_finalize(smc_fid, 0, x1, x2, 2450 x3, x4, x5, x6, 0, true, &send_id, 0, 0); 2451 SMC_RET1(handle, status); 2452 2453 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 2454 case INTEL_SIP_SMC_FCS_SDM_REMAPPER_CONFIG: 2455 status = intel_smmu_hps_remapper_config(x1); 2456 SMC_RET1(handle, status); 2457 #endif 2458 2459 case INTEL_SIP_SMC_GET_ROM_PATCH_SHA384: 2460 status = intel_fcs_get_rom_patch_sha384(x1, &retval64, 2461 &mbox_error); 2462 SMC_RET4(handle, status, mbox_error, x1, retval64); 2463 2464 case INTEL_SIP_SMC_SVC_VERSION: 2465 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 2466 SIP_SVC_VERSION_MAJOR, 2467 SIP_SVC_VERSION_MINOR); 2468 2469 case INTEL_SIP_SMC_SEU_ERR_STATUS: 2470 status = intel_sdm_seu_err_read(seu_respbuf, 2471 ARRAY_SIZE(seu_respbuf)); 2472 if (status) { 2473 SMC_RET1(handle, status); 2474 } else { 2475 SMC_RET3(handle, seu_respbuf[0], seu_respbuf[1], seu_respbuf[2]); 2476 } 2477 2478 case INTEL_SIP_SMC_SAFE_INJECT_SEU_ERR: 2479 status = intel_sdm_safe_inject_seu_err((uint32_t *)&x1, (uint32_t)x2); 2480 SMC_RET1(handle, status); 2481 2482 case INTEL_SIP_SMC_ATF_BUILD_VER: 2483 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, VERSION_MAJOR, 2484 VERSION_MINOR, VERSION_PATCH); 2485 2486 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 2487 case INTEL_SIP_SMC_INJECT_IO96B_ECC_ERR: 2488 intel_inject_io96b_ecc_err((uint32_t *)&x1, (uint32_t)x2); 2489 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_OK); 2490 #endif 2491 2492 default: 2493 return socfpga_sip_handler(smc_fid, x1, x2, x3, x4, 2494 cookie, handle, flags); 2495 } 2496 } 2497 2498 uintptr_t sip_smc_handler(uint32_t smc_fid, 2499 u_register_t x1, 2500 u_register_t x2, 2501 u_register_t x3, 2502 u_register_t x4, 2503 void *cookie, 2504 void *handle, 2505 u_register_t flags) 2506 { 2507 uint32_t cmd = smc_fid & INTEL_SIP_SMC_CMD_MASK; 2508 2509 if (cmd >= INTEL_SIP_SMC_CMD_V2_RANGE_BEGIN && 2510 cmd <= INTEL_SIP_SMC_CMD_V2_RANGE_END) { 2511 return sip_smc_handler_v2(smc_fid, x1, x2, x3, x4, 2512 cookie, handle, flags); 2513 } 2514 #if SIP_SVC_V3 2515 else if ((cmd >= INTEL_SIP_SMC_CMD_V3_RANGE_BEGIN) && 2516 (cmd <= INTEL_SIP_SMC_CMD_V3_RANGE_END)) { 2517 uintptr_t ret = sip_smc_handler_v3(smc_fid, x1, x2, x3, x4, 2518 cookie, handle, flags); 2519 return ret; 2520 } 2521 #endif 2522 else { 2523 return sip_smc_handler_v1(smc_fid, x1, x2, x3, x4, 2524 cookie, handle, flags); 2525 } 2526 } 2527 2528 DECLARE_RT_SVC( 2529 socfpga_sip_svc, 2530 OEN_SIP_START, 2531 OEN_SIP_END, 2532 SMC_TYPE_FAST, 2533 NULL, 2534 sip_smc_handler 2535 ); 2536 2537 DECLARE_RT_SVC( 2538 socfpga_sip_svc_std, 2539 OEN_SIP_START, 2540 OEN_SIP_END, 2541 SMC_TYPE_YIELD, 2542 NULL, 2543 sip_smc_handler 2544 ); 2545