1 /* 2 * Copyright (c) 2019-2023, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. 4 * Copyright (c) 2024-2025, Altera Corporation. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #include <assert.h> 10 #include <common/debug.h> 11 #include <common/runtime_svc.h> 12 #include <drivers/delay_timer.h> 13 #include <lib/mmio.h> 14 #include <tools_share/uuid.h> 15 16 #include "socfpga_fcs.h" 17 #include "socfpga_mailbox.h" 18 #include "socfpga_plat_def.h" 19 #include "socfpga_reset_manager.h" 20 #include "socfpga_sip_svc.h" 21 #include "socfpga_system_manager.h" 22 23 /* Total buffer the driver can hold */ 24 #define FPGA_CONFIG_BUFFER_SIZE 4 25 26 static config_type request_type = NO_REQUEST; 27 static int current_block, current_buffer; 28 static int read_block, max_blocks; 29 static uint32_t send_id, rcv_id; 30 static uint32_t bytes_per_block, blocks_submitted; 31 static bool bridge_disable; 32 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 33 static uint32_t g_remapper_bypass; 34 #endif 35 36 /* RSU static variables */ 37 static uint32_t rsu_dcmf_ver[4] = {0}; 38 static uint16_t rsu_dcmf_stat[4] = {0}; 39 static uint32_t rsu_max_retry; 40 41 /* SiP Service UUID */ 42 DEFINE_SVC_UUID2(intl_svc_uid, 43 0xa85273b0, 0xe85a, 0x4862, 0xa6, 0x2a, 44 0xfa, 0x88, 0x88, 0x17, 0x68, 0x81); 45 46 static uint64_t socfpga_sip_handler(uint32_t smc_fid, 47 uint64_t x1, 48 uint64_t x2, 49 uint64_t x3, 50 uint64_t x4, 51 void *cookie, 52 void *handle, 53 uint64_t flags) 54 { 55 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); 56 SMC_RET1(handle, SMC_UNK); 57 } 58 59 struct fpga_config_info fpga_config_buffers[FPGA_CONFIG_BUFFER_SIZE]; 60 61 static int intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer) 62 { 63 uint32_t args[3]; 64 65 while (max_blocks > 0 && buffer->size > buffer->size_written) { 66 args[0] = (1<<8); 67 args[1] = buffer->addr + buffer->size_written; 68 if (buffer->size - buffer->size_written <= bytes_per_block) { 69 args[2] = buffer->size - buffer->size_written; 70 current_buffer++; 71 current_buffer %= FPGA_CONFIG_BUFFER_SIZE; 72 } else { 73 args[2] = bytes_per_block; 74 } 75 76 buffer->size_written += args[2]; 77 mailbox_send_cmd_async(&send_id, MBOX_RECONFIG_DATA, args, 78 3U, CMD_INDIRECT); 79 80 buffer->subblocks_sent++; 81 max_blocks--; 82 } 83 84 return !max_blocks; 85 } 86 87 static int intel_fpga_sdm_write_all(void) 88 { 89 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 90 if (intel_fpga_sdm_write_buffer( 91 &fpga_config_buffers[current_buffer])) { 92 break; 93 } 94 } 95 return 0; 96 } 97 98 static uint32_t intel_mailbox_fpga_config_isdone(uint32_t *err_states) 99 { 100 uint32_t ret; 101 102 if (err_states == NULL) 103 return INTEL_SIP_SMC_STATUS_REJECTED; 104 105 switch (request_type) { 106 case RECONFIGURATION: 107 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, 108 true, err_states); 109 break; 110 case BITSTREAM_AUTH: 111 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, 112 false, err_states); 113 break; 114 default: 115 ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS, 116 false, err_states); 117 break; 118 } 119 120 if (ret != 0U) { 121 if (ret == MBOX_CFGSTAT_STATE_CONFIG) { 122 return INTEL_SIP_SMC_STATUS_BUSY; 123 } else { 124 request_type = NO_REQUEST; 125 return INTEL_SIP_SMC_STATUS_ERROR; 126 } 127 } 128 129 if (bridge_disable != 0U) { 130 socfpga_bridges_enable(~0); /* Enable bridge */ 131 bridge_disable = false; 132 } 133 request_type = NO_REQUEST; 134 135 return INTEL_SIP_SMC_STATUS_OK; 136 } 137 138 static int mark_last_buffer_xfer_completed(uint32_t *buffer_addr_completed) 139 { 140 int i; 141 142 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 143 if (fpga_config_buffers[i].block_number == current_block) { 144 fpga_config_buffers[i].subblocks_sent--; 145 if (fpga_config_buffers[i].subblocks_sent == 0 146 && fpga_config_buffers[i].size <= 147 fpga_config_buffers[i].size_written) { 148 fpga_config_buffers[i].write_requested = 0; 149 current_block++; 150 *buffer_addr_completed = 151 fpga_config_buffers[i].addr; 152 return 0; 153 } 154 } 155 } 156 157 return -1; 158 } 159 160 static int intel_fpga_config_completed_write(uint32_t *completed_addr, 161 uint32_t *count, uint32_t *job_id) 162 { 163 uint32_t resp[5]; 164 unsigned int resp_len = ARRAY_SIZE(resp); 165 int status = INTEL_SIP_SMC_STATUS_OK; 166 int all_completed = 1; 167 *count = 0; 168 169 while (*count < 3) { 170 171 status = mailbox_read_response(job_id, 172 resp, &resp_len); 173 174 if (status < 0) { 175 break; 176 } 177 178 max_blocks++; 179 180 if (mark_last_buffer_xfer_completed( 181 &completed_addr[*count]) == 0) { 182 *count = *count + 1; 183 } else { 184 break; 185 } 186 } 187 188 if (*count <= 0) { 189 if (status != MBOX_NO_RESPONSE && 190 status != MBOX_TIMEOUT && resp_len != 0) { 191 mailbox_clear_response(); 192 request_type = NO_REQUEST; 193 return INTEL_SIP_SMC_STATUS_ERROR; 194 } 195 196 *count = 0; 197 } 198 199 intel_fpga_sdm_write_all(); 200 201 if (*count > 0) { 202 status = INTEL_SIP_SMC_STATUS_OK; 203 } else if (*count == 0) { 204 status = INTEL_SIP_SMC_STATUS_BUSY; 205 } 206 207 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 208 if (fpga_config_buffers[i].write_requested != 0) { 209 all_completed = 0; 210 break; 211 } 212 } 213 214 if (all_completed == 1) { 215 return INTEL_SIP_SMC_STATUS_OK; 216 } 217 218 return status; 219 } 220 221 static int intel_fpga_config_start(uint32_t flag) 222 { 223 uint32_t argument = 0x1; 224 uint32_t response[3]; 225 int status = 0; 226 unsigned int size = 0; 227 unsigned int resp_len = ARRAY_SIZE(response); 228 229 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 230 /* 231 * To trigger isolation 232 * FPGA configuration complete signal should be de-asserted 233 */ 234 INFO("SOCFPGA: Request SDM to trigger isolation\n"); 235 status = mailbox_send_fpga_config_comp(); 236 237 if (status < 0) { 238 INFO("SOCFPGA: Isolation for FPGA configuration complete is not executed\n"); 239 } 240 #endif 241 242 request_type = RECONFIGURATION; 243 244 if (!CONFIG_TEST_FLAG(flag, PARTIAL_CONFIG)) { 245 bridge_disable = true; 246 } 247 248 if (CONFIG_TEST_FLAG(flag, AUTHENTICATION)) { 249 size = 1; 250 bridge_disable = false; 251 request_type = BITSTREAM_AUTH; 252 } 253 254 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 255 intel_smmu_hps_remapper_init(0U); 256 #endif 257 258 mailbox_clear_response(); 259 260 mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_CANCEL, NULL, 0U, 261 CMD_CASUAL, NULL, NULL); 262 263 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_RECONFIG, &argument, size, 264 CMD_CASUAL, response, &resp_len); 265 266 if (status < 0) { 267 bridge_disable = false; 268 request_type = NO_REQUEST; 269 return INTEL_SIP_SMC_STATUS_ERROR; 270 } 271 272 max_blocks = response[0]; 273 bytes_per_block = response[1]; 274 275 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 276 fpga_config_buffers[i].size = 0; 277 fpga_config_buffers[i].size_written = 0; 278 fpga_config_buffers[i].addr = 0; 279 fpga_config_buffers[i].write_requested = 0; 280 fpga_config_buffers[i].block_number = 0; 281 fpga_config_buffers[i].subblocks_sent = 0; 282 } 283 284 blocks_submitted = 0; 285 current_block = 0; 286 read_block = 0; 287 current_buffer = 0; 288 289 /* Disable bridge on full reconfiguration */ 290 if (bridge_disable) { 291 socfpga_bridges_disable(~0); 292 } 293 294 return INTEL_SIP_SMC_STATUS_OK; 295 } 296 297 static bool is_fpga_config_buffer_full(void) 298 { 299 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 300 if (!fpga_config_buffers[i].write_requested) { 301 return false; 302 } 303 } 304 return true; 305 } 306 307 bool is_address_in_ddr_range(uint64_t addr, uint64_t size) 308 { 309 uint128_t dram_max_sz = (uint128_t)DRAM_BASE + (uint128_t)DRAM_SIZE; 310 uint128_t dram_region_end = (uint128_t)addr + (uint128_t)size; 311 312 if (!addr && !size) { 313 return true; 314 } 315 if (size > (UINT64_MAX - addr)) { 316 return false; 317 } 318 if (addr < BL31_LIMIT) { 319 return false; 320 } 321 if (dram_region_end > dram_max_sz) { 322 return false; 323 } 324 325 return true; 326 } 327 328 static uint32_t intel_fpga_config_write(uint64_t mem, uint64_t size) 329 { 330 int i; 331 332 intel_fpga_sdm_write_all(); 333 334 if (!is_address_in_ddr_range(mem, size) || 335 is_fpga_config_buffer_full()) { 336 return INTEL_SIP_SMC_STATUS_REJECTED; 337 } 338 339 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 340 intel_smmu_hps_remapper_init(&mem); 341 #endif 342 343 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 344 int j = (i + current_buffer) % FPGA_CONFIG_BUFFER_SIZE; 345 346 if (!fpga_config_buffers[j].write_requested) { 347 fpga_config_buffers[j].addr = mem; 348 fpga_config_buffers[j].size = size; 349 fpga_config_buffers[j].size_written = 0; 350 fpga_config_buffers[j].write_requested = 1; 351 fpga_config_buffers[j].block_number = 352 blocks_submitted++; 353 fpga_config_buffers[j].subblocks_sent = 0; 354 break; 355 } 356 } 357 358 if (is_fpga_config_buffer_full()) { 359 return INTEL_SIP_SMC_STATUS_BUSY; 360 } 361 362 return INTEL_SIP_SMC_STATUS_OK; 363 } 364 365 static int is_out_of_sec_range(uint64_t reg_addr) 366 { 367 #if DEBUG 368 return 0; 369 #endif 370 371 #if PLATFORM_MODEL != PLAT_SOCFPGA_AGILEX5 372 switch (reg_addr) { 373 case(0xF8011100): /* ECCCTRL1 */ 374 case(0xF8011104): /* ECCCTRL2 */ 375 case(0xF8011110): /* ERRINTEN */ 376 case(0xF8011114): /* ERRINTENS */ 377 case(0xF8011118): /* ERRINTENR */ 378 case(0xF801111C): /* INTMODE */ 379 case(0xF8011120): /* INTSTAT */ 380 case(0xF8011124): /* DIAGINTTEST */ 381 case(0xF801112C): /* DERRADDRA */ 382 case(0xFA000000): /* SMMU SCR0 */ 383 case(0xFA000004): /* SMMU SCR1 */ 384 case(0xFA000400): /* SMMU NSCR0 */ 385 case(0xFA004000): /* SMMU SSD0_REG */ 386 case(0xFA000820): /* SMMU SMR8 */ 387 case(0xFA000c20): /* SMMU SCR8 */ 388 case(0xFA028000): /* SMMU CB8_SCTRL */ 389 case(0xFA001020): /* SMMU CBAR8 */ 390 case(0xFA028030): /* SMMU TCR_LPAE */ 391 case(0xFA028020): /* SMMU CB8_TTBR0_LOW */ 392 case(0xFA028024): /* SMMU CB8_PRRR_HIGH */ 393 case(0xFA028038): /* SMMU CB8_PRRR_MIR0 */ 394 case(0xFA02803C): /* SMMU CB8_PRRR_MIR1 */ 395 case(0xFA028010): /* SMMU_CB8)TCR2 */ 396 case(0xFFD080A4): /* SDM SMMU STREAM ID REG */ 397 case(0xFA001820): /* SMMU_CBA2R8 */ 398 case(0xFA000074): /* SMMU_STLBGSTATUS */ 399 case(0xFA0287F4): /* SMMU_CB8_TLBSTATUS */ 400 case(0xFA000060): /* SMMU_STLBIALL */ 401 case(0xFA000070): /* SMMU_STLBGSYNC */ 402 case(0xFA028618): /* CB8_TLBALL */ 403 case(0xFA0287F0): /* CB8_TLBSYNC */ 404 case(0xFFD12028): /* SDMMCGRP_CTRL */ 405 case(0xFFD12044): /* EMAC0 */ 406 case(0xFFD12048): /* EMAC1 */ 407 case(0xFFD1204C): /* EMAC2 */ 408 case(0xFFD12090): /* ECC_INT_MASK_VALUE */ 409 case(0xFFD12094): /* ECC_INT_MASK_SET */ 410 case(0xFFD12098): /* ECC_INT_MASK_CLEAR */ 411 case(0xFFD1209C): /* ECC_INTSTATUS_SERR */ 412 case(0xFFD120A0): /* ECC_INTSTATUS_DERR */ 413 case(0xFFD120C0): /* NOC_TIMEOUT */ 414 case(0xFFD120C4): /* NOC_IDLEREQ_SET */ 415 case(0xFFD120C8): /* NOC_IDLEREQ_CLR */ 416 case(0xFFD120D0): /* NOC_IDLEACK */ 417 case(0xFFD120D4): /* NOC_IDLESTATUS */ 418 case(0xFFD12200): /* BOOT_SCRATCH_COLD0 */ 419 case(0xFFD12204): /* BOOT_SCRATCH_COLD1 */ 420 case(0xFFD12220): /* BOOT_SCRATCH_COLD8 */ 421 case(0xFFD12224): /* BOOT_SCRATCH_COLD9 */ 422 return 0; 423 #else 424 switch (reg_addr) { 425 426 case(0xF8011104): /* ECCCTRL2 */ 427 case(0xFFD12028): /* SDMMCGRP_CTRL */ 428 case(0xFFD120C4): /* NOC_IDLEREQ_SET */ 429 case(0xFFD120C8): /* NOC_IDLEREQ_CLR */ 430 case(0xFFD120D0): /* NOC_IDLEACK */ 431 432 433 case(SOCFPGA_MEMCTRL(ECCCTRL1)): /* ECCCTRL1 */ 434 case(SOCFPGA_MEMCTRL(ERRINTEN)): /* ERRINTEN */ 435 case(SOCFPGA_MEMCTRL(ERRINTENS)): /* ERRINTENS */ 436 case(SOCFPGA_MEMCTRL(ERRINTENR)): /* ERRINTENR */ 437 case(SOCFPGA_MEMCTRL(INTMODE)): /* INTMODE */ 438 case(SOCFPGA_MEMCTRL(INTSTAT)): /* INTSTAT */ 439 case(SOCFPGA_MEMCTRL(DIAGINTTEST)): /* DIAGINTTEST */ 440 case(SOCFPGA_MEMCTRL(DERRADDRA)): /* DERRADDRA */ 441 442 case(SOCFPGA_ECC_QSPI(INITSTAT)): /* ECC_QSPI_INITSTAT */ 443 case(SOCFPGA_SYSMGR(EMAC_0)): /* EMAC0 */ 444 case(SOCFPGA_SYSMGR(EMAC_1)): /* EMAC1 */ 445 case(SOCFPGA_SYSMGR(EMAC_2)): /* EMAC2 */ 446 case(SOCFPGA_SYSMGR(ECC_INTMASK_VALUE)): /* ECC_INT_MASK_VALUE */ 447 case(SOCFPGA_SYSMGR(ECC_INTMASK_SET)): /* ECC_INT_MASK_SET */ 448 case(SOCFPGA_SYSMGR(ECC_INTMASK_CLR)): /* ECC_INT_MASK_CLEAR */ 449 case(SOCFPGA_SYSMGR(ECC_INTMASK_SERR)): /* ECC_INTSTATUS_SERR */ 450 case(SOCFPGA_SYSMGR(ECC_INTMASK_DERR)): /* ECC_INTSTATUS_DERR */ 451 case(SOCFPGA_SYSMGR(NOC_TIMEOUT)): /* NOC_TIMEOUT */ 452 case(SOCFPGA_SYSMGR(NOC_IDLESTATUS)): /* NOC_IDLESTATUS */ 453 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_0)): /* BOOT_SCRATCH_COLD0 */ 454 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_1)): /* BOOT_SCRATCH_COLD1 */ 455 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_8)): /* BOOT_SCRATCH_COLD8 */ 456 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_9)): /* BOOT_SCRATCH_COLD9 */ 457 #endif 458 case(SOCFPGA_ECC_QSPI(CTRL)): /* ECC_QSPI_CTRL */ 459 case(SOCFPGA_ECC_QSPI(ERRINTEN)): /* ECC_QSPI_ERRINTEN */ 460 case(SOCFPGA_ECC_QSPI(ERRINTENS)): /* ECC_QSPI_ERRINTENS */ 461 case(SOCFPGA_ECC_QSPI(ERRINTENR)): /* ECC_QSPI_ERRINTENR */ 462 case(SOCFPGA_ECC_QSPI(INTMODE)): /* ECC_QSPI_INTMODE */ 463 case(SOCFPGA_ECC_QSPI(ECC_ACCCTRL)): /* ECC_QSPI_ECC_ACCCTRL */ 464 case(SOCFPGA_ECC_QSPI(ECC_STARTACC)): /* ECC_QSPI_ECC_STARTACC */ 465 case(SOCFPGA_ECC_QSPI(ECC_WDCTRL)): /* ECC_QSPI_ECC_WDCTRL */ 466 case(SOCFPGA_ECC_QSPI(INTSTAT)): /* ECC_QSPI_INTSTAT */ 467 case(SOCFPGA_ECC_QSPI(INTTEST)): /* ECC_QSPI_INTMODE */ 468 return 0; 469 470 default: 471 break; 472 } 473 474 return -1; 475 } 476 477 /* Secure register access */ 478 uint32_t intel_secure_reg_read(uint64_t reg_addr, uint32_t *retval) 479 { 480 if (is_out_of_sec_range(reg_addr)) { 481 return INTEL_SIP_SMC_STATUS_ERROR; 482 } 483 484 *retval = mmio_read_32(reg_addr); 485 486 return INTEL_SIP_SMC_STATUS_OK; 487 } 488 489 uint32_t intel_secure_reg_write(uint64_t reg_addr, uint32_t val, 490 uint32_t *retval) 491 { 492 if (is_out_of_sec_range(reg_addr)) { 493 return INTEL_SIP_SMC_STATUS_ERROR; 494 } 495 496 switch (reg_addr) { 497 case(SOCFPGA_ECC_QSPI(INTSTAT)): /* ECC_QSPI_INTSTAT */ 498 case(SOCFPGA_ECC_QSPI(INTTEST)): /* ECC_QSPI_INTMODE */ 499 mmio_write_16(reg_addr, val); 500 break; 501 default: 502 mmio_write_32(reg_addr, val); 503 break; 504 } 505 506 return intel_secure_reg_read(reg_addr, retval); 507 } 508 509 uint32_t intel_secure_reg_update(uint64_t reg_addr, uint32_t mask, 510 uint32_t val, uint32_t *retval) 511 { 512 if (!intel_secure_reg_read(reg_addr, retval)) { 513 *retval &= ~mask; 514 *retval |= val & mask; 515 return intel_secure_reg_write(reg_addr, *retval, retval); 516 } 517 518 return INTEL_SIP_SMC_STATUS_ERROR; 519 } 520 521 /* Intel Remote System Update (RSU) services */ 522 uint64_t intel_rsu_update_address; 523 524 static uint32_t intel_rsu_status(uint64_t *respbuf, unsigned int respbuf_sz) 525 { 526 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) { 527 return INTEL_SIP_SMC_RSU_ERROR; 528 } 529 530 return INTEL_SIP_SMC_STATUS_OK; 531 } 532 533 static uint32_t intel_rsu_get_device_info(uint32_t *respbuf, 534 unsigned int respbuf_sz) 535 { 536 if (mailbox_rsu_get_device_info((uint32_t *)respbuf, respbuf_sz) < 0) { 537 return INTEL_SIP_SMC_RSU_ERROR; 538 } 539 540 return INTEL_SIP_SMC_STATUS_OK; 541 } 542 543 uint32_t intel_rsu_update(uint64_t update_address) 544 { 545 if (update_address > SIZE_MAX) { 546 return INTEL_SIP_SMC_STATUS_REJECTED; 547 } 548 549 intel_rsu_update_address = update_address; 550 return INTEL_SIP_SMC_STATUS_OK; 551 } 552 553 static uint32_t intel_rsu_notify(uint32_t execution_stage) 554 { 555 if (mailbox_hps_stage_notify(execution_stage) < 0) { 556 return INTEL_SIP_SMC_RSU_ERROR; 557 } 558 559 return INTEL_SIP_SMC_STATUS_OK; 560 } 561 562 static uint32_t intel_rsu_retry_counter(uint32_t *respbuf, uint32_t respbuf_sz, 563 uint32_t *ret_stat) 564 { 565 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) { 566 return INTEL_SIP_SMC_RSU_ERROR; 567 } 568 569 *ret_stat = respbuf[8]; 570 return INTEL_SIP_SMC_STATUS_OK; 571 } 572 573 static uint32_t intel_rsu_copy_dcmf_version(uint64_t dcmf_ver_1_0, 574 uint64_t dcmf_ver_3_2) 575 { 576 rsu_dcmf_ver[0] = dcmf_ver_1_0; 577 rsu_dcmf_ver[1] = dcmf_ver_1_0 >> 32; 578 rsu_dcmf_ver[2] = dcmf_ver_3_2; 579 rsu_dcmf_ver[3] = dcmf_ver_3_2 >> 32; 580 581 return INTEL_SIP_SMC_STATUS_OK; 582 } 583 584 static uint32_t intel_rsu_copy_dcmf_status(uint64_t dcmf_stat) 585 { 586 rsu_dcmf_stat[0] = 0xFFFF & (dcmf_stat >> (0 * 16)); 587 rsu_dcmf_stat[1] = 0xFFFF & (dcmf_stat >> (1 * 16)); 588 rsu_dcmf_stat[2] = 0xFFFF & (dcmf_stat >> (2 * 16)); 589 rsu_dcmf_stat[3] = 0xFFFF & (dcmf_stat >> (3 * 16)); 590 591 return INTEL_SIP_SMC_STATUS_OK; 592 } 593 594 /* Intel HWMON services */ 595 static uint32_t intel_hwmon_readtemp(uint32_t chan, uint32_t *retval) 596 { 597 if (mailbox_hwmon_readtemp(chan, retval) < 0) { 598 return INTEL_SIP_SMC_STATUS_ERROR; 599 } 600 601 return INTEL_SIP_SMC_STATUS_OK; 602 } 603 604 static uint32_t intel_hwmon_readvolt(uint32_t chan, uint32_t *retval) 605 { 606 if (mailbox_hwmon_readvolt(chan, retval) < 0) { 607 return INTEL_SIP_SMC_STATUS_ERROR; 608 } 609 610 return INTEL_SIP_SMC_STATUS_OK; 611 } 612 613 /* Mailbox services */ 614 static uint32_t intel_smc_fw_version(uint32_t *fw_version) 615 { 616 int status; 617 unsigned int resp_len = CONFIG_STATUS_WORD_SIZE; 618 uint32_t resp_data[CONFIG_STATUS_WORD_SIZE] = {0U}; 619 620 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CONFIG_STATUS, NULL, 0U, 621 CMD_CASUAL, resp_data, &resp_len); 622 623 if (status < 0) { 624 return INTEL_SIP_SMC_STATUS_ERROR; 625 } 626 627 if (resp_len <= CONFIG_STATUS_FW_VER_OFFSET) { 628 return INTEL_SIP_SMC_STATUS_ERROR; 629 } 630 631 *fw_version = resp_data[CONFIG_STATUS_FW_VER_OFFSET] & CONFIG_STATUS_FW_VER_MASK; 632 633 return INTEL_SIP_SMC_STATUS_OK; 634 } 635 636 static uint32_t intel_mbox_send_cmd(uint32_t cmd, uint32_t *args, 637 unsigned int len, uint32_t urgent, uint64_t response, 638 unsigned int resp_len, int *mbox_status, 639 unsigned int *len_in_resp) 640 { 641 *len_in_resp = 0; 642 *mbox_status = GENERIC_RESPONSE_ERROR; 643 644 if (!is_address_in_ddr_range((uint64_t)args, sizeof(uint32_t) * len)) { 645 return INTEL_SIP_SMC_STATUS_REJECTED; 646 } 647 648 int status = mailbox_send_cmd(MBOX_JOB_ID, cmd, args, len, urgent, 649 (uint32_t *) response, &resp_len); 650 651 if (status < 0) { 652 *mbox_status = -status; 653 return INTEL_SIP_SMC_STATUS_ERROR; 654 } 655 656 *mbox_status = 0; 657 *len_in_resp = resp_len; 658 659 flush_dcache_range(response, resp_len * MBOX_WORD_BYTE); 660 661 return INTEL_SIP_SMC_STATUS_OK; 662 } 663 664 static int intel_smc_get_usercode(uint32_t *user_code) 665 { 666 int status; 667 unsigned int resp_len = sizeof(user_code) / MBOX_WORD_BYTE; 668 669 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_GET_USERCODE, NULL, 670 0U, CMD_CASUAL, user_code, &resp_len); 671 672 if (status < 0) { 673 return INTEL_SIP_SMC_STATUS_ERROR; 674 } 675 676 return INTEL_SIP_SMC_STATUS_OK; 677 } 678 679 uint32_t intel_smc_service_completed(uint64_t addr, uint32_t size, 680 uint32_t mode, uint32_t *job_id, 681 uint32_t *ret_size, uint32_t *mbox_error) 682 { 683 int status = 0; 684 uint32_t resp_len = size / MBOX_WORD_BYTE; 685 686 if (resp_len > MBOX_DATA_MAX_LEN) { 687 return INTEL_SIP_SMC_STATUS_REJECTED; 688 } 689 690 if (!is_address_in_ddr_range(addr, size)) { 691 return INTEL_SIP_SMC_STATUS_REJECTED; 692 } 693 694 if (mode == SERVICE_COMPLETED_MODE_ASYNC) { 695 status = mailbox_read_response_async(job_id, 696 NULL, (uint32_t *) addr, &resp_len, 0); 697 } else { 698 status = mailbox_read_response(job_id, 699 (uint32_t *) addr, &resp_len); 700 701 if (status == MBOX_NO_RESPONSE) { 702 status = MBOX_BUSY; 703 } 704 } 705 706 if (status == MBOX_NO_RESPONSE) { 707 return INTEL_SIP_SMC_STATUS_NO_RESPONSE; 708 } 709 710 if (status == MBOX_BUSY) { 711 return INTEL_SIP_SMC_STATUS_BUSY; 712 } 713 714 *ret_size = resp_len * MBOX_WORD_BYTE; 715 flush_dcache_range(addr, *ret_size); 716 717 if (status == MBOX_RET_SDOS_DECRYPTION_ERROR_102 || 718 status == MBOX_RET_SDOS_DECRYPTION_ERROR_103) { 719 *mbox_error = -status; 720 } else if (status != MBOX_RET_OK) { 721 *mbox_error = -status; 722 return INTEL_SIP_SMC_STATUS_ERROR; 723 } 724 725 return INTEL_SIP_SMC_STATUS_OK; 726 } 727 728 /* Miscellaneous HPS services */ 729 uint32_t intel_hps_set_bridges(uint64_t enable, uint64_t mask) 730 { 731 int status = 0; 732 733 if ((enable & SOCFPGA_BRIDGE_ENABLE) != 0U) { 734 if ((enable & SOCFPGA_BRIDGE_HAS_MASK) != 0U) { 735 status = socfpga_bridges_enable((uint32_t)mask); 736 } else { 737 status = socfpga_bridges_enable(~0); 738 } 739 } else { 740 if ((enable & SOCFPGA_BRIDGE_HAS_MASK) != 0U) { 741 status = socfpga_bridges_disable((uint32_t)mask); 742 } else { 743 status = socfpga_bridges_disable(~0); 744 } 745 } 746 747 if (status < 0) { 748 return INTEL_SIP_SMC_STATUS_ERROR; 749 } 750 751 return INTEL_SIP_SMC_STATUS_OK; 752 } 753 754 /* SDM SEU Error services */ 755 static uint32_t intel_sdm_seu_err_read(uint32_t *respbuf, unsigned int respbuf_sz) 756 { 757 if (mailbox_seu_err_status(respbuf, respbuf_sz) < 0) { 758 return INTEL_SIP_SMC_SEU_ERR_READ_ERROR; 759 } 760 761 return INTEL_SIP_SMC_STATUS_OK; 762 } 763 764 /* SDM SAFE SEU Error inject services */ 765 static uint32_t intel_sdm_safe_inject_seu_err(uint32_t *command, uint32_t len) 766 { 767 if (mailbox_safe_inject_seu_err(command, len) < 0) { 768 return INTEL_SIP_SMC_SEU_ERR_READ_ERROR; 769 } 770 771 return INTEL_SIP_SMC_STATUS_OK; 772 } 773 774 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 775 /* SMMU HPS Remapper */ 776 void intel_smmu_hps_remapper_init(uint64_t *mem) 777 { 778 /* Read out Bit 1 value */ 779 uint32_t remap = (mmio_read_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_POR_1)) & 0x02); 780 781 if ((remap == 0x00) && (g_remapper_bypass == 0x00)) { 782 /* Update DRAM Base address for SDM SMMU */ 783 mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_ARADDR_REMAP), DRAM_BASE); 784 mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_AWADDR_REMAP), DRAM_BASE); 785 *mem = *mem - DRAM_BASE; 786 } else { 787 *mem = *mem - DRAM_BASE; 788 } 789 } 790 791 int intel_smmu_hps_remapper_config(uint32_t remapper_bypass) 792 { 793 /* Read out the JTAG-ID from boot scratch register */ 794 if (is_agilex5_A5F0() || is_agilex5_A5F4()) { 795 if (remapper_bypass == 0x01) { 796 g_remapper_bypass = remapper_bypass; 797 mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_ARADDR_REMAP), 0); 798 mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_AWADDR_REMAP), 0); 799 } 800 } 801 return INTEL_SIP_SMC_STATUS_OK; 802 } 803 804 static void intel_inject_io96b_ecc_err(const uint32_t *syndrome, const uint32_t command) 805 { 806 volatile uint64_t atf_ddr_buffer; 807 volatile uint64_t val; 808 809 mmio_write_32(IOSSM_CMD_PARAM, *syndrome); 810 mmio_write_32(IOSSM_CMD_TRIG_OP, command); 811 udelay(IOSSM_ECC_ERR_INJ_DELAY_USECS); 812 atf_ddr_buffer = 0xCAFEBABEFEEDFACE; /* Write data */ 813 memcpy_s((void *)&val, sizeof(val), 814 (void *)&atf_ddr_buffer, sizeof(atf_ddr_buffer)); 815 816 /* Clear response_ready BIT0 of status_register before sending next command. */ 817 mmio_clrbits_32(IOSSM_CMD_RESP_STATUS, IOSSM_CMD_STATUS_RESP_READY); 818 } 819 #endif 820 821 #if SIP_SVC_V3 822 uint8_t sip_smc_cmd_cb_ret2(void *resp_desc, void *cmd_desc, uint64_t *ret_args) 823 { 824 uint8_t ret_args_len = 0U; 825 sdm_response_t *resp = (sdm_response_t *)resp_desc; 826 sdm_command_t *cmd = (sdm_command_t *)cmd_desc; 827 828 (void)cmd; 829 /* Returns 3 SMC arguments for SMC_RET3 */ 830 ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK; 831 ret_args[ret_args_len++] = resp->err_code; 832 833 return ret_args_len; 834 } 835 836 uint8_t sip_smc_cmd_cb_ret3(void *resp_desc, void *cmd_desc, uint64_t *ret_args) 837 { 838 uint8_t ret_args_len = 0U; 839 sdm_response_t *resp = (sdm_response_t *)resp_desc; 840 sdm_command_t *cmd = (sdm_command_t *)cmd_desc; 841 842 (void)cmd; 843 /* Returns 3 SMC arguments for SMC_RET3 */ 844 ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK; 845 ret_args[ret_args_len++] = resp->err_code; 846 ret_args[ret_args_len++] = resp->resp_data[0]; 847 848 return ret_args_len; 849 } 850 851 uint8_t sip_smc_ret_nbytes_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args) 852 { 853 uint8_t ret_args_len = 0U; 854 sdm_response_t *resp = (sdm_response_t *)resp_desc; 855 sdm_command_t *cmd = (sdm_command_t *)cmd_desc; 856 857 (void)cmd; 858 INFO("MBOX: %s: mailbox_err 0%x, nbytes_ret %d\n", 859 __func__, resp->err_code, resp->rcvd_resp_len * MBOX_WORD_BYTE); 860 861 ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK; 862 ret_args[ret_args_len++] = resp->err_code; 863 ret_args[ret_args_len++] = resp->rcvd_resp_len * MBOX_WORD_BYTE; 864 865 return ret_args_len; 866 } 867 868 uint8_t sip_smc_get_chipid_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args) 869 { 870 uint8_t ret_args_len = 0U; 871 sdm_response_t *resp = (sdm_response_t *)resp_desc; 872 sdm_command_t *cmd = (sdm_command_t *)cmd_desc; 873 874 (void)cmd; 875 INFO("MBOX: %s: mailbox_err 0%x, data[0] 0x%x, data[1] 0x%x\n", 876 __func__, resp->err_code, resp->resp_data[0], resp->resp_data[1]); 877 878 ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK; 879 ret_args[ret_args_len++] = resp->err_code; 880 ret_args[ret_args_len++] = resp->resp_data[0]; 881 ret_args[ret_args_len++] = resp->resp_data[1]; 882 883 return ret_args_len; 884 } 885 886 static uintptr_t smc_ret(void *handle, uint64_t *ret_args, uint32_t ret_args_len) 887 { 888 889 switch (ret_args_len) { 890 case SMC_RET_ARGS_ONE: 891 VERBOSE("SVC V3: %s: x0 0x%lx\n", __func__, ret_args[0]); 892 SMC_RET1(handle, ret_args[0]); 893 break; 894 895 case SMC_RET_ARGS_TWO: 896 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx\n", __func__, ret_args[0], ret_args[1]); 897 SMC_RET2(handle, ret_args[0], ret_args[1]); 898 break; 899 900 case SMC_RET_ARGS_THREE: 901 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx, x2 0x%lx\n", 902 __func__, ret_args[0], ret_args[1], ret_args[2]); 903 SMC_RET3(handle, ret_args[0], ret_args[1], ret_args[2]); 904 break; 905 906 case SMC_RET_ARGS_FOUR: 907 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx, x2 0x%lx, x3 0x%lx\n", 908 __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3]); 909 SMC_RET4(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3]); 910 break; 911 912 case SMC_RET_ARGS_FIVE: 913 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx, x2 0x%lx, x3 0x%lx, x4 0x%lx\n", 914 __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4]); 915 SMC_RET5(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4]); 916 break; 917 918 case SMC_RET_ARGS_SIX: 919 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx x2 0x%lx x3 0x%lx, x4 0x%lx x5 0x%lx\n", 920 __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4], 921 ret_args[5]); 922 SMC_RET6(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4], 923 ret_args[5]); 924 break; 925 926 case SMC_RET_ARGS_SEVEN: 927 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx x2 0x%lx, x3 0x%lx, x4 0x%lx, x5 0x%lx\t" 928 "x6 0x%lx\n", 929 __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4], 930 ret_args[5], ret_args[6]); 931 SMC_RET7(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4], 932 ret_args[5], ret_args[6]); 933 break; 934 935 case SMC_RET_ARGS_EIGHT: 936 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx x2 0x%lx, x3 0x%lx, x4 0x%lx x5 0x%lx\t" 937 "x6 0x%lx, x7 0x%lx\n", 938 __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4], 939 ret_args[5], ret_args[6], ret_args[7]); 940 SMC_RET8(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4], 941 ret_args[5], ret_args[6], ret_args[7]); 942 break; 943 944 case SMC_RET_ARGS_NINE: 945 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx x2 0x%lx, x3 0x%lx, x4 0x%lx, x5 0x%lx\t" 946 "x6 0x%lx, x7 0x%lx, x8 0x%lx\n", 947 __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4], 948 ret_args[5], ret_args[6], ret_args[7], ret_args[8]); 949 SMC_RET18(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4], 950 ret_args[5], ret_args[6], ret_args[7], ret_args[8], 951 0, 0, 0, 0, 0, 0, 0, 0, 0); 952 break; 953 954 case SMC_RET_ARGS_TEN: 955 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx, x2 0x%lx, x3 0x%lx, x4 0x%lx x5 0x%lx\t" 956 "x6 0x%lx, x7 0x%lx x8 0x%lx, x9 0x%lx, x10 0x%lx\n", 957 __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], 958 ret_args[4], ret_args[5], ret_args[6], ret_args[7], ret_args[8], 959 ret_args[9], ret_args[10]); 960 SMC_RET18(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4], 961 ret_args[5], ret_args[6], ret_args[7], ret_args[8], ret_args[9], 962 0, 0, 0, 0, 0, 0, 0, 0); 963 break; 964 965 default: 966 VERBOSE("SVC V3: %s ret_args_len is wrong, please check %d\n ", 967 __func__, ret_args_len); 968 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR); 969 break; 970 } 971 } 972 973 /* 974 * This function is responsible for handling all SiP SVC V3 calls from the 975 * non-secure world. 976 */ 977 static uintptr_t sip_smc_handler_v3(uint32_t smc_fid, 978 u_register_t x1, 979 u_register_t x2, 980 u_register_t x3, 981 u_register_t x4, 982 void *cookie, 983 void *handle, 984 u_register_t flags) 985 { 986 int status = 0; 987 uint32_t mbox_error = 0U; 988 u_register_t x5, x6, x7, x8, x9, x10, x11; 989 990 /* Get all the SMC call arguments */ 991 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 992 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 993 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 994 x8 = SMC_GET_GP(handle, CTX_GPREG_X8); 995 x9 = SMC_GET_GP(handle, CTX_GPREG_X9); 996 x10 = SMC_GET_GP(handle, CTX_GPREG_X10); 997 x11 = SMC_GET_GP(handle, CTX_GPREG_X11); 998 999 INFO("MBOX: SVC_V3: x0 0x%x, x1 0x%lx, x2 0x%lx, x3 0x%lx, x4 0x%lx, x5 0x%lx\n", 1000 smc_fid, x1, x2, x3, x4, x5); 1001 INFO("MBOX: SVC_V3: x6 0x%lx, x7 0x%lx, x8 0x%lx, x9 0x%lx, x10 0x%lx x11 0x%lx\n", 1002 x6, x7, x8, x9, x10, x11); 1003 1004 switch (smc_fid) { 1005 case ALTERA_SIP_SMC_ASYNC_RESP_POLL: 1006 { 1007 uint64_t ret_args[16] = {0}; 1008 uint32_t ret_args_len = 0; 1009 1010 status = mailbox_response_poll_v3(GET_CLIENT_ID(x1), 1011 GET_JOB_ID(x1), 1012 ret_args, 1013 &ret_args_len); 1014 /* Always reserve [0] index for command status. */ 1015 ret_args[0] = status; 1016 1017 /* Return SMC call based on the number of return arguments */ 1018 return smc_ret(handle, ret_args, ret_args_len); 1019 } 1020 1021 case ALTERA_SIP_SMC_ASYNC_RESP_POLL_ON_INTR: 1022 { 1023 /* TBD: Here now we don't need these CID and JID?? */ 1024 uint8_t client_id = 0U; 1025 uint8_t job_id = 0U; 1026 uint64_t trans_id_bitmap[4] = {0U}; 1027 1028 status = mailbox_response_poll_on_intr_v3(&client_id, 1029 &job_id, 1030 trans_id_bitmap); 1031 1032 SMC_RET5(handle, status, trans_id_bitmap[0], trans_id_bitmap[1], 1033 trans_id_bitmap[2], trans_id_bitmap[3]); 1034 break; 1035 } 1036 1037 case ALTERA_SIP_SMC_ASYNC_GET_DEVICE_IDENTITY: 1038 { 1039 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1040 GET_JOB_ID(x1), 1041 MBOX_CMD_GET_DEVICEID, 1042 NULL, 1043 0U, 1044 MBOX_CMD_FLAG_CASUAL, 1045 sip_smc_ret_nbytes_cb, 1046 (uint32_t *)x2, 1047 2); 1048 1049 SMC_RET1(handle, status); 1050 } 1051 1052 case ALTERA_SIP_SMC_ASYNC_GET_IDCODE: 1053 { 1054 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1055 GET_JOB_ID(x1), 1056 MBOX_CMD_GET_IDCODE, 1057 NULL, 1058 0U, 1059 MBOX_CMD_FLAG_CASUAL, 1060 sip_smc_cmd_cb_ret3, 1061 NULL, 1062 0); 1063 1064 SMC_RET1(handle, status); 1065 } 1066 1067 case ALTERA_SIP_SMC_ASYNC_QSPI_OPEN: 1068 { 1069 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1070 GET_JOB_ID(x1), 1071 MBOX_CMD_QSPI_OPEN, 1072 NULL, 1073 0U, 1074 MBOX_CMD_FLAG_CASUAL, 1075 sip_smc_cmd_cb_ret2, 1076 NULL, 1077 0U); 1078 1079 SMC_RET1(handle, status); 1080 } 1081 1082 case ALTERA_SIP_SMC_ASYNC_QSPI_CLOSE: 1083 { 1084 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1085 GET_JOB_ID(x1), 1086 MBOX_CMD_QSPI_CLOSE, 1087 NULL, 1088 0U, 1089 MBOX_CMD_FLAG_CASUAL, 1090 sip_smc_cmd_cb_ret2, 1091 NULL, 1092 0U); 1093 1094 SMC_RET1(handle, status); 1095 } 1096 1097 case ALTERA_SIP_SMC_ASYNC_QSPI_SET_CS: 1098 { 1099 uint32_t cmd_data = 0U; 1100 uint32_t chip_sel = (uint32_t)x2; 1101 uint32_t comb_addr_mode = (uint32_t)x3; 1102 uint32_t ext_dec_mode = (uint32_t)x4; 1103 1104 cmd_data = (chip_sel << MBOX_QSPI_SET_CS_OFFSET) | 1105 (comb_addr_mode << MBOX_QSPI_SET_CS_CA_OFFSET) | 1106 (ext_dec_mode << MBOX_QSPI_SET_CS_MODE_OFFSET); 1107 1108 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1109 GET_JOB_ID(x1), 1110 MBOX_CMD_QSPI_SET_CS, 1111 &cmd_data, 1112 1U, 1113 MBOX_CMD_FLAG_CASUAL, 1114 sip_smc_cmd_cb_ret2, 1115 NULL, 1116 0U); 1117 1118 SMC_RET1(handle, status); 1119 } 1120 1121 case ALTERA_SIP_SMC_ASYNC_QSPI_ERASE: 1122 { 1123 uint32_t qspi_addr = (uint32_t)x2; 1124 uint32_t qspi_nwords = (uint32_t)x3; 1125 1126 /* QSPI address offset to start erase, must be 4K aligned */ 1127 if (MBOX_IS_4K_ALIGNED(qspi_addr)) { 1128 ERROR("MBOX: 0x%x: QSPI address not 4K aligned\n", 1129 smc_fid); 1130 status = INTEL_SIP_SMC_STATUS_REJECTED; 1131 SMC_RET1(handle, status); 1132 } 1133 1134 /* Number of words to erase, multiples of 0x400 or 4K */ 1135 if (qspi_nwords % MBOX_QSPI_ERASE_SIZE_GRAN) { 1136 ERROR("MBOX: 0x%x: Given words not in multiples of 4K\n", 1137 smc_fid); 1138 status = INTEL_SIP_SMC_STATUS_REJECTED; 1139 SMC_RET1(handle, status); 1140 } 1141 1142 uint32_t cmd_data[2] = {qspi_addr, qspi_nwords}; 1143 1144 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1145 GET_JOB_ID(x1), 1146 MBOX_CMD_QSPI_ERASE, 1147 cmd_data, 1148 sizeof(cmd_data) / MBOX_WORD_BYTE, 1149 MBOX_CMD_FLAG_CASUAL, 1150 sip_smc_cmd_cb_ret2, 1151 NULL, 1152 0U); 1153 1154 SMC_RET1(handle, status); 1155 } 1156 1157 case ALTERA_SIP_SMC_ASYNC_QSPI_WRITE: 1158 { 1159 uint32_t *qspi_payload = (uint32_t *)x2; 1160 uint32_t qspi_total_nwords = (((uint32_t)x3) / MBOX_WORD_BYTE); 1161 uint32_t qspi_addr = qspi_payload[0]; 1162 uint32_t qspi_nwords = qspi_payload[1]; 1163 1164 if (!MBOX_IS_WORD_ALIGNED(qspi_addr)) { 1165 ERROR("MBOX: 0x%x: Given address is not WORD aligned\n", 1166 smc_fid); 1167 status = INTEL_SIP_SMC_STATUS_REJECTED; 1168 SMC_RET1(handle, status); 1169 } 1170 1171 if (qspi_nwords > MBOX_QSPI_RW_MAX_WORDS) { 1172 ERROR("MBOX: 0x%x: Number of words exceeds max limit\n", 1173 smc_fid); 1174 status = INTEL_SIP_SMC_STATUS_REJECTED; 1175 SMC_RET1(handle, status); 1176 } 1177 1178 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1179 GET_JOB_ID(x1), 1180 MBOX_CMD_QSPI_WRITE, 1181 qspi_payload, 1182 qspi_total_nwords, 1183 MBOX_CMD_FLAG_CASUAL, 1184 sip_smc_cmd_cb_ret2, 1185 NULL, 1186 0U); 1187 1188 SMC_RET1(handle, status); 1189 } 1190 1191 case ALTERA_SIP_SMC_ASYNC_QSPI_READ: 1192 { 1193 uint32_t qspi_addr = (uint32_t)x2; 1194 uint32_t qspi_nwords = (((uint32_t)x4) / MBOX_WORD_BYTE); 1195 1196 if (qspi_nwords > MBOX_QSPI_RW_MAX_WORDS) { 1197 ERROR("MBOX: 0x%x: Number of words exceeds max limit\n", 1198 smc_fid); 1199 status = INTEL_SIP_SMC_STATUS_REJECTED; 1200 SMC_RET1(handle, status); 1201 } 1202 1203 uint32_t cmd_data[2] = {qspi_addr, qspi_nwords}; 1204 1205 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1206 GET_JOB_ID(x1), 1207 MBOX_CMD_QSPI_READ, 1208 cmd_data, 1209 sizeof(cmd_data) / MBOX_WORD_BYTE, 1210 MBOX_CMD_FLAG_CASUAL, 1211 sip_smc_ret_nbytes_cb, 1212 (uint32_t *)x3, 1213 2); 1214 1215 SMC_RET1(handle, status); 1216 } 1217 1218 case ALTERA_SIP_SMC_ASYNC_QSPI_GET_DEV_INFO: 1219 { 1220 uint32_t *dst_addr = (uint32_t *)x2; 1221 1222 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1223 GET_JOB_ID(x1), 1224 MBOX_CMD_QSPI_GET_DEV_INFO, 1225 NULL, 1226 0U, 1227 MBOX_CMD_FLAG_CASUAL, 1228 sip_smc_ret_nbytes_cb, 1229 (uint32_t *)dst_addr, 1230 2); 1231 1232 SMC_RET1(handle, status); 1233 } 1234 1235 case ALTERA_SIP_SMC_ASYNC_HWMON_READVOLT: 1236 case ALTERA_SIP_SMC_ASYNC_HWMON_READTEMP: 1237 { 1238 uint32_t channel = (uint32_t)x2; 1239 uint32_t mbox_cmd = ((smc_fid == ALTERA_SIP_SMC_ASYNC_HWMON_READVOLT) ? 1240 MBOX_HWMON_READVOLT : MBOX_HWMON_READTEMP); 1241 1242 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1243 GET_JOB_ID(x1), 1244 mbox_cmd, 1245 &channel, 1246 1U, 1247 MBOX_CMD_FLAG_CASUAL, 1248 sip_smc_cmd_cb_ret3, 1249 NULL, 1250 0); 1251 1252 SMC_RET1(handle, status); 1253 } 1254 1255 case ALTERA_SIP_SMC_ASYNC_FCS_RANDOM_NUMBER_EXT: 1256 { 1257 uint32_t session_id = (uint32_t)x2; 1258 uint32_t context_id = (uint32_t)x3; 1259 uint64_t ret_random_addr = (uint64_t)x4; 1260 uint32_t random_len = (uint32_t)SMC_GET_GP(handle, CTX_GPREG_X5); 1261 uint32_t crypto_header = 0U; 1262 1263 if ((random_len > (FCS_RANDOM_EXT_MAX_WORD_SIZE * MBOX_WORD_BYTE)) || 1264 (random_len == 0U) || 1265 (!is_size_4_bytes_aligned(random_len))) { 1266 ERROR("MBOX: 0x%x is rejected\n", smc_fid); 1267 status = INTEL_SIP_SMC_STATUS_REJECTED; 1268 SMC_RET1(handle, status); 1269 } 1270 1271 crypto_header = ((FCS_CS_FIELD_FLAG_INIT | FCS_CS_FIELD_FLAG_FINALIZE) << 1272 FCS_CS_FIELD_FLAG_OFFSET); 1273 fcs_rng_payload payload = {session_id, context_id, 1274 crypto_header, random_len}; 1275 1276 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1277 GET_JOB_ID(x1), 1278 MBOX_FCS_RANDOM_GEN, 1279 (uint32_t *)&payload, 1280 sizeof(payload) / MBOX_WORD_BYTE, 1281 MBOX_CMD_FLAG_CASUAL, 1282 sip_smc_ret_nbytes_cb, 1283 (uint32_t *)ret_random_addr, 1284 2); 1285 SMC_RET1(handle, status); 1286 } 1287 1288 case ALTERA_SIP_SMC_ASYNC_FCS_GET_PROVISION_DATA: 1289 { 1290 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1291 GET_JOB_ID(x1), 1292 MBOX_FCS_GET_PROVISION, 1293 NULL, 1294 0U, 1295 MBOX_CMD_FLAG_CASUAL, 1296 sip_smc_ret_nbytes_cb, 1297 (uint32_t *)x2, 1298 2); 1299 SMC_RET1(handle, status); 1300 } 1301 1302 case ALTERA_SIP_SMC_ASYNC_FCS_CNTR_SET_PREAUTH: 1303 { 1304 status = intel_fcs_cntr_set_preauth(smc_fid, x1, x2, x3, 1305 x4, &mbox_error); 1306 SMC_RET1(handle, status); 1307 } 1308 1309 case ALTERA_SIP_SMC_ASYNC_FCS_CHIP_ID: 1310 { 1311 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1312 GET_JOB_ID(x1), 1313 MBOX_CMD_GET_CHIPID, 1314 NULL, 1315 0U, 1316 MBOX_CMD_FLAG_CASUAL, 1317 sip_smc_get_chipid_cb, 1318 NULL, 1319 0); 1320 SMC_RET1(handle, status); 1321 } 1322 1323 case ALTERA_SIP_SMC_ASYNC_FCS_GET_ATTESTATION_CERT: 1324 { 1325 status = intel_fcs_get_attestation_cert(smc_fid, x1, x2, x3, 1326 (uint32_t *) &x4, &mbox_error); 1327 SMC_RET1(handle, status); 1328 } 1329 1330 case ALTERA_SIP_SMC_ASYNC_FCS_CREATE_CERT_ON_RELOAD: 1331 { 1332 status = intel_fcs_create_cert_on_reload(smc_fid, x1, 1333 x2, &mbox_error); 1334 SMC_RET1(handle, status); 1335 } 1336 1337 case ALTERA_SIP_SMC_ASYNC_FCS_CRYPTION_EXT: 1338 { 1339 if (x4 == FCS_MODE_ENCRYPT) { 1340 status = intel_fcs_encryption_ext(smc_fid, x1, x2, x3, 1341 x5, x6, x7, (uint32_t *) &x8, 1342 &mbox_error, x10, x11); 1343 } else if (x4 == FCS_MODE_DECRYPT) { 1344 status = intel_fcs_decryption_ext(smc_fid, x1, x2, x3, 1345 x5, x6, x7, (uint32_t *) &x8, 1346 &mbox_error, x9, x10, x11); 1347 } else { 1348 ERROR("MBOX: 0x%x: Wrong crypto mode\n", smc_fid); 1349 status = INTEL_SIP_SMC_STATUS_REJECTED; 1350 } 1351 SMC_RET1(handle, status); 1352 } 1353 1354 case ALTERA_SIP_SMC_ASYNC_FCS_SEND_CERTIFICATE: 1355 { 1356 status = intel_fcs_send_cert(smc_fid, x1, x2, x3, &mbox_error); 1357 SMC_RET1(handle, status); 1358 } 1359 1360 case ALTERA_SIP_SMC_ASYNC_FCS_OPEN_CS_SESSION: 1361 { 1362 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1363 GET_JOB_ID(x1), 1364 MBOX_FCS_OPEN_CS_SESSION, 1365 NULL, 1366 0U, 1367 MBOX_CMD_FLAG_CASUAL, 1368 sip_smc_cmd_cb_ret3, 1369 NULL, 1370 0); 1371 SMC_RET1(handle, status); 1372 } 1373 1374 case ALTERA_SIP_SMC_ASYNC_FCS_CLOSE_CS_SESSION: 1375 { 1376 uint32_t session_id = (uint32_t)x2; 1377 1378 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1379 GET_JOB_ID(x1), 1380 MBOX_FCS_CLOSE_CS_SESSION, 1381 &session_id, 1382 1U, 1383 MBOX_CMD_FLAG_CASUAL, 1384 sip_smc_cmd_cb_ret2, 1385 NULL, 1386 0); 1387 SMC_RET1(handle, status); 1388 } 1389 1390 case ALTERA_SIP_SMC_ASYNC_FCS_IMPORT_CS_KEY: 1391 { 1392 uint64_t key_addr = x2; 1393 uint32_t key_len_words = (uint32_t)x3 / MBOX_WORD_BYTE; 1394 1395 if ((key_len_words > FCS_CS_KEY_OBJ_MAX_WORD_SIZE) || 1396 (!is_address_in_ddr_range(key_addr, key_len_words * 4))) { 1397 ERROR("MBOX: 0x%x: Addr not in DDR range or key len exceeds\n", 1398 smc_fid); 1399 status = INTEL_SIP_SMC_STATUS_REJECTED; 1400 SMC_RET1(handle, status); 1401 } 1402 1403 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1404 GET_JOB_ID(x1), 1405 MBOX_FCS_IMPORT_CS_KEY, 1406 (uint32_t *)key_addr, 1407 key_len_words, 1408 MBOX_CMD_FLAG_CASUAL, 1409 sip_smc_cmd_cb_ret3, 1410 NULL, 1411 0); 1412 SMC_RET1(handle, status); 1413 } 1414 1415 case ALTERA_SIP_SMC_ASYNC_FCS_CREATE_CS_KEY: 1416 { 1417 uint64_t key_addr = x2; 1418 uint32_t key_len_words = (uint32_t)x3 / MBOX_WORD_BYTE; 1419 1420 if (!is_address_in_ddr_range(key_addr, key_len_words * 4)) { 1421 ERROR("MBOX: 0x%x: Addr not in DDR range\n", smc_fid); 1422 status = INTEL_SIP_SMC_STATUS_REJECTED; 1423 SMC_RET1(handle, status); 1424 } 1425 1426 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1427 GET_JOB_ID(x1), 1428 MBOX_FCS_CREATE_CS_KEY, 1429 (uint32_t *)key_addr, 1430 key_len_words, 1431 MBOX_CMD_FLAG_CASUAL, 1432 sip_smc_cmd_cb_ret3, 1433 NULL, 1434 0); 1435 SMC_RET1(handle, status); 1436 } 1437 1438 case ALTERA_SIP_SMC_ASYNC_FCS_EXPORT_CS_KEY: 1439 { 1440 uint32_t session_id = (uint32_t)x2; 1441 uint32_t key_uid = (uint32_t)x3; 1442 uint64_t ret_key_addr = (uint64_t)x4; 1443 uint32_t key_len = (uint32_t)SMC_GET_GP(handle, CTX_GPREG_X5); 1444 1445 if (!is_address_in_ddr_range(ret_key_addr, key_len)) { 1446 ERROR("MBOX: 0x%x: Addr not in DDR range\n", smc_fid); 1447 status = INTEL_SIP_SMC_STATUS_REJECTED; 1448 SMC_RET1(handle, status); 1449 } 1450 1451 fcs_cs_key_payload payload = {session_id, RESERVED_AS_ZERO, 1452 RESERVED_AS_ZERO, key_uid}; 1453 1454 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1455 GET_JOB_ID(x1), 1456 MBOX_FCS_EXPORT_CS_KEY, 1457 (uint32_t *)&payload, 1458 sizeof(payload) / MBOX_WORD_BYTE, 1459 MBOX_CMD_FLAG_CASUAL, 1460 sip_smc_ret_nbytes_cb, 1461 (uint32_t *)ret_key_addr, 1462 2); 1463 SMC_RET1(handle, status); 1464 } 1465 1466 case ALTERA_SIP_SMC_ASYNC_FCS_REMOVE_CS_KEY: 1467 { 1468 uint32_t session_id = (uint32_t)x2; 1469 uint32_t key_uid = (uint32_t)x3; 1470 1471 fcs_cs_key_payload payload = {session_id, RESERVED_AS_ZERO, 1472 RESERVED_AS_ZERO, key_uid}; 1473 1474 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1475 GET_JOB_ID(x1), 1476 MBOX_FCS_REMOVE_CS_KEY, 1477 (uint32_t *)&payload, 1478 sizeof(payload) / MBOX_WORD_BYTE, 1479 MBOX_CMD_FLAG_CASUAL, 1480 sip_smc_cmd_cb_ret3, 1481 NULL, 1482 0); 1483 SMC_RET1(handle, status); 1484 } 1485 1486 case ALTERA_SIP_SMC_ASYNC_FCS_GET_CS_KEY_INFO: 1487 { 1488 uint32_t session_id = (uint32_t)x2; 1489 uint32_t key_uid = (uint32_t)x3; 1490 uint64_t ret_key_addr = (uint64_t)x4; 1491 uint32_t key_len = (uint32_t)SMC_GET_GP(handle, CTX_GPREG_X5); 1492 1493 if (!is_address_in_ddr_range(ret_key_addr, key_len)) { 1494 ERROR("MBOX: 0x%x: Addr not in DDR range\n", smc_fid); 1495 status = INTEL_SIP_SMC_STATUS_REJECTED; 1496 SMC_RET1(handle, status); 1497 } 1498 1499 fcs_cs_key_payload payload = {session_id, RESERVED_AS_ZERO, 1500 RESERVED_AS_ZERO, key_uid}; 1501 1502 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1503 GET_JOB_ID(x1), 1504 MBOX_FCS_GET_CS_KEY_INFO, 1505 (uint32_t *)&payload, 1506 sizeof(payload) / MBOX_WORD_BYTE, 1507 MBOX_CMD_FLAG_CASUAL, 1508 sip_smc_ret_nbytes_cb, 1509 (uint32_t *)ret_key_addr, 1510 2); 1511 SMC_RET1(handle, status); 1512 } 1513 1514 case ALTERA_SIP_SMC_ASYNC_FCS_AES_CRYPT_INIT: 1515 { 1516 status = intel_fcs_aes_crypt_init(x2, x3, x4, x5, 1517 x6, &mbox_error); 1518 SMC_RET1(handle, status); 1519 } 1520 1521 case ALTERA_SIP_SMC_ASYNC_FCS_AES_CRYPT_UPDATE: 1522 case ALTERA_SIP_SMC_ASYNC_FCS_AES_CRYPT_FINALIZE: 1523 { 1524 uint32_t job_id = 0U; 1525 bool is_final = (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_AES_CRYPT_FINALIZE) ? 1526 true : false; 1527 1528 status = intel_fcs_aes_crypt_update_finalize(smc_fid, x1, x2, 1529 x3, x4, x5, x6, x7, x8, is_final, 1530 &job_id, x9, x10); 1531 SMC_RET1(handle, status); 1532 } 1533 1534 case ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_INIT: 1535 { 1536 status = intel_fcs_get_digest_init(x2, x3, x4, x5, x6, 1537 &mbox_error); 1538 SMC_RET1(handle, status); 1539 } 1540 1541 case ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_UPDATE: 1542 case ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_FINALIZE: 1543 { 1544 bool is_final = (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_FINALIZE) ? 1545 true : false; 1546 1547 status = intel_fcs_get_digest_update_finalize(smc_fid, x1, x2, 1548 x3, x4, x5, x6, (uint32_t *) &x7, 1549 is_final, &mbox_error, x8); 1550 1551 SMC_RET1(handle, status); 1552 } 1553 1554 case ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_INIT: 1555 { 1556 status = intel_fcs_mac_verify_init(x2, x3, x4, x5, x6, 1557 &mbox_error); 1558 SMC_RET1(handle, status); 1559 } 1560 1561 case ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_UPDATE: 1562 case ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_FINALIZE: 1563 { 1564 bool is_final = (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_FINALIZE) ? 1565 true : false; 1566 1567 status = intel_fcs_mac_verify_update_finalize(smc_fid, x1, x2, 1568 x3, x4, x5, x6, (uint32_t *) &x7, x8, 1569 is_final, &mbox_error, x9); 1570 SMC_RET1(handle, status); 1571 } 1572 1573 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIGN_INIT: 1574 { 1575 status = intel_fcs_ecdsa_hash_sign_init(x2, x3, x4, x5, x6, 1576 &mbox_error); 1577 SMC_RET1(handle, status); 1578 } 1579 1580 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIGN_FINALIZE: 1581 { 1582 status = intel_fcs_ecdsa_hash_sign_finalize(smc_fid, x1, x2, x3, 1583 x4, x5, x6, (uint32_t *) &x7, 1584 &mbox_error); 1585 SMC_RET1(handle, status); 1586 } 1587 1588 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_INIT: 1589 { 1590 status = intel_fcs_ecdsa_sha2_data_sign_init(x2, x3, x4, x5, x6, 1591 &mbox_error); 1592 SMC_RET1(handle, status); 1593 } 1594 1595 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_UPDATE: 1596 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE: 1597 { 1598 bool is_final = (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE) 1599 ? true : false; 1600 1601 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(smc_fid, 1602 x1, x2, x3, x4, x5, x6, (uint32_t *) &x7, 1603 is_final, &mbox_error, x8); 1604 SMC_RET1(handle, status); 1605 } 1606 1607 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIG_VERIFY_INIT: 1608 { 1609 status = intel_fcs_ecdsa_hash_sig_verify_init(x2, x3, x4, x5, 1610 x6, &mbox_error); 1611 SMC_RET1(handle, status); 1612 } 1613 1614 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIG_VERIFY_FINALIZE: 1615 { 1616 status = intel_fcs_ecdsa_hash_sig_verify_finalize(smc_fid, x1, 1617 x2, x3, x4, x5, x6, (uint32_t *) &x7, 1618 &mbox_error); 1619 SMC_RET1(handle, status); 1620 } 1621 1622 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_INIT: 1623 { 1624 status = intel_fcs_ecdsa_sha2_data_sig_verify_init(x2, x3, x4, 1625 x5, x6, &mbox_error); 1626 SMC_RET1(handle, status); 1627 } 1628 1629 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_UPDATE: 1630 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE: 1631 { 1632 bool is_final = (smc_fid == 1633 ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE) ? 1634 true : false; 1635 1636 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize( 1637 smc_fid, x1, x2, x3, x4, x5, x6, 1638 (uint32_t *) &x7, x8, is_final, 1639 &mbox_error, x9); 1640 SMC_RET1(handle, status); 1641 } 1642 1643 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_GET_PUBKEY_INIT: 1644 { 1645 status = intel_fcs_ecdsa_get_pubkey_init(x2, x3, x4, x5, x6, 1646 &mbox_error); 1647 SMC_RET1(handle, status); 1648 } 1649 1650 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_GET_PUBKEY_FINALIZE: 1651 { 1652 status = intel_fcs_ecdsa_get_pubkey_finalize(smc_fid, x1, x2, x3, 1653 x4, (uint32_t *) &x5, &mbox_error); 1654 SMC_RET1(handle, status); 1655 } 1656 1657 case ALTERA_SIP_SMC_ASYNC_FCS_ECDH_REQUEST_INIT: 1658 { 1659 status = intel_fcs_ecdh_request_init(x2, x3, x4, x5, x6, 1660 &mbox_error); 1661 SMC_RET1(handle, status); 1662 } 1663 1664 case ALTERA_SIP_SMC_ASYNC_FCS_ECDH_REQUEST_FINALIZE: 1665 { 1666 uint32_t dest_size = (uint32_t)x7; 1667 1668 NOTICE("MBOX: %s, %d: x7 0x%x, dest_size 0x%x\n", 1669 __func__, __LINE__, (uint32_t)x7, dest_size); 1670 1671 status = intel_fcs_ecdh_request_finalize(smc_fid, x1, x2, x3, 1672 x4, x5, x6, (uint32_t *) &dest_size, 1673 &mbox_error); 1674 SMC_RET1(handle, status); 1675 } 1676 1677 case ALTERA_SIP_SMC_ASYNC_MCTP_MSG: 1678 { 1679 uint32_t *src_addr = (uint32_t *)x2; 1680 uint32_t src_size = (uint32_t)x3; 1681 uint32_t *dst_addr = (uint32_t *)x4; 1682 1683 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1684 GET_JOB_ID(x1), 1685 MBOX_CMD_MCTP_MSG, 1686 src_addr, 1687 src_size / MBOX_WORD_BYTE, 1688 MBOX_CMD_FLAG_CASUAL, 1689 sip_smc_ret_nbytes_cb, 1690 dst_addr, 1691 2); 1692 1693 SMC_RET1(handle, status); 1694 } 1695 1696 case ALTERA_SIP_SMC_ASYNC_FCS_HKDF_REQUEST: 1697 { 1698 status = intel_fcs_hkdf_request(smc_fid, x1, x2, x3, x4, x5, x6, 1699 x7); 1700 SMC_RET1(handle, status); 1701 } 1702 1703 default: 1704 return socfpga_sip_handler(smc_fid, x1, x2, x3, x4, 1705 cookie, handle, flags); 1706 } /* switch (smc_fid) */ 1707 } 1708 #endif 1709 1710 /* 1711 * This function is responsible for handling all SiP calls from the NS world 1712 */ 1713 1714 uintptr_t sip_smc_handler_v1(uint32_t smc_fid, 1715 u_register_t x1, 1716 u_register_t x2, 1717 u_register_t x3, 1718 u_register_t x4, 1719 void *cookie, 1720 void *handle, 1721 u_register_t flags) 1722 { 1723 uint32_t retval = 0, completed_addr[3]; 1724 uint32_t retval2 = 0; 1725 uint32_t mbox_error = 0; 1726 uint32_t err_states = 0; 1727 uint64_t retval64, rsu_respbuf[9]; 1728 uint32_t seu_respbuf[3]; 1729 int status = INTEL_SIP_SMC_STATUS_OK; 1730 int mbox_status; 1731 unsigned int len_in_resp; 1732 u_register_t x5, x6, x7; 1733 1734 switch (smc_fid) { 1735 case SIP_SVC_UID: 1736 /* Return UID to the caller */ 1737 SMC_UUID_RET(handle, intl_svc_uid); 1738 1739 case INTEL_SIP_SMC_FPGA_CONFIG_ISDONE: 1740 status = intel_mailbox_fpga_config_isdone(&err_states); 1741 SMC_RET4(handle, status, err_states, 0, 0); 1742 1743 case INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM: 1744 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 1745 INTEL_SIP_SMC_FPGA_CONFIG_ADDR, 1746 INTEL_SIP_SMC_FPGA_CONFIG_SIZE - 1747 INTEL_SIP_SMC_FPGA_CONFIG_ADDR); 1748 1749 case INTEL_SIP_SMC_FPGA_CONFIG_START: 1750 status = intel_fpga_config_start(x1); 1751 SMC_RET4(handle, status, 0, 0, 0); 1752 1753 case INTEL_SIP_SMC_FPGA_CONFIG_WRITE: 1754 status = intel_fpga_config_write(x1, x2); 1755 SMC_RET4(handle, status, 0, 0, 0); 1756 1757 case INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE: 1758 status = intel_fpga_config_completed_write(completed_addr, 1759 &retval, &rcv_id); 1760 switch (retval) { 1761 case 1: 1762 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 1763 completed_addr[0], 0, 0); 1764 1765 case 2: 1766 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 1767 completed_addr[0], 1768 completed_addr[1], 0); 1769 1770 case 3: 1771 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 1772 completed_addr[0], 1773 completed_addr[1], 1774 completed_addr[2]); 1775 1776 case 0: 1777 SMC_RET4(handle, status, 0, 0, 0); 1778 1779 default: 1780 mailbox_clear_response(); 1781 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR); 1782 } 1783 1784 case INTEL_SIP_SMC_REG_READ: 1785 status = intel_secure_reg_read(x1, &retval); 1786 SMC_RET3(handle, status, retval, x1); 1787 1788 case INTEL_SIP_SMC_REG_WRITE: 1789 status = intel_secure_reg_write(x1, (uint32_t)x2, &retval); 1790 SMC_RET3(handle, status, retval, x1); 1791 1792 case INTEL_SIP_SMC_REG_UPDATE: 1793 status = intel_secure_reg_update(x1, (uint32_t)x2, 1794 (uint32_t)x3, &retval); 1795 SMC_RET3(handle, status, retval, x1); 1796 1797 case INTEL_SIP_SMC_RSU_STATUS: 1798 status = intel_rsu_status(rsu_respbuf, 1799 ARRAY_SIZE(rsu_respbuf)); 1800 if (status) { 1801 SMC_RET1(handle, status); 1802 } else { 1803 SMC_RET4(handle, rsu_respbuf[0], rsu_respbuf[1], 1804 rsu_respbuf[2], rsu_respbuf[3]); 1805 } 1806 1807 case INTEL_SIP_SMC_RSU_UPDATE: 1808 status = intel_rsu_update(x1); 1809 SMC_RET1(handle, status); 1810 1811 case INTEL_SIP_SMC_RSU_NOTIFY: 1812 status = intel_rsu_notify(x1); 1813 SMC_RET1(handle, status); 1814 1815 case INTEL_SIP_SMC_RSU_RETRY_COUNTER: 1816 status = intel_rsu_retry_counter((uint32_t *)rsu_respbuf, 1817 ARRAY_SIZE(rsu_respbuf), &retval); 1818 if (status) { 1819 SMC_RET1(handle, status); 1820 } else { 1821 SMC_RET2(handle, status, retval); 1822 } 1823 1824 case INTEL_SIP_SMC_RSU_DCMF_VERSION: 1825 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 1826 ((uint64_t)rsu_dcmf_ver[1] << 32) | rsu_dcmf_ver[0], 1827 ((uint64_t)rsu_dcmf_ver[3] << 32) | rsu_dcmf_ver[2]); 1828 1829 case INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION: 1830 status = intel_rsu_copy_dcmf_version(x1, x2); 1831 SMC_RET1(handle, status); 1832 1833 case INTEL_SIP_SMC_RSU_GET_DEVICE_INFO: 1834 status = intel_rsu_get_device_info((uint32_t *)rsu_respbuf, 1835 ARRAY_SIZE(rsu_respbuf)); 1836 if (status) { 1837 SMC_RET1(handle, status); 1838 } else { 1839 SMC_RET5(handle, status, rsu_respbuf[0], rsu_respbuf[1], 1840 rsu_respbuf[2], rsu_respbuf[3]); 1841 } 1842 1843 case INTEL_SIP_SMC_RSU_DCMF_STATUS: 1844 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, 1845 ((uint64_t)rsu_dcmf_stat[3] << 48) | 1846 ((uint64_t)rsu_dcmf_stat[2] << 32) | 1847 ((uint64_t)rsu_dcmf_stat[1] << 16) | 1848 rsu_dcmf_stat[0]); 1849 1850 case INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS: 1851 status = intel_rsu_copy_dcmf_status(x1); 1852 SMC_RET1(handle, status); 1853 1854 case INTEL_SIP_SMC_RSU_MAX_RETRY: 1855 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, rsu_max_retry); 1856 1857 case INTEL_SIP_SMC_RSU_COPY_MAX_RETRY: 1858 rsu_max_retry = x1; 1859 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_OK); 1860 1861 case INTEL_SIP_SMC_ECC_DBE: 1862 status = intel_ecc_dbe_notification(x1); 1863 SMC_RET1(handle, status); 1864 1865 case INTEL_SIP_SMC_SERVICE_COMPLETED: 1866 status = intel_smc_service_completed(x1, x2, x3, &rcv_id, 1867 &len_in_resp, &mbox_error); 1868 SMC_RET4(handle, status, mbox_error, x1, len_in_resp); 1869 1870 case INTEL_SIP_SMC_FIRMWARE_VERSION: 1871 status = intel_smc_fw_version(&retval); 1872 SMC_RET2(handle, status, retval); 1873 1874 case INTEL_SIP_SMC_MBOX_SEND_CMD: 1875 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1876 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1877 status = intel_mbox_send_cmd(x1, (uint32_t *)x2, x3, x4, x5, x6, 1878 &mbox_status, &len_in_resp); 1879 SMC_RET3(handle, status, mbox_status, len_in_resp); 1880 1881 case INTEL_SIP_SMC_GET_USERCODE: 1882 status = intel_smc_get_usercode(&retval); 1883 SMC_RET2(handle, status, retval); 1884 1885 case INTEL_SIP_SMC_FCS_CRYPTION: 1886 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1887 1888 if (x1 == FCS_MODE_DECRYPT) { 1889 status = intel_fcs_decryption(x2, x3, x4, x5, &send_id); 1890 } else if (x1 == FCS_MODE_ENCRYPT) { 1891 status = intel_fcs_encryption(x2, x3, x4, x5, &send_id); 1892 } else { 1893 status = INTEL_SIP_SMC_STATUS_REJECTED; 1894 } 1895 1896 SMC_RET3(handle, status, x4, x5); 1897 1898 case INTEL_SIP_SMC_FCS_CRYPTION_EXT: 1899 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1900 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1901 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1902 1903 if (x3 == FCS_MODE_DECRYPT) { 1904 status = intel_fcs_decryption_ext(smc_fid, 0, x1, x2, x4, x5, x6, 1905 (uint32_t *) &x7, &mbox_error, 0, 0, 0); 1906 } else if (x3 == FCS_MODE_ENCRYPT) { 1907 status = intel_fcs_encryption_ext(smc_fid, 0, x1, x2, x4, x5, x6, 1908 (uint32_t *) &x7, &mbox_error, 0, 0); 1909 } else { 1910 status = INTEL_SIP_SMC_STATUS_REJECTED; 1911 } 1912 1913 SMC_RET4(handle, status, mbox_error, x6, x7); 1914 1915 case INTEL_SIP_SMC_FCS_RANDOM_NUMBER: 1916 status = intel_fcs_random_number_gen(x1, &retval64, 1917 &mbox_error); 1918 SMC_RET4(handle, status, mbox_error, x1, retval64); 1919 1920 case INTEL_SIP_SMC_FCS_RANDOM_NUMBER_EXT: 1921 status = intel_fcs_random_number_gen_ext(x1, x2, x3, 1922 &send_id); 1923 SMC_RET1(handle, status); 1924 1925 case INTEL_SIP_SMC_FCS_SEND_CERTIFICATE: 1926 status = intel_fcs_send_cert(smc_fid, 0, x1, x2, &send_id); 1927 SMC_RET1(handle, status); 1928 1929 case INTEL_SIP_SMC_FCS_GET_PROVISION_DATA: 1930 status = intel_fcs_get_provision_data(&send_id); 1931 SMC_RET1(handle, status); 1932 1933 case INTEL_SIP_SMC_FCS_CNTR_SET_PREAUTH: 1934 status = intel_fcs_cntr_set_preauth(smc_fid, 0, x1, x2, x3, 1935 &mbox_error); 1936 SMC_RET2(handle, status, mbox_error); 1937 1938 case INTEL_SIP_SMC_HPS_SET_BRIDGES: 1939 status = intel_hps_set_bridges(x1, x2); 1940 SMC_RET1(handle, status); 1941 1942 case INTEL_SIP_SMC_HWMON_READTEMP: 1943 status = intel_hwmon_readtemp(x1, &retval); 1944 SMC_RET2(handle, status, retval); 1945 1946 case INTEL_SIP_SMC_HWMON_READVOLT: 1947 status = intel_hwmon_readvolt(x1, &retval); 1948 SMC_RET2(handle, status, retval); 1949 1950 case INTEL_SIP_SMC_FCS_PSGSIGMA_TEARDOWN: 1951 status = intel_fcs_sigma_teardown(x1, &mbox_error); 1952 SMC_RET2(handle, status, mbox_error); 1953 1954 case INTEL_SIP_SMC_FCS_CHIP_ID: 1955 status = intel_fcs_chip_id(&retval, &retval2, &mbox_error); 1956 SMC_RET4(handle, status, mbox_error, retval, retval2); 1957 1958 case INTEL_SIP_SMC_FCS_ATTESTATION_SUBKEY: 1959 status = intel_fcs_attestation_subkey(x1, x2, x3, 1960 (uint32_t *) &x4, &mbox_error); 1961 SMC_RET4(handle, status, mbox_error, x3, x4); 1962 1963 case INTEL_SIP_SMC_FCS_ATTESTATION_MEASUREMENTS: 1964 status = intel_fcs_get_measurement(x1, x2, x3, 1965 (uint32_t *) &x4, &mbox_error); 1966 SMC_RET4(handle, status, mbox_error, x3, x4); 1967 1968 case INTEL_SIP_SMC_FCS_GET_ATTESTATION_CERT: 1969 status = intel_fcs_get_attestation_cert(smc_fid, 0, x1, x2, 1970 (uint32_t *) &x3, &mbox_error); 1971 SMC_RET4(handle, status, mbox_error, x2, x3); 1972 1973 case INTEL_SIP_SMC_FCS_CREATE_CERT_ON_RELOAD: 1974 status = intel_fcs_create_cert_on_reload(smc_fid, 0, x1, &mbox_error); 1975 SMC_RET2(handle, status, mbox_error); 1976 1977 case INTEL_SIP_SMC_FCS_OPEN_CS_SESSION: 1978 status = intel_fcs_open_crypto_service_session(&retval, &mbox_error); 1979 SMC_RET3(handle, status, mbox_error, retval); 1980 1981 case INTEL_SIP_SMC_FCS_CLOSE_CS_SESSION: 1982 status = intel_fcs_close_crypto_service_session(x1, &mbox_error); 1983 SMC_RET2(handle, status, mbox_error); 1984 1985 case INTEL_SIP_SMC_FCS_IMPORT_CS_KEY: 1986 status = intel_fcs_import_crypto_service_key(x1, x2, &send_id); 1987 SMC_RET1(handle, status); 1988 1989 case INTEL_SIP_SMC_FCS_EXPORT_CS_KEY: 1990 status = intel_fcs_export_crypto_service_key(x1, x2, x3, 1991 (uint32_t *) &x4, &mbox_error); 1992 SMC_RET4(handle, status, mbox_error, x3, x4); 1993 1994 case INTEL_SIP_SMC_FCS_REMOVE_CS_KEY: 1995 status = intel_fcs_remove_crypto_service_key(x1, x2, 1996 &mbox_error); 1997 SMC_RET2(handle, status, mbox_error); 1998 1999 case INTEL_SIP_SMC_FCS_GET_CS_KEY_INFO: 2000 status = intel_fcs_get_crypto_service_key_info(x1, x2, x3, 2001 (uint32_t *) &x4, &mbox_error); 2002 SMC_RET4(handle, status, mbox_error, x3, x4); 2003 2004 case INTEL_SIP_SMC_FCS_GET_DIGEST_INIT: 2005 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2006 status = intel_fcs_get_digest_init(x1, x2, x3, 2007 x4, x5, &mbox_error); 2008 SMC_RET2(handle, status, mbox_error); 2009 2010 case INTEL_SIP_SMC_FCS_GET_DIGEST_UPDATE: 2011 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2012 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2013 status = intel_fcs_get_digest_update_finalize(smc_fid, 0, x1, x2, 2014 x3, x4, x5, (uint32_t *) &x6, false, 2015 &mbox_error, 0); 2016 SMC_RET4(handle, status, mbox_error, x5, x6); 2017 2018 case INTEL_SIP_SMC_FCS_GET_DIGEST_FINALIZE: 2019 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2020 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2021 status = intel_fcs_get_digest_update_finalize(smc_fid, 0, x1, x2, 2022 x3, x4, x5, (uint32_t *) &x6, true, 2023 &mbox_error, 0); 2024 SMC_RET4(handle, status, mbox_error, x5, x6); 2025 2026 case INTEL_SIP_SMC_FCS_GET_DIGEST_SMMU_UPDATE: 2027 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2028 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2029 status = intel_fcs_get_digest_smmu_update_finalize(x1, x2, x3, 2030 x4, x5, (uint32_t *) &x6, false, 2031 &mbox_error, &send_id); 2032 SMC_RET4(handle, status, mbox_error, x5, x6); 2033 2034 case INTEL_SIP_SMC_FCS_GET_DIGEST_SMMU_FINALIZE: 2035 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2036 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2037 status = intel_fcs_get_digest_smmu_update_finalize(x1, x2, x3, 2038 x4, x5, (uint32_t *) &x6, true, 2039 &mbox_error, &send_id); 2040 SMC_RET4(handle, status, mbox_error, x5, x6); 2041 2042 case INTEL_SIP_SMC_FCS_MAC_VERIFY_INIT: 2043 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2044 status = intel_fcs_mac_verify_init(x1, x2, x3, 2045 x4, x5, &mbox_error); 2046 SMC_RET2(handle, status, mbox_error); 2047 2048 case INTEL_SIP_SMC_FCS_MAC_VERIFY_UPDATE: 2049 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2050 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2051 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2052 status = intel_fcs_mac_verify_update_finalize(smc_fid, 0, x1, x2, 2053 x3, x4, x5, (uint32_t *) &x6, x7, false, 2054 &mbox_error, 0); 2055 SMC_RET4(handle, status, mbox_error, x5, x6); 2056 2057 case INTEL_SIP_SMC_FCS_MAC_VERIFY_FINALIZE: 2058 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2059 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2060 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2061 status = intel_fcs_mac_verify_update_finalize(smc_fid, 0, x1, x2, 2062 x3, x4, x5, (uint32_t *) &x6, x7, true, 2063 &mbox_error, 0); 2064 SMC_RET4(handle, status, mbox_error, x5, x6); 2065 2066 case INTEL_SIP_SMC_FCS_MAC_VERIFY_SMMU_UPDATE: 2067 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2068 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2069 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2070 status = intel_fcs_mac_verify_smmu_update_finalize(x1, x2, x3, 2071 x4, x5, (uint32_t *) &x6, x7, 2072 false, &mbox_error, &send_id); 2073 SMC_RET4(handle, status, mbox_error, x5, x6); 2074 2075 case INTEL_SIP_SMC_FCS_MAC_VERIFY_SMMU_FINALIZE: 2076 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2077 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2078 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2079 status = intel_fcs_mac_verify_smmu_update_finalize(x1, x2, x3, 2080 x4, x5, (uint32_t *) &x6, x7, 2081 true, &mbox_error, &send_id); 2082 SMC_RET4(handle, status, mbox_error, x5, x6); 2083 2084 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_INIT: 2085 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2086 status = intel_fcs_ecdsa_sha2_data_sign_init(x1, x2, x3, 2087 x4, x5, &mbox_error); 2088 SMC_RET2(handle, status, mbox_error); 2089 2090 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_UPDATE: 2091 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2092 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2093 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(smc_fid, 2094 0, x1, x2, x3, x4, x5, (uint32_t *) &x6, 2095 false, &mbox_error, 0); 2096 SMC_RET4(handle, status, mbox_error, x5, x6); 2097 2098 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE: 2099 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2100 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2101 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(smc_fid, 2102 0, x1, x2, x3, x4, x5, (uint32_t *) &x6, 2103 true, &mbox_error, 0); 2104 SMC_RET4(handle, status, mbox_error, x5, x6); 2105 2106 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_UPDATE: 2107 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2108 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2109 status = intel_fcs_ecdsa_sha2_data_sign_smmu_update_finalize(x1, 2110 x2, x3, x4, x5, (uint32_t *) &x6, false, 2111 &mbox_error, &send_id); 2112 SMC_RET4(handle, status, mbox_error, x5, x6); 2113 2114 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_FINALIZE: 2115 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2116 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2117 status = intel_fcs_ecdsa_sha2_data_sign_smmu_update_finalize(x1, 2118 x2, x3, x4, x5, (uint32_t *) &x6, true, 2119 &mbox_error, &send_id); 2120 SMC_RET4(handle, status, mbox_error, x5, x6); 2121 2122 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_INIT: 2123 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2124 status = intel_fcs_ecdsa_hash_sign_init(x1, x2, x3, 2125 x4, x5, &mbox_error); 2126 SMC_RET2(handle, status, mbox_error); 2127 2128 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_FINALIZE: 2129 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2130 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2131 status = intel_fcs_ecdsa_hash_sign_finalize(smc_fid, 0, x1, x2, 2132 x3, x4, x5, (uint32_t *) &x6, 2133 &mbox_error); 2134 SMC_RET4(handle, status, mbox_error, x5, x6); 2135 2136 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_INIT: 2137 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2138 status = intel_fcs_ecdsa_hash_sig_verify_init(x1, x2, x3, 2139 x4, x5, &mbox_error); 2140 SMC_RET2(handle, status, mbox_error); 2141 2142 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_FINALIZE: 2143 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2144 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2145 status = intel_fcs_ecdsa_hash_sig_verify_finalize(smc_fid, 0, x1, 2146 x2, x3, x4, x5, (uint32_t *) &x6, 2147 &mbox_error); 2148 SMC_RET4(handle, status, mbox_error, x5, x6); 2149 2150 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_INIT: 2151 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2152 status = intel_fcs_ecdsa_sha2_data_sig_verify_init(x1, x2, x3, 2153 x4, x5, &mbox_error); 2154 SMC_RET2(handle, status, mbox_error); 2155 2156 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_UPDATE: 2157 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2158 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2159 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2160 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize( 2161 smc_fid, 0, x1, x2, x3, x4, x5, 2162 (uint32_t *) &x6, x7, false, 2163 &mbox_error, 0); 2164 SMC_RET4(handle, status, mbox_error, x5, x6); 2165 2166 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_UPDATE: 2167 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2168 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2169 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2170 status = intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize( 2171 x1, x2, x3, x4, x5, (uint32_t *) &x6, 2172 x7, false, &mbox_error, &send_id); 2173 SMC_RET4(handle, status, mbox_error, x5, x6); 2174 2175 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_FINALIZE: 2176 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2177 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2178 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2179 status = intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize( 2180 x1, x2, x3, x4, x5, (uint32_t *) &x6, 2181 x7, true, &mbox_error, &send_id); 2182 SMC_RET4(handle, status, mbox_error, x5, x6); 2183 2184 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE: 2185 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2186 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2187 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2188 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize( 2189 smc_fid, 0, x1, x2, x3, x4, x5, 2190 (uint32_t *) &x6, x7, true, 2191 &mbox_error, 0); 2192 SMC_RET4(handle, status, mbox_error, x5, x6); 2193 2194 case INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_INIT: 2195 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2196 status = intel_fcs_ecdsa_get_pubkey_init(x1, x2, x3, 2197 x4, x5, &mbox_error); 2198 SMC_RET2(handle, status, mbox_error); 2199 2200 case INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_FINALIZE: 2201 status = intel_fcs_ecdsa_get_pubkey_finalize( 2202 INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_FINALIZE, 0, 2203 x1, x2, x3, (uint32_t *) &x4, &mbox_error); 2204 SMC_RET4(handle, status, mbox_error, x3, x4); 2205 2206 case INTEL_SIP_SMC_FCS_ECDH_REQUEST_INIT: 2207 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2208 status = intel_fcs_ecdh_request_init(x1, x2, x3, 2209 x4, x5, &mbox_error); 2210 SMC_RET2(handle, status, mbox_error); 2211 2212 case INTEL_SIP_SMC_FCS_ECDH_REQUEST_FINALIZE: 2213 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2214 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2215 status = intel_fcs_ecdh_request_finalize(smc_fid, 0, x1, x2, x3, 2216 x4, x5, (uint32_t *) &x6, &mbox_error); 2217 SMC_RET4(handle, status, mbox_error, x5, x6); 2218 2219 case INTEL_SIP_SMC_FCS_AES_CRYPT_INIT: 2220 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2221 status = intel_fcs_aes_crypt_init(x1, x2, x3, x4, x5, 2222 &mbox_error); 2223 SMC_RET2(handle, status, mbox_error); 2224 2225 case INTEL_SIP_SMC_FCS_AES_CRYPT_UPDATE: 2226 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2227 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2228 status = intel_fcs_aes_crypt_update_finalize(smc_fid, 0, x1, x2, 2229 x3, x4, x5, x6, 0, false, &send_id, 0, 0); 2230 SMC_RET1(handle, status); 2231 2232 case INTEL_SIP_SMC_FCS_AES_CRYPT_FINALIZE: 2233 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2234 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2235 status = intel_fcs_aes_crypt_update_finalize(smc_fid, 0, x1, x2, 2236 x3, x4, x5, x6, 0, true, &send_id, 0, 0); 2237 SMC_RET1(handle, status); 2238 2239 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 2240 case INTEL_SIP_SMC_FCS_SDM_REMAPPER_CONFIG: 2241 status = intel_smmu_hps_remapper_config(x1); 2242 SMC_RET1(handle, status); 2243 #endif 2244 2245 case INTEL_SIP_SMC_GET_ROM_PATCH_SHA384: 2246 status = intel_fcs_get_rom_patch_sha384(x1, &retval64, 2247 &mbox_error); 2248 SMC_RET4(handle, status, mbox_error, x1, retval64); 2249 2250 case INTEL_SIP_SMC_SVC_VERSION: 2251 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 2252 SIP_SVC_VERSION_MAJOR, 2253 SIP_SVC_VERSION_MINOR); 2254 2255 case INTEL_SIP_SMC_SEU_ERR_STATUS: 2256 status = intel_sdm_seu_err_read(seu_respbuf, 2257 ARRAY_SIZE(seu_respbuf)); 2258 if (status) { 2259 SMC_RET1(handle, status); 2260 } else { 2261 SMC_RET3(handle, seu_respbuf[0], seu_respbuf[1], seu_respbuf[2]); 2262 } 2263 2264 case INTEL_SIP_SMC_SAFE_INJECT_SEU_ERR: 2265 status = intel_sdm_safe_inject_seu_err((uint32_t *)&x1, (uint32_t)x2); 2266 SMC_RET1(handle, status); 2267 2268 case INTEL_SIP_SMC_ATF_BUILD_VER: 2269 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, VERSION_MAJOR, 2270 VERSION_MINOR, VERSION_PATCH); 2271 2272 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 2273 case INTEL_SIP_SMC_INJECT_IO96B_ECC_ERR: 2274 intel_inject_io96b_ecc_err((uint32_t *)&x1, (uint32_t)x2); 2275 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_OK); 2276 #endif 2277 2278 default: 2279 return socfpga_sip_handler(smc_fid, x1, x2, x3, x4, 2280 cookie, handle, flags); 2281 } 2282 } 2283 2284 uintptr_t sip_smc_handler(uint32_t smc_fid, 2285 u_register_t x1, 2286 u_register_t x2, 2287 u_register_t x3, 2288 u_register_t x4, 2289 void *cookie, 2290 void *handle, 2291 u_register_t flags) 2292 { 2293 uint32_t cmd = smc_fid & INTEL_SIP_SMC_CMD_MASK; 2294 2295 if (cmd >= INTEL_SIP_SMC_CMD_V2_RANGE_BEGIN && 2296 cmd <= INTEL_SIP_SMC_CMD_V2_RANGE_END) { 2297 return sip_smc_handler_v2(smc_fid, x1, x2, x3, x4, 2298 cookie, handle, flags); 2299 } 2300 #if SIP_SVC_V3 2301 else if ((cmd >= INTEL_SIP_SMC_CMD_V3_RANGE_BEGIN) && 2302 (cmd <= INTEL_SIP_SMC_CMD_V3_RANGE_END)) { 2303 uintptr_t ret = sip_smc_handler_v3(smc_fid, x1, x2, x3, x4, 2304 cookie, handle, flags); 2305 return ret; 2306 } 2307 #endif 2308 else { 2309 return sip_smc_handler_v1(smc_fid, x1, x2, x3, x4, 2310 cookie, handle, flags); 2311 } 2312 } 2313 2314 DECLARE_RT_SVC( 2315 socfpga_sip_svc, 2316 OEN_SIP_START, 2317 OEN_SIP_END, 2318 SMC_TYPE_FAST, 2319 NULL, 2320 sip_smc_handler 2321 ); 2322 2323 DECLARE_RT_SVC( 2324 socfpga_sip_svc_std, 2325 OEN_SIP_START, 2326 OEN_SIP_END, 2327 SMC_TYPE_YIELD, 2328 NULL, 2329 sip_smc_handler 2330 ); 2331