1 /* 2 * Copyright (c) 2019-2023, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. 4 * Copyright (c) 2024-2025, Altera Corporation. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #include <assert.h> 10 #include <common/debug.h> 11 #include <common/runtime_svc.h> 12 #include <lib/mmio.h> 13 #include <tools_share/uuid.h> 14 15 #include "socfpga_fcs.h" 16 #include "socfpga_mailbox.h" 17 #include "socfpga_plat_def.h" 18 #include "socfpga_reset_manager.h" 19 #include "socfpga_sip_svc.h" 20 #include "socfpga_system_manager.h" 21 22 /* Total buffer the driver can hold */ 23 #define FPGA_CONFIG_BUFFER_SIZE 4 24 25 static config_type request_type = NO_REQUEST; 26 static int current_block, current_buffer; 27 static int read_block, max_blocks; 28 static uint32_t send_id, rcv_id; 29 static uint32_t bytes_per_block, blocks_submitted; 30 static bool bridge_disable; 31 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 32 static uint32_t g_remapper_bypass; 33 #endif 34 35 /* RSU static variables */ 36 static uint32_t rsu_dcmf_ver[4] = {0}; 37 static uint16_t rsu_dcmf_stat[4] = {0}; 38 static uint32_t rsu_max_retry; 39 40 /* SiP Service UUID */ 41 DEFINE_SVC_UUID2(intl_svc_uid, 42 0xa85273b0, 0xe85a, 0x4862, 0xa6, 0x2a, 43 0xfa, 0x88, 0x88, 0x17, 0x68, 0x81); 44 45 static uint64_t socfpga_sip_handler(uint32_t smc_fid, 46 uint64_t x1, 47 uint64_t x2, 48 uint64_t x3, 49 uint64_t x4, 50 void *cookie, 51 void *handle, 52 uint64_t flags) 53 { 54 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); 55 SMC_RET1(handle, SMC_UNK); 56 } 57 58 struct fpga_config_info fpga_config_buffers[FPGA_CONFIG_BUFFER_SIZE]; 59 60 static int intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer) 61 { 62 uint32_t args[3]; 63 64 while (max_blocks > 0 && buffer->size > buffer->size_written) { 65 args[0] = (1<<8); 66 args[1] = buffer->addr + buffer->size_written; 67 if (buffer->size - buffer->size_written <= bytes_per_block) { 68 args[2] = buffer->size - buffer->size_written; 69 current_buffer++; 70 current_buffer %= FPGA_CONFIG_BUFFER_SIZE; 71 } else { 72 args[2] = bytes_per_block; 73 } 74 75 buffer->size_written += args[2]; 76 mailbox_send_cmd_async(&send_id, MBOX_RECONFIG_DATA, args, 77 3U, CMD_INDIRECT); 78 79 buffer->subblocks_sent++; 80 max_blocks--; 81 } 82 83 return !max_blocks; 84 } 85 86 static int intel_fpga_sdm_write_all(void) 87 { 88 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 89 if (intel_fpga_sdm_write_buffer( 90 &fpga_config_buffers[current_buffer])) { 91 break; 92 } 93 } 94 return 0; 95 } 96 97 static uint32_t intel_mailbox_fpga_config_isdone(uint32_t *err_states) 98 { 99 uint32_t ret; 100 101 if (err_states == NULL) 102 return INTEL_SIP_SMC_STATUS_REJECTED; 103 104 switch (request_type) { 105 case RECONFIGURATION: 106 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, 107 true, err_states); 108 break; 109 case BITSTREAM_AUTH: 110 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, 111 false, err_states); 112 break; 113 default: 114 ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS, 115 false, err_states); 116 break; 117 } 118 119 if (ret != 0U) { 120 if (ret == MBOX_CFGSTAT_STATE_CONFIG) { 121 return INTEL_SIP_SMC_STATUS_BUSY; 122 } else { 123 request_type = NO_REQUEST; 124 return INTEL_SIP_SMC_STATUS_ERROR; 125 } 126 } 127 128 if (bridge_disable != 0U) { 129 socfpga_bridges_enable(~0); /* Enable bridge */ 130 bridge_disable = false; 131 } 132 request_type = NO_REQUEST; 133 134 return INTEL_SIP_SMC_STATUS_OK; 135 } 136 137 static int mark_last_buffer_xfer_completed(uint32_t *buffer_addr_completed) 138 { 139 int i; 140 141 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 142 if (fpga_config_buffers[i].block_number == current_block) { 143 fpga_config_buffers[i].subblocks_sent--; 144 if (fpga_config_buffers[i].subblocks_sent == 0 145 && fpga_config_buffers[i].size <= 146 fpga_config_buffers[i].size_written) { 147 fpga_config_buffers[i].write_requested = 0; 148 current_block++; 149 *buffer_addr_completed = 150 fpga_config_buffers[i].addr; 151 return 0; 152 } 153 } 154 } 155 156 return -1; 157 } 158 159 static int intel_fpga_config_completed_write(uint32_t *completed_addr, 160 uint32_t *count, uint32_t *job_id) 161 { 162 uint32_t resp[5]; 163 unsigned int resp_len = ARRAY_SIZE(resp); 164 int status = INTEL_SIP_SMC_STATUS_OK; 165 int all_completed = 1; 166 *count = 0; 167 168 while (*count < 3) { 169 170 status = mailbox_read_response(job_id, 171 resp, &resp_len); 172 173 if (status < 0) { 174 break; 175 } 176 177 max_blocks++; 178 179 if (mark_last_buffer_xfer_completed( 180 &completed_addr[*count]) == 0) { 181 *count = *count + 1; 182 } else { 183 break; 184 } 185 } 186 187 if (*count <= 0) { 188 if (status != MBOX_NO_RESPONSE && 189 status != MBOX_TIMEOUT && resp_len != 0) { 190 mailbox_clear_response(); 191 request_type = NO_REQUEST; 192 return INTEL_SIP_SMC_STATUS_ERROR; 193 } 194 195 *count = 0; 196 } 197 198 intel_fpga_sdm_write_all(); 199 200 if (*count > 0) { 201 status = INTEL_SIP_SMC_STATUS_OK; 202 } else if (*count == 0) { 203 status = INTEL_SIP_SMC_STATUS_BUSY; 204 } 205 206 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 207 if (fpga_config_buffers[i].write_requested != 0) { 208 all_completed = 0; 209 break; 210 } 211 } 212 213 if (all_completed == 1) { 214 return INTEL_SIP_SMC_STATUS_OK; 215 } 216 217 return status; 218 } 219 220 static int intel_fpga_config_start(uint32_t flag) 221 { 222 uint32_t argument = 0x1; 223 uint32_t response[3]; 224 int status = 0; 225 unsigned int size = 0; 226 unsigned int resp_len = ARRAY_SIZE(response); 227 228 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 229 /* 230 * To trigger isolation 231 * FPGA configuration complete signal should be de-asserted 232 */ 233 INFO("SOCFPGA: Request SDM to trigger isolation\n"); 234 status = mailbox_send_fpga_config_comp(); 235 236 if (status < 0) { 237 INFO("SOCFPGA: Isolation for FPGA configuration complete is not executed\n"); 238 } 239 #endif 240 241 request_type = RECONFIGURATION; 242 243 if (!CONFIG_TEST_FLAG(flag, PARTIAL_CONFIG)) { 244 bridge_disable = true; 245 } 246 247 if (CONFIG_TEST_FLAG(flag, AUTHENTICATION)) { 248 size = 1; 249 bridge_disable = false; 250 request_type = BITSTREAM_AUTH; 251 } 252 253 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 254 intel_smmu_hps_remapper_init(0U); 255 #endif 256 257 mailbox_clear_response(); 258 259 mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_CANCEL, NULL, 0U, 260 CMD_CASUAL, NULL, NULL); 261 262 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_RECONFIG, &argument, size, 263 CMD_CASUAL, response, &resp_len); 264 265 if (status < 0) { 266 bridge_disable = false; 267 request_type = NO_REQUEST; 268 return INTEL_SIP_SMC_STATUS_ERROR; 269 } 270 271 max_blocks = response[0]; 272 bytes_per_block = response[1]; 273 274 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 275 fpga_config_buffers[i].size = 0; 276 fpga_config_buffers[i].size_written = 0; 277 fpga_config_buffers[i].addr = 0; 278 fpga_config_buffers[i].write_requested = 0; 279 fpga_config_buffers[i].block_number = 0; 280 fpga_config_buffers[i].subblocks_sent = 0; 281 } 282 283 blocks_submitted = 0; 284 current_block = 0; 285 read_block = 0; 286 current_buffer = 0; 287 288 /* Disable bridge on full reconfiguration */ 289 if (bridge_disable) { 290 socfpga_bridges_disable(~0); 291 } 292 293 return INTEL_SIP_SMC_STATUS_OK; 294 } 295 296 static bool is_fpga_config_buffer_full(void) 297 { 298 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 299 if (!fpga_config_buffers[i].write_requested) { 300 return false; 301 } 302 } 303 return true; 304 } 305 306 bool is_address_in_ddr_range(uint64_t addr, uint64_t size) 307 { 308 uint128_t dram_max_sz = (uint128_t)DRAM_BASE + (uint128_t)DRAM_SIZE; 309 uint128_t dram_region_end = (uint128_t)addr + (uint128_t)size; 310 311 if (!addr && !size) { 312 return true; 313 } 314 if (size > (UINT64_MAX - addr)) { 315 return false; 316 } 317 if (addr < BL31_LIMIT) { 318 return false; 319 } 320 if (dram_region_end > dram_max_sz) { 321 return false; 322 } 323 324 return true; 325 } 326 327 static uint32_t intel_fpga_config_write(uint64_t mem, uint64_t size) 328 { 329 int i; 330 331 intel_fpga_sdm_write_all(); 332 333 if (!is_address_in_ddr_range(mem, size) || 334 is_fpga_config_buffer_full()) { 335 return INTEL_SIP_SMC_STATUS_REJECTED; 336 } 337 338 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 339 intel_smmu_hps_remapper_init(&mem); 340 #endif 341 342 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 343 int j = (i + current_buffer) % FPGA_CONFIG_BUFFER_SIZE; 344 345 if (!fpga_config_buffers[j].write_requested) { 346 fpga_config_buffers[j].addr = mem; 347 fpga_config_buffers[j].size = size; 348 fpga_config_buffers[j].size_written = 0; 349 fpga_config_buffers[j].write_requested = 1; 350 fpga_config_buffers[j].block_number = 351 blocks_submitted++; 352 fpga_config_buffers[j].subblocks_sent = 0; 353 break; 354 } 355 } 356 357 if (is_fpga_config_buffer_full()) { 358 return INTEL_SIP_SMC_STATUS_BUSY; 359 } 360 361 return INTEL_SIP_SMC_STATUS_OK; 362 } 363 364 static int is_out_of_sec_range(uint64_t reg_addr) 365 { 366 #if DEBUG 367 return 0; 368 #endif 369 370 #if PLATFORM_MODEL != PLAT_SOCFPGA_AGILEX5 371 switch (reg_addr) { 372 case(0xF8011100): /* ECCCTRL1 */ 373 case(0xF8011104): /* ECCCTRL2 */ 374 case(0xF8011110): /* ERRINTEN */ 375 case(0xF8011114): /* ERRINTENS */ 376 case(0xF8011118): /* ERRINTENR */ 377 case(0xF801111C): /* INTMODE */ 378 case(0xF8011120): /* INTSTAT */ 379 case(0xF8011124): /* DIAGINTTEST */ 380 case(0xF801112C): /* DERRADDRA */ 381 case(0xFA000000): /* SMMU SCR0 */ 382 case(0xFA000004): /* SMMU SCR1 */ 383 case(0xFA000400): /* SMMU NSCR0 */ 384 case(0xFA004000): /* SMMU SSD0_REG */ 385 case(0xFA000820): /* SMMU SMR8 */ 386 case(0xFA000c20): /* SMMU SCR8 */ 387 case(0xFA028000): /* SMMU CB8_SCTRL */ 388 case(0xFA001020): /* SMMU CBAR8 */ 389 case(0xFA028030): /* SMMU TCR_LPAE */ 390 case(0xFA028020): /* SMMU CB8_TTBR0_LOW */ 391 case(0xFA028024): /* SMMU CB8_PRRR_HIGH */ 392 case(0xFA028038): /* SMMU CB8_PRRR_MIR0 */ 393 case(0xFA02803C): /* SMMU CB8_PRRR_MIR1 */ 394 case(0xFA028010): /* SMMU_CB8)TCR2 */ 395 case(0xFFD080A4): /* SDM SMMU STREAM ID REG */ 396 case(0xFA001820): /* SMMU_CBA2R8 */ 397 case(0xFA000074): /* SMMU_STLBGSTATUS */ 398 case(0xFA0287F4): /* SMMU_CB8_TLBSTATUS */ 399 case(0xFA000060): /* SMMU_STLBIALL */ 400 case(0xFA000070): /* SMMU_STLBGSYNC */ 401 case(0xFA028618): /* CB8_TLBALL */ 402 case(0xFA0287F0): /* CB8_TLBSYNC */ 403 case(0xFFD12028): /* SDMMCGRP_CTRL */ 404 case(0xFFD12044): /* EMAC0 */ 405 case(0xFFD12048): /* EMAC1 */ 406 case(0xFFD1204C): /* EMAC2 */ 407 case(0xFFD12090): /* ECC_INT_MASK_VALUE */ 408 case(0xFFD12094): /* ECC_INT_MASK_SET */ 409 case(0xFFD12098): /* ECC_INT_MASK_CLEAR */ 410 case(0xFFD1209C): /* ECC_INTSTATUS_SERR */ 411 case(0xFFD120A0): /* ECC_INTSTATUS_DERR */ 412 case(0xFFD120C0): /* NOC_TIMEOUT */ 413 case(0xFFD120C4): /* NOC_IDLEREQ_SET */ 414 case(0xFFD120C8): /* NOC_IDLEREQ_CLR */ 415 case(0xFFD120D0): /* NOC_IDLEACK */ 416 case(0xFFD120D4): /* NOC_IDLESTATUS */ 417 case(0xFFD12200): /* BOOT_SCRATCH_COLD0 */ 418 case(0xFFD12204): /* BOOT_SCRATCH_COLD1 */ 419 case(0xFFD12220): /* BOOT_SCRATCH_COLD8 */ 420 case(0xFFD12224): /* BOOT_SCRATCH_COLD9 */ 421 return 0; 422 #else 423 switch (reg_addr) { 424 425 case(0xF8011104): /* ECCCTRL2 */ 426 case(0xFFD12028): /* SDMMCGRP_CTRL */ 427 case(0xFFD120C4): /* NOC_IDLEREQ_SET */ 428 case(0xFFD120C8): /* NOC_IDLEREQ_CLR */ 429 case(0xFFD120D0): /* NOC_IDLEACK */ 430 431 432 case(SOCFPGA_MEMCTRL(ECCCTRL1)): /* ECCCTRL1 */ 433 case(SOCFPGA_MEMCTRL(ERRINTEN)): /* ERRINTEN */ 434 case(SOCFPGA_MEMCTRL(ERRINTENS)): /* ERRINTENS */ 435 case(SOCFPGA_MEMCTRL(ERRINTENR)): /* ERRINTENR */ 436 case(SOCFPGA_MEMCTRL(INTMODE)): /* INTMODE */ 437 case(SOCFPGA_MEMCTRL(INTSTAT)): /* INTSTAT */ 438 case(SOCFPGA_MEMCTRL(DIAGINTTEST)): /* DIAGINTTEST */ 439 case(SOCFPGA_MEMCTRL(DERRADDRA)): /* DERRADDRA */ 440 441 case(SOCFPGA_ECC_QSPI(INITSTAT)): /* ECC_QSPI_INITSTAT */ 442 case(SOCFPGA_SYSMGR(EMAC_0)): /* EMAC0 */ 443 case(SOCFPGA_SYSMGR(EMAC_1)): /* EMAC1 */ 444 case(SOCFPGA_SYSMGR(EMAC_2)): /* EMAC2 */ 445 case(SOCFPGA_SYSMGR(ECC_INTMASK_VALUE)): /* ECC_INT_MASK_VALUE */ 446 case(SOCFPGA_SYSMGR(ECC_INTMASK_SET)): /* ECC_INT_MASK_SET */ 447 case(SOCFPGA_SYSMGR(ECC_INTMASK_CLR)): /* ECC_INT_MASK_CLEAR */ 448 case(SOCFPGA_SYSMGR(ECC_INTMASK_SERR)): /* ECC_INTSTATUS_SERR */ 449 case(SOCFPGA_SYSMGR(ECC_INTMASK_DERR)): /* ECC_INTSTATUS_DERR */ 450 case(SOCFPGA_SYSMGR(NOC_TIMEOUT)): /* NOC_TIMEOUT */ 451 case(SOCFPGA_SYSMGR(NOC_IDLESTATUS)): /* NOC_IDLESTATUS */ 452 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_0)): /* BOOT_SCRATCH_COLD0 */ 453 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_1)): /* BOOT_SCRATCH_COLD1 */ 454 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_8)): /* BOOT_SCRATCH_COLD8 */ 455 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_9)): /* BOOT_SCRATCH_COLD9 */ 456 #endif 457 case(SOCFPGA_ECC_QSPI(CTRL)): /* ECC_QSPI_CTRL */ 458 case(SOCFPGA_ECC_QSPI(ERRINTEN)): /* ECC_QSPI_ERRINTEN */ 459 case(SOCFPGA_ECC_QSPI(ERRINTENS)): /* ECC_QSPI_ERRINTENS */ 460 case(SOCFPGA_ECC_QSPI(ERRINTENR)): /* ECC_QSPI_ERRINTENR */ 461 case(SOCFPGA_ECC_QSPI(INTMODE)): /* ECC_QSPI_INTMODE */ 462 case(SOCFPGA_ECC_QSPI(ECC_ACCCTRL)): /* ECC_QSPI_ECC_ACCCTRL */ 463 case(SOCFPGA_ECC_QSPI(ECC_STARTACC)): /* ECC_QSPI_ECC_STARTACC */ 464 case(SOCFPGA_ECC_QSPI(ECC_WDCTRL)): /* ECC_QSPI_ECC_WDCTRL */ 465 case(SOCFPGA_ECC_QSPI(INTSTAT)): /* ECC_QSPI_INTSTAT */ 466 case(SOCFPGA_ECC_QSPI(INTTEST)): /* ECC_QSPI_INTMODE */ 467 return 0; 468 469 default: 470 break; 471 } 472 473 return -1; 474 } 475 476 /* Secure register access */ 477 uint32_t intel_secure_reg_read(uint64_t reg_addr, uint32_t *retval) 478 { 479 if (is_out_of_sec_range(reg_addr)) { 480 return INTEL_SIP_SMC_STATUS_ERROR; 481 } 482 483 *retval = mmio_read_32(reg_addr); 484 485 return INTEL_SIP_SMC_STATUS_OK; 486 } 487 488 uint32_t intel_secure_reg_write(uint64_t reg_addr, uint32_t val, 489 uint32_t *retval) 490 { 491 if (is_out_of_sec_range(reg_addr)) { 492 return INTEL_SIP_SMC_STATUS_ERROR; 493 } 494 495 switch (reg_addr) { 496 case(SOCFPGA_ECC_QSPI(INTSTAT)): /* ECC_QSPI_INTSTAT */ 497 case(SOCFPGA_ECC_QSPI(INTTEST)): /* ECC_QSPI_INTMODE */ 498 mmio_write_16(reg_addr, val); 499 break; 500 default: 501 mmio_write_32(reg_addr, val); 502 break; 503 } 504 505 return intel_secure_reg_read(reg_addr, retval); 506 } 507 508 uint32_t intel_secure_reg_update(uint64_t reg_addr, uint32_t mask, 509 uint32_t val, uint32_t *retval) 510 { 511 if (!intel_secure_reg_read(reg_addr, retval)) { 512 *retval &= ~mask; 513 *retval |= val & mask; 514 return intel_secure_reg_write(reg_addr, *retval, retval); 515 } 516 517 return INTEL_SIP_SMC_STATUS_ERROR; 518 } 519 520 /* Intel Remote System Update (RSU) services */ 521 uint64_t intel_rsu_update_address; 522 523 static uint32_t intel_rsu_status(uint64_t *respbuf, unsigned int respbuf_sz) 524 { 525 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) { 526 return INTEL_SIP_SMC_RSU_ERROR; 527 } 528 529 return INTEL_SIP_SMC_STATUS_OK; 530 } 531 532 static uint32_t intel_rsu_get_device_info(uint32_t *respbuf, 533 unsigned int respbuf_sz) 534 { 535 if (mailbox_rsu_get_device_info((uint32_t *)respbuf, respbuf_sz) < 0) { 536 return INTEL_SIP_SMC_RSU_ERROR; 537 } 538 539 return INTEL_SIP_SMC_STATUS_OK; 540 } 541 542 uint32_t intel_rsu_update(uint64_t update_address) 543 { 544 if (update_address > SIZE_MAX) { 545 return INTEL_SIP_SMC_STATUS_REJECTED; 546 } 547 548 intel_rsu_update_address = update_address; 549 return INTEL_SIP_SMC_STATUS_OK; 550 } 551 552 static uint32_t intel_rsu_notify(uint32_t execution_stage) 553 { 554 if (mailbox_hps_stage_notify(execution_stage) < 0) { 555 return INTEL_SIP_SMC_RSU_ERROR; 556 } 557 558 return INTEL_SIP_SMC_STATUS_OK; 559 } 560 561 static uint32_t intel_rsu_retry_counter(uint32_t *respbuf, uint32_t respbuf_sz, 562 uint32_t *ret_stat) 563 { 564 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) { 565 return INTEL_SIP_SMC_RSU_ERROR; 566 } 567 568 *ret_stat = respbuf[8]; 569 return INTEL_SIP_SMC_STATUS_OK; 570 } 571 572 static uint32_t intel_rsu_copy_dcmf_version(uint64_t dcmf_ver_1_0, 573 uint64_t dcmf_ver_3_2) 574 { 575 rsu_dcmf_ver[0] = dcmf_ver_1_0; 576 rsu_dcmf_ver[1] = dcmf_ver_1_0 >> 32; 577 rsu_dcmf_ver[2] = dcmf_ver_3_2; 578 rsu_dcmf_ver[3] = dcmf_ver_3_2 >> 32; 579 580 return INTEL_SIP_SMC_STATUS_OK; 581 } 582 583 static uint32_t intel_rsu_copy_dcmf_status(uint64_t dcmf_stat) 584 { 585 rsu_dcmf_stat[0] = 0xFFFF & (dcmf_stat >> (0 * 16)); 586 rsu_dcmf_stat[1] = 0xFFFF & (dcmf_stat >> (1 * 16)); 587 rsu_dcmf_stat[2] = 0xFFFF & (dcmf_stat >> (2 * 16)); 588 rsu_dcmf_stat[3] = 0xFFFF & (dcmf_stat >> (3 * 16)); 589 590 return INTEL_SIP_SMC_STATUS_OK; 591 } 592 593 /* Intel HWMON services */ 594 static uint32_t intel_hwmon_readtemp(uint32_t chan, uint32_t *retval) 595 { 596 if (mailbox_hwmon_readtemp(chan, retval) < 0) { 597 return INTEL_SIP_SMC_STATUS_ERROR; 598 } 599 600 return INTEL_SIP_SMC_STATUS_OK; 601 } 602 603 static uint32_t intel_hwmon_readvolt(uint32_t chan, uint32_t *retval) 604 { 605 if (mailbox_hwmon_readvolt(chan, retval) < 0) { 606 return INTEL_SIP_SMC_STATUS_ERROR; 607 } 608 609 return INTEL_SIP_SMC_STATUS_OK; 610 } 611 612 /* Mailbox services */ 613 static uint32_t intel_smc_fw_version(uint32_t *fw_version) 614 { 615 int status; 616 unsigned int resp_len = CONFIG_STATUS_WORD_SIZE; 617 uint32_t resp_data[CONFIG_STATUS_WORD_SIZE] = {0U}; 618 619 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CONFIG_STATUS, NULL, 0U, 620 CMD_CASUAL, resp_data, &resp_len); 621 622 if (status < 0) { 623 return INTEL_SIP_SMC_STATUS_ERROR; 624 } 625 626 if (resp_len <= CONFIG_STATUS_FW_VER_OFFSET) { 627 return INTEL_SIP_SMC_STATUS_ERROR; 628 } 629 630 *fw_version = resp_data[CONFIG_STATUS_FW_VER_OFFSET] & CONFIG_STATUS_FW_VER_MASK; 631 632 return INTEL_SIP_SMC_STATUS_OK; 633 } 634 635 static uint32_t intel_mbox_send_cmd(uint32_t cmd, uint32_t *args, 636 unsigned int len, uint32_t urgent, uint64_t response, 637 unsigned int resp_len, int *mbox_status, 638 unsigned int *len_in_resp) 639 { 640 *len_in_resp = 0; 641 *mbox_status = GENERIC_RESPONSE_ERROR; 642 643 if (!is_address_in_ddr_range((uint64_t)args, sizeof(uint32_t) * len)) { 644 return INTEL_SIP_SMC_STATUS_REJECTED; 645 } 646 647 int status = mailbox_send_cmd(MBOX_JOB_ID, cmd, args, len, urgent, 648 (uint32_t *) response, &resp_len); 649 650 if (status < 0) { 651 *mbox_status = -status; 652 return INTEL_SIP_SMC_STATUS_ERROR; 653 } 654 655 *mbox_status = 0; 656 *len_in_resp = resp_len; 657 658 flush_dcache_range(response, resp_len * MBOX_WORD_BYTE); 659 660 return INTEL_SIP_SMC_STATUS_OK; 661 } 662 663 static int intel_smc_get_usercode(uint32_t *user_code) 664 { 665 int status; 666 unsigned int resp_len = sizeof(user_code) / MBOX_WORD_BYTE; 667 668 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_GET_USERCODE, NULL, 669 0U, CMD_CASUAL, user_code, &resp_len); 670 671 if (status < 0) { 672 return INTEL_SIP_SMC_STATUS_ERROR; 673 } 674 675 return INTEL_SIP_SMC_STATUS_OK; 676 } 677 678 uint32_t intel_smc_service_completed(uint64_t addr, uint32_t size, 679 uint32_t mode, uint32_t *job_id, 680 uint32_t *ret_size, uint32_t *mbox_error) 681 { 682 int status = 0; 683 uint32_t resp_len = size / MBOX_WORD_BYTE; 684 685 if (resp_len > MBOX_DATA_MAX_LEN) { 686 return INTEL_SIP_SMC_STATUS_REJECTED; 687 } 688 689 if (!is_address_in_ddr_range(addr, size)) { 690 return INTEL_SIP_SMC_STATUS_REJECTED; 691 } 692 693 if (mode == SERVICE_COMPLETED_MODE_ASYNC) { 694 status = mailbox_read_response_async(job_id, 695 NULL, (uint32_t *) addr, &resp_len, 0); 696 } else { 697 status = mailbox_read_response(job_id, 698 (uint32_t *) addr, &resp_len); 699 700 if (status == MBOX_NO_RESPONSE) { 701 status = MBOX_BUSY; 702 } 703 } 704 705 if (status == MBOX_NO_RESPONSE) { 706 return INTEL_SIP_SMC_STATUS_NO_RESPONSE; 707 } 708 709 if (status == MBOX_BUSY) { 710 return INTEL_SIP_SMC_STATUS_BUSY; 711 } 712 713 *ret_size = resp_len * MBOX_WORD_BYTE; 714 flush_dcache_range(addr, *ret_size); 715 716 if (status == MBOX_RET_SDOS_DECRYPTION_ERROR_102 || 717 status == MBOX_RET_SDOS_DECRYPTION_ERROR_103) { 718 *mbox_error = -status; 719 } else if (status != MBOX_RET_OK) { 720 *mbox_error = -status; 721 return INTEL_SIP_SMC_STATUS_ERROR; 722 } 723 724 return INTEL_SIP_SMC_STATUS_OK; 725 } 726 727 /* Miscellaneous HPS services */ 728 uint32_t intel_hps_set_bridges(uint64_t enable, uint64_t mask) 729 { 730 int status = 0; 731 732 if ((enable & SOCFPGA_BRIDGE_ENABLE) != 0U) { 733 if ((enable & SOCFPGA_BRIDGE_HAS_MASK) != 0U) { 734 status = socfpga_bridges_enable((uint32_t)mask); 735 } else { 736 status = socfpga_bridges_enable(~0); 737 } 738 } else { 739 if ((enable & SOCFPGA_BRIDGE_HAS_MASK) != 0U) { 740 status = socfpga_bridges_disable((uint32_t)mask); 741 } else { 742 status = socfpga_bridges_disable(~0); 743 } 744 } 745 746 if (status < 0) { 747 return INTEL_SIP_SMC_STATUS_ERROR; 748 } 749 750 return INTEL_SIP_SMC_STATUS_OK; 751 } 752 753 /* SDM SEU Error services */ 754 static uint32_t intel_sdm_seu_err_read(uint32_t *respbuf, unsigned int respbuf_sz) 755 { 756 if (mailbox_seu_err_status(respbuf, respbuf_sz) < 0) { 757 return INTEL_SIP_SMC_SEU_ERR_READ_ERROR; 758 } 759 760 return INTEL_SIP_SMC_STATUS_OK; 761 } 762 763 /* SDM SAFE SEU Error inject services */ 764 static uint32_t intel_sdm_safe_inject_seu_err(uint32_t *command, uint32_t len) 765 { 766 if (mailbox_safe_inject_seu_err(command, len) < 0) { 767 return INTEL_SIP_SMC_SEU_ERR_READ_ERROR; 768 } 769 770 return INTEL_SIP_SMC_STATUS_OK; 771 } 772 773 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 774 /* SMMU HPS Remapper */ 775 void intel_smmu_hps_remapper_init(uint64_t *mem) 776 { 777 /* Read out Bit 1 value */ 778 uint32_t remap = (mmio_read_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_POR_1)) & 0x02); 779 780 if ((remap == 0x00) && (g_remapper_bypass == 0x00)) { 781 /* Update DRAM Base address for SDM SMMU */ 782 mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_ARADDR_REMAP), DRAM_BASE); 783 mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_AWADDR_REMAP), DRAM_BASE); 784 *mem = *mem - DRAM_BASE; 785 } else { 786 *mem = *mem - DRAM_BASE; 787 } 788 } 789 790 int intel_smmu_hps_remapper_config(uint32_t remapper_bypass) 791 { 792 /* Read out the JTAG-ID from boot scratch register */ 793 if (is_agilex5_A5F0() || is_agilex5_A5F4()) { 794 if (remapper_bypass == 0x01) { 795 g_remapper_bypass = remapper_bypass; 796 mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_ARADDR_REMAP), 0); 797 mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_AWADDR_REMAP), 0); 798 } 799 } 800 return INTEL_SIP_SMC_STATUS_OK; 801 } 802 #endif 803 804 #if SIP_SVC_V3 805 uint8_t sip_smc_cmd_cb_ret2(void *resp_desc, void *cmd_desc, uint64_t *ret_args) 806 { 807 uint8_t ret_args_len = 0U; 808 sdm_response_t *resp = (sdm_response_t *)resp_desc; 809 sdm_command_t *cmd = (sdm_command_t *)cmd_desc; 810 811 (void)cmd; 812 /* Returns 3 SMC arguments for SMC_RET3 */ 813 ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK; 814 ret_args[ret_args_len++] = resp->err_code; 815 816 return ret_args_len; 817 } 818 819 uint8_t sip_smc_cmd_cb_ret3(void *resp_desc, void *cmd_desc, uint64_t *ret_args) 820 { 821 uint8_t ret_args_len = 0U; 822 sdm_response_t *resp = (sdm_response_t *)resp_desc; 823 sdm_command_t *cmd = (sdm_command_t *)cmd_desc; 824 825 (void)cmd; 826 /* Returns 3 SMC arguments for SMC_RET3 */ 827 ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK; 828 ret_args[ret_args_len++] = resp->err_code; 829 ret_args[ret_args_len++] = resp->resp_data[0]; 830 831 return ret_args_len; 832 } 833 834 uint8_t sip_smc_ret_nbytes_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args) 835 { 836 uint8_t ret_args_len = 0U; 837 sdm_response_t *resp = (sdm_response_t *)resp_desc; 838 sdm_command_t *cmd = (sdm_command_t *)cmd_desc; 839 840 (void)cmd; 841 INFO("MBOX: %s: mailbox_err 0%x, nbytes_ret %d\n", 842 __func__, resp->err_code, resp->rcvd_resp_len * MBOX_WORD_BYTE); 843 844 ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK; 845 ret_args[ret_args_len++] = resp->err_code; 846 ret_args[ret_args_len++] = resp->rcvd_resp_len * MBOX_WORD_BYTE; 847 848 return ret_args_len; 849 } 850 851 uint8_t sip_smc_get_chipid_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args) 852 { 853 uint8_t ret_args_len = 0U; 854 sdm_response_t *resp = (sdm_response_t *)resp_desc; 855 sdm_command_t *cmd = (sdm_command_t *)cmd_desc; 856 857 (void)cmd; 858 INFO("MBOX: %s: mailbox_err 0%x, data[0] 0x%x, data[1] 0x%x\n", 859 __func__, resp->err_code, resp->resp_data[0], resp->resp_data[1]); 860 861 ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK; 862 ret_args[ret_args_len++] = resp->err_code; 863 ret_args[ret_args_len++] = resp->resp_data[0]; 864 ret_args[ret_args_len++] = resp->resp_data[1]; 865 866 return ret_args_len; 867 } 868 869 static uintptr_t smc_ret(void *handle, uint64_t *ret_args, uint32_t ret_args_len) 870 { 871 872 switch (ret_args_len) { 873 case SMC_RET_ARGS_ONE: 874 VERBOSE("SVC V3: %s: x0 0x%lx\n", __func__, ret_args[0]); 875 SMC_RET1(handle, ret_args[0]); 876 break; 877 878 case SMC_RET_ARGS_TWO: 879 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx\n", __func__, ret_args[0], ret_args[1]); 880 SMC_RET2(handle, ret_args[0], ret_args[1]); 881 break; 882 883 case SMC_RET_ARGS_THREE: 884 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx, x2 0x%lx\n", 885 __func__, ret_args[0], ret_args[1], ret_args[2]); 886 SMC_RET3(handle, ret_args[0], ret_args[1], ret_args[2]); 887 break; 888 889 case SMC_RET_ARGS_FOUR: 890 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx, x2 0x%lx, x3 0x%lx\n", 891 __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3]); 892 SMC_RET4(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3]); 893 break; 894 895 case SMC_RET_ARGS_FIVE: 896 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx, x2 0x%lx, x3 0x%lx, x4 0x%lx\n", 897 __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4]); 898 SMC_RET5(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4]); 899 break; 900 901 case SMC_RET_ARGS_SIX: 902 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx x2 0x%lx x3 0x%lx, x4 0x%lx x5 0x%lx\n", 903 __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4], 904 ret_args[5]); 905 SMC_RET6(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4], 906 ret_args[5]); 907 break; 908 909 case SMC_RET_ARGS_SEVEN: 910 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx x2 0x%lx, x3 0x%lx, x4 0x%lx, x5 0x%lx\t" 911 "x6 0x%lx\n", 912 __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4], 913 ret_args[5], ret_args[6]); 914 SMC_RET7(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4], 915 ret_args[5], ret_args[6]); 916 break; 917 918 case SMC_RET_ARGS_EIGHT: 919 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx x2 0x%lx, x3 0x%lx, x4 0x%lx x5 0x%lx\t" 920 "x6 0x%lx, x7 0x%lx\n", 921 __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4], 922 ret_args[5], ret_args[6], ret_args[7]); 923 SMC_RET8(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4], 924 ret_args[5], ret_args[6], ret_args[7]); 925 break; 926 927 case SMC_RET_ARGS_NINE: 928 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx x2 0x%lx, x3 0x%lx, x4 0x%lx, x5 0x%lx\t" 929 "x6 0x%lx, x7 0x%lx, x8 0x%lx\n", 930 __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4], 931 ret_args[5], ret_args[6], ret_args[7], ret_args[8]); 932 SMC_RET18(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4], 933 ret_args[5], ret_args[6], ret_args[7], ret_args[8], 934 0, 0, 0, 0, 0, 0, 0, 0, 0); 935 break; 936 937 case SMC_RET_ARGS_TEN: 938 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx, x2 0x%lx, x3 0x%lx, x4 0x%lx x5 0x%lx\t" 939 "x6 0x%lx, x7 0x%lx x8 0x%lx, x9 0x%lx, x10 0x%lx\n", 940 __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], 941 ret_args[4], ret_args[5], ret_args[6], ret_args[7], ret_args[8], 942 ret_args[9], ret_args[10]); 943 SMC_RET18(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4], 944 ret_args[5], ret_args[6], ret_args[7], ret_args[8], ret_args[9], 945 0, 0, 0, 0, 0, 0, 0, 0); 946 break; 947 948 default: 949 VERBOSE("SVC V3: %s ret_args_len is wrong, please check %d\n ", 950 __func__, ret_args_len); 951 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR); 952 break; 953 } 954 } 955 956 static inline bool is_gen_mbox_cmd_allowed(uint32_t cmd) 957 { 958 /* Check if the command is allowed to be executed in generic mbox format */ 959 bool is_cmd_allowed = false; 960 961 switch (cmd) { 962 case ALTERA_SIP_SMC_ASYNC_FCS_OPEN_CS_SESSION: 963 case ALTERA_SIP_SMC_ASYNC_FCS_CLOSE_CS_SESSION: 964 case ALTERA_SIP_SMC_ASYNC_FCS_IMPORT_CS_KEY: 965 case ALTERA_SIP_SMC_ASYNC_FCS_EXPORT_CS_KEY: 966 case ALTERA_SIP_SMC_ASYNC_FCS_REMOVE_CS_KEY: 967 case ALTERA_SIP_SMC_ASYNC_FCS_GET_CS_KEY_INFO: 968 case ALTERA_SIP_SMC_ASYNC_FCS_CREATE_CS_KEY: 969 case ALTERA_SIP_SMC_ASYNC_FCS_RANDOM_NUMBER_EXT: 970 case ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_INIT: 971 case ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_UPDATE: 972 case ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_FINALIZE: 973 case ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_INIT: 974 case ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_UPDATE: 975 case ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_FINALIZE: 976 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIGN_INIT: 977 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIGN_FINALIZE: 978 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_INIT: 979 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_UPDATE: 980 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE: 981 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_UPDATE: 982 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_FINALIZE: 983 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIG_VERIFY_INIT: 984 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIG_VERIFY_FINALIZE: 985 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_INIT: 986 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_UPDATE: 987 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE: 988 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_UPDATE: 989 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_FINALIZE: 990 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_GET_PUBKEY_INIT: 991 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_GET_PUBKEY_FINALIZE: 992 case ALTERA_SIP_SMC_ASYNC_FCS_ECDH_REQUEST_INIT: 993 case ALTERA_SIP_SMC_ASYNC_FCS_ECDH_REQUEST_FINALIZE: 994 case ALTERA_SIP_SMC_ASYNC_FCS_HKDF_REQUEST: 995 case ALTERA_SIP_SMC_ASYNC_FCS_CRYPTION_EXT: 996 case ALTERA_SIP_SMC_ASYNC_FCS_CRYPTION: 997 /* These commands are not supported in the generic mailbox format. */ 998 break; 999 1000 default: 1001 is_cmd_allowed = true; 1002 break; 1003 } /* switch */ 1004 1005 return is_cmd_allowed; 1006 } 1007 1008 /* 1009 * This function is responsible for handling all SiP SVC V3 calls from the 1010 * non-secure world. 1011 */ 1012 static uintptr_t sip_smc_handler_v3(uint32_t smc_fid, 1013 u_register_t x1, 1014 u_register_t x2, 1015 u_register_t x3, 1016 u_register_t x4, 1017 void *cookie, 1018 void *handle, 1019 u_register_t flags) 1020 { 1021 int status = 0; 1022 uint32_t mbox_error = 0U; 1023 u_register_t x5, x6, x7, x8, x9, x10, x11; 1024 1025 /* Get all the SMC call arguments */ 1026 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1027 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1028 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1029 x8 = SMC_GET_GP(handle, CTX_GPREG_X8); 1030 x9 = SMC_GET_GP(handle, CTX_GPREG_X9); 1031 x10 = SMC_GET_GP(handle, CTX_GPREG_X10); 1032 x11 = SMC_GET_GP(handle, CTX_GPREG_X11); 1033 1034 INFO("MBOX: SVC_V3: x0 0x%x, x1 0x%lx, x2 0x%lx, x3 0x%lx, x4 0x%lx, x5 0x%lx\n", 1035 smc_fid, x1, x2, x3, x4, x5); 1036 INFO("MBOX: SVC_V3: x6 0x%lx, x7 0x%lx, x8 0x%lx, x9 0x%lx, x10 0x%lx x11 0x%lx\n", 1037 x6, x7, x8, x9, x10, x11); 1038 1039 switch (smc_fid) { 1040 case ALTERA_SIP_SMC_ASYNC_RESP_POLL: 1041 { 1042 uint64_t ret_args[16] = {0}; 1043 uint32_t ret_args_len = 0; 1044 1045 status = mailbox_response_poll_v3(GET_CLIENT_ID(x1), 1046 GET_JOB_ID(x1), 1047 ret_args, 1048 &ret_args_len); 1049 /* Always reserve [0] index for command status. */ 1050 ret_args[0] = status; 1051 1052 /* Return SMC call based on the number of return arguments */ 1053 return smc_ret(handle, ret_args, ret_args_len); 1054 } 1055 1056 case ALTERA_SIP_SMC_ASYNC_RESP_POLL_ON_INTR: 1057 { 1058 /* TBD: Here now we don't need these CID and JID?? */ 1059 uint8_t client_id = 0U; 1060 uint8_t job_id = 0U; 1061 uint64_t trans_id_bitmap[4] = {0U}; 1062 1063 status = mailbox_response_poll_on_intr_v3(&client_id, 1064 &job_id, 1065 trans_id_bitmap); 1066 1067 SMC_RET5(handle, status, trans_id_bitmap[0], trans_id_bitmap[1], 1068 trans_id_bitmap[2], trans_id_bitmap[3]); 1069 break; 1070 } 1071 1072 case ALTERA_SIP_SMC_ASYNC_GET_DEVICE_IDENTITY: 1073 { 1074 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1075 GET_JOB_ID(x1), 1076 MBOX_CMD_GET_DEVICEID, 1077 NULL, 1078 0U, 1079 MBOX_CMD_FLAG_CASUAL, 1080 sip_smc_ret_nbytes_cb, 1081 (uint32_t *)x2, 1082 2); 1083 1084 SMC_RET1(handle, status); 1085 } 1086 1087 case ALTERA_SIP_SMC_ASYNC_GET_IDCODE: 1088 { 1089 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1090 GET_JOB_ID(x1), 1091 MBOX_CMD_GET_IDCODE, 1092 NULL, 1093 0U, 1094 MBOX_CMD_FLAG_CASUAL, 1095 sip_smc_cmd_cb_ret3, 1096 NULL, 1097 0); 1098 1099 SMC_RET1(handle, status); 1100 } 1101 1102 case ALTERA_SIP_SMC_ASYNC_QSPI_OPEN: 1103 { 1104 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1105 GET_JOB_ID(x1), 1106 MBOX_CMD_QSPI_OPEN, 1107 NULL, 1108 0U, 1109 MBOX_CMD_FLAG_CASUAL, 1110 sip_smc_cmd_cb_ret2, 1111 NULL, 1112 0U); 1113 1114 SMC_RET1(handle, status); 1115 } 1116 1117 case ALTERA_SIP_SMC_ASYNC_QSPI_CLOSE: 1118 { 1119 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1120 GET_JOB_ID(x1), 1121 MBOX_CMD_QSPI_CLOSE, 1122 NULL, 1123 0U, 1124 MBOX_CMD_FLAG_CASUAL, 1125 sip_smc_cmd_cb_ret2, 1126 NULL, 1127 0U); 1128 1129 SMC_RET1(handle, status); 1130 } 1131 1132 case ALTERA_SIP_SMC_ASYNC_QSPI_SET_CS: 1133 { 1134 uint32_t cmd_data = 0U; 1135 uint32_t chip_sel = (uint32_t)x2; 1136 uint32_t comb_addr_mode = (uint32_t)x3; 1137 uint32_t ext_dec_mode = (uint32_t)x4; 1138 1139 cmd_data = (chip_sel << MBOX_QSPI_SET_CS_OFFSET) | 1140 (comb_addr_mode << MBOX_QSPI_SET_CS_CA_OFFSET) | 1141 (ext_dec_mode << MBOX_QSPI_SET_CS_MODE_OFFSET); 1142 1143 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1144 GET_JOB_ID(x1), 1145 MBOX_CMD_QSPI_SET_CS, 1146 &cmd_data, 1147 1U, 1148 MBOX_CMD_FLAG_CASUAL, 1149 sip_smc_cmd_cb_ret2, 1150 NULL, 1151 0U); 1152 1153 SMC_RET1(handle, status); 1154 } 1155 1156 case ALTERA_SIP_SMC_ASYNC_QSPI_ERASE: 1157 { 1158 uint32_t qspi_addr = (uint32_t)x2; 1159 uint32_t qspi_nwords = (uint32_t)x3; 1160 1161 /* QSPI address offset to start erase, must be 4K aligned */ 1162 if (MBOX_IS_4K_ALIGNED(qspi_addr)) { 1163 ERROR("MBOX: 0x%x: QSPI address not 4K aligned\n", 1164 smc_fid); 1165 status = INTEL_SIP_SMC_STATUS_REJECTED; 1166 SMC_RET1(handle, status); 1167 } 1168 1169 /* Number of words to erase, multiples of 0x400 or 4K */ 1170 if (qspi_nwords % MBOX_QSPI_ERASE_SIZE_GRAN) { 1171 ERROR("MBOX: 0x%x: Given words not in multiples of 4K\n", 1172 smc_fid); 1173 status = INTEL_SIP_SMC_STATUS_REJECTED; 1174 SMC_RET1(handle, status); 1175 } 1176 1177 uint32_t cmd_data[2] = {qspi_addr, qspi_nwords}; 1178 1179 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1180 GET_JOB_ID(x1), 1181 MBOX_CMD_QSPI_ERASE, 1182 cmd_data, 1183 sizeof(cmd_data) / MBOX_WORD_BYTE, 1184 MBOX_CMD_FLAG_CASUAL, 1185 sip_smc_cmd_cb_ret2, 1186 NULL, 1187 0U); 1188 1189 SMC_RET1(handle, status); 1190 } 1191 1192 case ALTERA_SIP_SMC_ASYNC_QSPI_WRITE: 1193 { 1194 uint32_t *qspi_payload = (uint32_t *)x2; 1195 uint32_t qspi_total_nwords = (((uint32_t)x3) / MBOX_WORD_BYTE); 1196 uint32_t qspi_addr = qspi_payload[0]; 1197 uint32_t qspi_nwords = qspi_payload[1]; 1198 1199 if (!MBOX_IS_WORD_ALIGNED(qspi_addr)) { 1200 ERROR("MBOX: 0x%x: Given address is not WORD aligned\n", 1201 smc_fid); 1202 status = INTEL_SIP_SMC_STATUS_REJECTED; 1203 SMC_RET1(handle, status); 1204 } 1205 1206 if (qspi_nwords > MBOX_QSPI_RW_MAX_WORDS) { 1207 ERROR("MBOX: 0x%x: Number of words exceeds max limit\n", 1208 smc_fid); 1209 status = INTEL_SIP_SMC_STATUS_REJECTED; 1210 SMC_RET1(handle, status); 1211 } 1212 1213 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1214 GET_JOB_ID(x1), 1215 MBOX_CMD_QSPI_WRITE, 1216 qspi_payload, 1217 qspi_total_nwords, 1218 MBOX_CMD_FLAG_CASUAL, 1219 sip_smc_cmd_cb_ret2, 1220 NULL, 1221 0U); 1222 1223 SMC_RET1(handle, status); 1224 } 1225 1226 case ALTERA_SIP_SMC_ASYNC_QSPI_READ: 1227 { 1228 uint32_t qspi_addr = (uint32_t)x2; 1229 uint32_t qspi_nwords = (((uint32_t)x4) / MBOX_WORD_BYTE); 1230 1231 if (qspi_nwords > MBOX_QSPI_RW_MAX_WORDS) { 1232 ERROR("MBOX: 0x%x: Number of words exceeds max limit\n", 1233 smc_fid); 1234 status = INTEL_SIP_SMC_STATUS_REJECTED; 1235 SMC_RET1(handle, status); 1236 } 1237 1238 uint32_t cmd_data[2] = {qspi_addr, qspi_nwords}; 1239 1240 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1241 GET_JOB_ID(x1), 1242 MBOX_CMD_QSPI_READ, 1243 cmd_data, 1244 sizeof(cmd_data) / MBOX_WORD_BYTE, 1245 MBOX_CMD_FLAG_CASUAL, 1246 sip_smc_ret_nbytes_cb, 1247 (uint32_t *)x3, 1248 2); 1249 1250 SMC_RET1(handle, status); 1251 } 1252 1253 case ALTERA_SIP_SMC_ASYNC_QSPI_GET_DEV_INFO: 1254 { 1255 uint32_t *dst_addr = (uint32_t *)x2; 1256 1257 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1258 GET_JOB_ID(x1), 1259 MBOX_CMD_QSPI_GET_DEV_INFO, 1260 NULL, 1261 0U, 1262 MBOX_CMD_FLAG_CASUAL, 1263 sip_smc_ret_nbytes_cb, 1264 (uint32_t *)dst_addr, 1265 2); 1266 1267 SMC_RET1(handle, status); 1268 } 1269 1270 case ALTERA_SIP_SMC_ASYNC_HWMON_READVOLT: 1271 case ALTERA_SIP_SMC_ASYNC_HWMON_READTEMP: 1272 { 1273 uint32_t channel = (uint32_t)x2; 1274 uint32_t mbox_cmd = ((smc_fid == ALTERA_SIP_SMC_ASYNC_HWMON_READVOLT) ? 1275 MBOX_HWMON_READVOLT : MBOX_HWMON_READTEMP); 1276 1277 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1278 GET_JOB_ID(x1), 1279 mbox_cmd, 1280 &channel, 1281 1U, 1282 MBOX_CMD_FLAG_CASUAL, 1283 sip_smc_cmd_cb_ret3, 1284 NULL, 1285 0); 1286 1287 SMC_RET1(handle, status); 1288 } 1289 1290 case ALTERA_SIP_SMC_ASYNC_GEN_MBOX_CMD: 1291 { 1292 /* Filter the required commands here. */ 1293 if (!is_gen_mbox_cmd_allowed(smc_fid)) { 1294 status = INTEL_SIP_SMC_STATUS_REJECTED; 1295 SMC_RET1(handle, status); 1296 } 1297 1298 /* Collect all the args passed in, and send the mailbox command. */ 1299 uint32_t mbox_cmd = (uint32_t)x2; 1300 uint32_t *cmd_payload_addr = NULL; 1301 uint32_t cmd_payload_len = (uint32_t)x4 / MBOX_WORD_BYTE; 1302 uint32_t *resp_payload_addr = NULL; 1303 uint32_t resp_payload_len = (uint32_t)x6 / MBOX_WORD_BYTE; 1304 1305 if ((cmd_payload_len > MBOX_GEN_CMD_MAX_WORDS) || 1306 (resp_payload_len > MBOX_GEN_CMD_MAX_WORDS)) { 1307 ERROR("MBOX: 0x%x: Command/Response payload length exceeds max limit\n", 1308 smc_fid); 1309 status = INTEL_SIP_SMC_STATUS_REJECTED; 1310 SMC_RET1(handle, status); 1311 } 1312 1313 /* Make sure we have valid command payload length and buffer */ 1314 if (cmd_payload_len != 0U) { 1315 cmd_payload_addr = (uint32_t *)x3; 1316 if (cmd_payload_addr == NULL) { 1317 ERROR("MBOX: 0x%x: Command payload address is NULL\n", 1318 smc_fid); 1319 status = INTEL_SIP_SMC_STATUS_REJECTED; 1320 SMC_RET1(handle, status); 1321 } 1322 } 1323 1324 /* Make sure we have valid response payload length and buffer */ 1325 if (resp_payload_len != 0U) { 1326 resp_payload_addr = (uint32_t *)x5; 1327 if (resp_payload_addr == NULL) { 1328 ERROR("MBOX: 0x%x: Response payload address is NULL\n", 1329 smc_fid); 1330 status = INTEL_SIP_SMC_STATUS_REJECTED; 1331 SMC_RET1(handle, status); 1332 } 1333 } 1334 1335 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1336 GET_JOB_ID(x1), 1337 mbox_cmd, 1338 (uint32_t *)cmd_payload_addr, 1339 cmd_payload_len, 1340 MBOX_CMD_FLAG_CASUAL, 1341 sip_smc_ret_nbytes_cb, 1342 (uint32_t *)resp_payload_addr, 1343 resp_payload_len); 1344 1345 SMC_RET1(handle, status); 1346 } 1347 1348 case ALTERA_SIP_SMC_ASYNC_FCS_RANDOM_NUMBER_EXT: 1349 { 1350 uint32_t session_id = (uint32_t)x2; 1351 uint32_t context_id = (uint32_t)x3; 1352 uint64_t ret_random_addr = (uint64_t)x4; 1353 uint32_t random_len = (uint32_t)SMC_GET_GP(handle, CTX_GPREG_X5); 1354 uint32_t crypto_header = 0U; 1355 1356 if ((random_len > (FCS_RANDOM_EXT_MAX_WORD_SIZE * MBOX_WORD_BYTE)) || 1357 (random_len == 0U) || 1358 (!is_size_4_bytes_aligned(random_len))) { 1359 ERROR("MBOX: 0x%x is rejected\n", smc_fid); 1360 status = INTEL_SIP_SMC_STATUS_REJECTED; 1361 SMC_RET1(handle, status); 1362 } 1363 1364 crypto_header = ((FCS_CS_FIELD_FLAG_INIT | FCS_CS_FIELD_FLAG_FINALIZE) << 1365 FCS_CS_FIELD_FLAG_OFFSET); 1366 fcs_rng_payload payload = {session_id, context_id, 1367 crypto_header, random_len}; 1368 1369 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1370 GET_JOB_ID(x1), 1371 MBOX_FCS_RANDOM_GEN, 1372 (uint32_t *)&payload, 1373 sizeof(payload) / MBOX_WORD_BYTE, 1374 MBOX_CMD_FLAG_CASUAL, 1375 sip_smc_ret_nbytes_cb, 1376 (uint32_t *)ret_random_addr, 1377 2); 1378 SMC_RET1(handle, status); 1379 } 1380 1381 case ALTERA_SIP_SMC_ASYNC_FCS_GET_PROVISION_DATA: 1382 { 1383 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1384 GET_JOB_ID(x1), 1385 MBOX_FCS_GET_PROVISION, 1386 NULL, 1387 0U, 1388 MBOX_CMD_FLAG_CASUAL, 1389 sip_smc_ret_nbytes_cb, 1390 (uint32_t *)x2, 1391 2); 1392 SMC_RET1(handle, status); 1393 } 1394 1395 case ALTERA_SIP_SMC_ASYNC_FCS_CNTR_SET_PREAUTH: 1396 { 1397 status = intel_fcs_cntr_set_preauth(smc_fid, x1, x2, x3, 1398 x4, &mbox_error); 1399 SMC_RET1(handle, status); 1400 } 1401 1402 case ALTERA_SIP_SMC_ASYNC_FCS_CHIP_ID: 1403 { 1404 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1405 GET_JOB_ID(x1), 1406 MBOX_CMD_GET_CHIPID, 1407 NULL, 1408 0U, 1409 MBOX_CMD_FLAG_CASUAL, 1410 sip_smc_get_chipid_cb, 1411 NULL, 1412 0); 1413 SMC_RET1(handle, status); 1414 } 1415 1416 case ALTERA_SIP_SMC_ASYNC_FCS_GET_ATTESTATION_CERT: 1417 { 1418 status = intel_fcs_get_attestation_cert(smc_fid, x1, x2, x3, 1419 (uint32_t *) &x4, &mbox_error); 1420 SMC_RET1(handle, status); 1421 } 1422 1423 case ALTERA_SIP_SMC_ASYNC_FCS_CREATE_CERT_ON_RELOAD: 1424 { 1425 status = intel_fcs_create_cert_on_reload(smc_fid, x1, 1426 x2, &mbox_error); 1427 SMC_RET1(handle, status); 1428 } 1429 1430 case ALTERA_SIP_SMC_ASYNC_FCS_CRYPTION_EXT: 1431 { 1432 if (x4 == FCS_MODE_ENCRYPT) { 1433 status = intel_fcs_encryption_ext(smc_fid, x1, x2, x3, 1434 x5, x6, x7, (uint32_t *) &x8, 1435 &mbox_error, x10, x11); 1436 } else if (x4 == FCS_MODE_DECRYPT) { 1437 status = intel_fcs_decryption_ext(smc_fid, x1, x2, x3, 1438 x5, x6, x7, (uint32_t *) &x8, 1439 &mbox_error, x9, x10, x11); 1440 } else { 1441 ERROR("MBOX: 0x%x: Wrong crypto mode\n", smc_fid); 1442 status = INTEL_SIP_SMC_STATUS_REJECTED; 1443 } 1444 SMC_RET1(handle, status); 1445 } 1446 1447 case ALTERA_SIP_SMC_ASYNC_FCS_SEND_CERTIFICATE: 1448 { 1449 status = intel_fcs_send_cert(smc_fid, x1, x2, x3, &mbox_error); 1450 SMC_RET1(handle, status); 1451 } 1452 1453 case ALTERA_SIP_SMC_ASYNC_FCS_OPEN_CS_SESSION: 1454 { 1455 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1456 GET_JOB_ID(x1), 1457 MBOX_FCS_OPEN_CS_SESSION, 1458 NULL, 1459 0U, 1460 MBOX_CMD_FLAG_CASUAL, 1461 sip_smc_cmd_cb_ret3, 1462 NULL, 1463 0); 1464 SMC_RET1(handle, status); 1465 } 1466 1467 case ALTERA_SIP_SMC_ASYNC_FCS_CLOSE_CS_SESSION: 1468 { 1469 uint32_t session_id = (uint32_t)x2; 1470 1471 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1472 GET_JOB_ID(x1), 1473 MBOX_FCS_CLOSE_CS_SESSION, 1474 &session_id, 1475 1U, 1476 MBOX_CMD_FLAG_CASUAL, 1477 sip_smc_cmd_cb_ret2, 1478 NULL, 1479 0); 1480 SMC_RET1(handle, status); 1481 } 1482 1483 case ALTERA_SIP_SMC_ASYNC_FCS_IMPORT_CS_KEY: 1484 { 1485 uint64_t key_addr = x2; 1486 uint32_t key_len_words = (uint32_t)x3 / MBOX_WORD_BYTE; 1487 1488 if ((key_len_words > FCS_CS_KEY_OBJ_MAX_WORD_SIZE) || 1489 (!is_address_in_ddr_range(key_addr, key_len_words * 4))) { 1490 ERROR("MBOX: 0x%x: Addr not in DDR range or key len exceeds\n", 1491 smc_fid); 1492 status = INTEL_SIP_SMC_STATUS_REJECTED; 1493 SMC_RET1(handle, status); 1494 } 1495 1496 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1497 GET_JOB_ID(x1), 1498 MBOX_FCS_IMPORT_CS_KEY, 1499 (uint32_t *)key_addr, 1500 key_len_words, 1501 MBOX_CMD_FLAG_CASUAL, 1502 sip_smc_cmd_cb_ret3, 1503 NULL, 1504 0); 1505 SMC_RET1(handle, status); 1506 } 1507 1508 case ALTERA_SIP_SMC_ASYNC_FCS_CREATE_CS_KEY: 1509 { 1510 uint64_t key_addr = x2; 1511 uint32_t key_len_words = (uint32_t)x3 / MBOX_WORD_BYTE; 1512 1513 if (!is_address_in_ddr_range(key_addr, key_len_words * 4)) { 1514 ERROR("MBOX: 0x%x: Addr not in DDR range\n", smc_fid); 1515 status = INTEL_SIP_SMC_STATUS_REJECTED; 1516 SMC_RET1(handle, status); 1517 } 1518 1519 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1520 GET_JOB_ID(x1), 1521 MBOX_FCS_CREATE_CS_KEY, 1522 (uint32_t *)key_addr, 1523 key_len_words, 1524 MBOX_CMD_FLAG_CASUAL, 1525 sip_smc_cmd_cb_ret3, 1526 NULL, 1527 0); 1528 SMC_RET1(handle, status); 1529 } 1530 1531 case ALTERA_SIP_SMC_ASYNC_FCS_EXPORT_CS_KEY: 1532 { 1533 uint32_t session_id = (uint32_t)x2; 1534 uint32_t key_uid = (uint32_t)x3; 1535 uint64_t ret_key_addr = (uint64_t)x4; 1536 uint32_t key_len = (uint32_t)SMC_GET_GP(handle, CTX_GPREG_X5); 1537 1538 if (!is_address_in_ddr_range(ret_key_addr, key_len)) { 1539 ERROR("MBOX: 0x%x: Addr not in DDR range\n", smc_fid); 1540 status = INTEL_SIP_SMC_STATUS_REJECTED; 1541 SMC_RET1(handle, status); 1542 } 1543 1544 fcs_cs_key_payload payload = {session_id, RESERVED_AS_ZERO, 1545 RESERVED_AS_ZERO, key_uid}; 1546 1547 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1548 GET_JOB_ID(x1), 1549 MBOX_FCS_EXPORT_CS_KEY, 1550 (uint32_t *)&payload, 1551 sizeof(payload) / MBOX_WORD_BYTE, 1552 MBOX_CMD_FLAG_CASUAL, 1553 sip_smc_ret_nbytes_cb, 1554 (uint32_t *)ret_key_addr, 1555 2); 1556 SMC_RET1(handle, status); 1557 } 1558 1559 case ALTERA_SIP_SMC_ASYNC_FCS_REMOVE_CS_KEY: 1560 { 1561 uint32_t session_id = (uint32_t)x2; 1562 uint32_t key_uid = (uint32_t)x3; 1563 1564 fcs_cs_key_payload payload = {session_id, RESERVED_AS_ZERO, 1565 RESERVED_AS_ZERO, key_uid}; 1566 1567 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1568 GET_JOB_ID(x1), 1569 MBOX_FCS_REMOVE_CS_KEY, 1570 (uint32_t *)&payload, 1571 sizeof(payload) / MBOX_WORD_BYTE, 1572 MBOX_CMD_FLAG_CASUAL, 1573 sip_smc_cmd_cb_ret3, 1574 NULL, 1575 0); 1576 SMC_RET1(handle, status); 1577 } 1578 1579 case ALTERA_SIP_SMC_ASYNC_FCS_GET_CS_KEY_INFO: 1580 { 1581 uint32_t session_id = (uint32_t)x2; 1582 uint32_t key_uid = (uint32_t)x3; 1583 uint64_t ret_key_addr = (uint64_t)x4; 1584 uint32_t key_len = (uint32_t)SMC_GET_GP(handle, CTX_GPREG_X5); 1585 1586 if (!is_address_in_ddr_range(ret_key_addr, key_len)) { 1587 ERROR("MBOX: 0x%x: Addr not in DDR range\n", smc_fid); 1588 status = INTEL_SIP_SMC_STATUS_REJECTED; 1589 SMC_RET1(handle, status); 1590 } 1591 1592 fcs_cs_key_payload payload = {session_id, RESERVED_AS_ZERO, 1593 RESERVED_AS_ZERO, key_uid}; 1594 1595 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1596 GET_JOB_ID(x1), 1597 MBOX_FCS_GET_CS_KEY_INFO, 1598 (uint32_t *)&payload, 1599 sizeof(payload) / MBOX_WORD_BYTE, 1600 MBOX_CMD_FLAG_CASUAL, 1601 sip_smc_ret_nbytes_cb, 1602 (uint32_t *)ret_key_addr, 1603 2); 1604 SMC_RET1(handle, status); 1605 } 1606 1607 case ALTERA_SIP_SMC_ASYNC_FCS_AES_CRYPT_INIT: 1608 { 1609 status = intel_fcs_aes_crypt_init(x2, x3, x4, x5, 1610 x6, &mbox_error); 1611 SMC_RET1(handle, status); 1612 } 1613 1614 case ALTERA_SIP_SMC_ASYNC_FCS_AES_CRYPT_UPDATE: 1615 case ALTERA_SIP_SMC_ASYNC_FCS_AES_CRYPT_FINALIZE: 1616 { 1617 uint32_t job_id = 0U; 1618 bool is_final = (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_AES_CRYPT_FINALIZE) ? 1619 true : false; 1620 1621 status = intel_fcs_aes_crypt_update_finalize(smc_fid, x1, x2, 1622 x3, x4, x5, x6, x7, x8, is_final, 1623 &job_id, x9, x10); 1624 SMC_RET1(handle, status); 1625 } 1626 1627 case ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_INIT: 1628 { 1629 status = intel_fcs_get_digest_init(x2, x3, x4, x5, x6, 1630 &mbox_error); 1631 SMC_RET1(handle, status); 1632 } 1633 1634 case ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_UPDATE: 1635 case ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_FINALIZE: 1636 { 1637 bool is_final = (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_FINALIZE) ? 1638 true : false; 1639 1640 status = intel_fcs_get_digest_update_finalize(smc_fid, x1, x2, 1641 x3, x4, x5, x6, (uint32_t *) &x7, 1642 is_final, &mbox_error, x8); 1643 1644 SMC_RET1(handle, status); 1645 } 1646 1647 case ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_INIT: 1648 { 1649 status = intel_fcs_mac_verify_init(x2, x3, x4, x5, x6, 1650 &mbox_error); 1651 SMC_RET1(handle, status); 1652 } 1653 1654 case ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_UPDATE: 1655 case ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_FINALIZE: 1656 { 1657 bool is_final = (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_FINALIZE) ? 1658 true : false; 1659 1660 status = intel_fcs_mac_verify_update_finalize(smc_fid, x1, x2, 1661 x3, x4, x5, x6, (uint32_t *) &x7, x8, 1662 is_final, &mbox_error, x9); 1663 SMC_RET1(handle, status); 1664 } 1665 1666 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIGN_INIT: 1667 { 1668 status = intel_fcs_ecdsa_hash_sign_init(x2, x3, x4, x5, x6, 1669 &mbox_error); 1670 SMC_RET1(handle, status); 1671 } 1672 1673 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIGN_FINALIZE: 1674 { 1675 status = intel_fcs_ecdsa_hash_sign_finalize(smc_fid, x1, x2, x3, 1676 x4, x5, x6, (uint32_t *) &x7, 1677 &mbox_error); 1678 SMC_RET1(handle, status); 1679 } 1680 1681 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_INIT: 1682 { 1683 status = intel_fcs_ecdsa_sha2_data_sign_init(x2, x3, x4, x5, x6, 1684 &mbox_error); 1685 SMC_RET1(handle, status); 1686 } 1687 1688 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_UPDATE: 1689 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE: 1690 { 1691 bool is_final = (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE) 1692 ? true : false; 1693 1694 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(smc_fid, 1695 x1, x2, x3, x4, x5, x6, (uint32_t *) &x7, 1696 is_final, &mbox_error, x8); 1697 SMC_RET1(handle, status); 1698 } 1699 1700 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIG_VERIFY_INIT: 1701 { 1702 status = intel_fcs_ecdsa_hash_sig_verify_init(x2, x3, x4, x5, 1703 x6, &mbox_error); 1704 SMC_RET1(handle, status); 1705 } 1706 1707 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIG_VERIFY_FINALIZE: 1708 { 1709 status = intel_fcs_ecdsa_hash_sig_verify_finalize(smc_fid, x1, 1710 x2, x3, x4, x5, x6, (uint32_t *) &x7, 1711 &mbox_error); 1712 SMC_RET1(handle, status); 1713 } 1714 1715 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_INIT: 1716 { 1717 status = intel_fcs_ecdsa_sha2_data_sig_verify_init(x2, x3, x4, 1718 x5, x6, &mbox_error); 1719 SMC_RET1(handle, status); 1720 } 1721 1722 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_UPDATE: 1723 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE: 1724 { 1725 bool is_final = (smc_fid == 1726 ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE) ? 1727 true : false; 1728 1729 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize( 1730 smc_fid, x1, x2, x3, x4, x5, x6, 1731 (uint32_t *) &x7, x8, is_final, 1732 &mbox_error, x9); 1733 SMC_RET1(handle, status); 1734 } 1735 1736 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_GET_PUBKEY_INIT: 1737 { 1738 status = intel_fcs_ecdsa_get_pubkey_init(x2, x3, x4, x5, x6, 1739 &mbox_error); 1740 SMC_RET1(handle, status); 1741 } 1742 1743 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_GET_PUBKEY_FINALIZE: 1744 { 1745 status = intel_fcs_ecdsa_get_pubkey_finalize(smc_fid, x1, x2, x3, 1746 x4, (uint32_t *) &x5, &mbox_error); 1747 SMC_RET1(handle, status); 1748 } 1749 1750 case ALTERA_SIP_SMC_ASYNC_FCS_ECDH_REQUEST_INIT: 1751 { 1752 status = intel_fcs_ecdh_request_init(x2, x3, x4, x5, x6, 1753 &mbox_error); 1754 SMC_RET1(handle, status); 1755 } 1756 1757 case ALTERA_SIP_SMC_ASYNC_FCS_ECDH_REQUEST_FINALIZE: 1758 { 1759 uint32_t dest_size = (uint32_t)x7; 1760 1761 NOTICE("MBOX: %s, %d: x7 0x%x, dest_size 0x%x\n", 1762 __func__, __LINE__, (uint32_t)x7, dest_size); 1763 1764 status = intel_fcs_ecdh_request_finalize(smc_fid, x1, x2, x3, 1765 x4, x5, x6, (uint32_t *) &dest_size, 1766 &mbox_error); 1767 SMC_RET1(handle, status); 1768 } 1769 1770 case ALTERA_SIP_SMC_ASYNC_MCTP_MSG: 1771 { 1772 uint32_t *src_addr = (uint32_t *)x2; 1773 uint32_t src_size = (uint32_t)x3; 1774 uint32_t *dst_addr = (uint32_t *)x4; 1775 1776 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1777 GET_JOB_ID(x1), 1778 MBOX_CMD_MCTP_MSG, 1779 src_addr, 1780 src_size / MBOX_WORD_BYTE, 1781 MBOX_CMD_FLAG_CASUAL, 1782 sip_smc_ret_nbytes_cb, 1783 dst_addr, 1784 2); 1785 1786 SMC_RET1(handle, status); 1787 } 1788 1789 case ALTERA_SIP_SMC_ASYNC_FCS_HKDF_REQUEST: 1790 { 1791 status = intel_fcs_hkdf_request(smc_fid, x1, x2, x3, x4, x5, x6, 1792 x7); 1793 SMC_RET1(handle, status); 1794 } 1795 1796 default: 1797 return socfpga_sip_handler(smc_fid, x1, x2, x3, x4, 1798 cookie, handle, flags); 1799 } /* switch (smc_fid) */ 1800 } 1801 #endif 1802 1803 /* 1804 * This function is responsible for handling all SiP calls from the NS world 1805 */ 1806 1807 uintptr_t sip_smc_handler_v1(uint32_t smc_fid, 1808 u_register_t x1, 1809 u_register_t x2, 1810 u_register_t x3, 1811 u_register_t x4, 1812 void *cookie, 1813 void *handle, 1814 u_register_t flags) 1815 { 1816 uint32_t retval = 0, completed_addr[3]; 1817 uint32_t retval2 = 0; 1818 uint32_t mbox_error = 0; 1819 uint32_t err_states = 0; 1820 uint64_t retval64, rsu_respbuf[9]; 1821 uint32_t seu_respbuf[3]; 1822 int status = INTEL_SIP_SMC_STATUS_OK; 1823 int mbox_status; 1824 unsigned int len_in_resp; 1825 u_register_t x5, x6, x7; 1826 1827 switch (smc_fid) { 1828 case SIP_SVC_UID: 1829 /* Return UID to the caller */ 1830 SMC_UUID_RET(handle, intl_svc_uid); 1831 1832 case INTEL_SIP_SMC_FPGA_CONFIG_ISDONE: 1833 status = intel_mailbox_fpga_config_isdone(&err_states); 1834 SMC_RET4(handle, status, err_states, 0, 0); 1835 1836 case INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM: 1837 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 1838 INTEL_SIP_SMC_FPGA_CONFIG_ADDR, 1839 INTEL_SIP_SMC_FPGA_CONFIG_SIZE - 1840 INTEL_SIP_SMC_FPGA_CONFIG_ADDR); 1841 1842 case INTEL_SIP_SMC_FPGA_CONFIG_START: 1843 status = intel_fpga_config_start(x1); 1844 SMC_RET4(handle, status, 0, 0, 0); 1845 1846 case INTEL_SIP_SMC_FPGA_CONFIG_WRITE: 1847 status = intel_fpga_config_write(x1, x2); 1848 SMC_RET4(handle, status, 0, 0, 0); 1849 1850 case INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE: 1851 status = intel_fpga_config_completed_write(completed_addr, 1852 &retval, &rcv_id); 1853 switch (retval) { 1854 case 1: 1855 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 1856 completed_addr[0], 0, 0); 1857 1858 case 2: 1859 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 1860 completed_addr[0], 1861 completed_addr[1], 0); 1862 1863 case 3: 1864 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 1865 completed_addr[0], 1866 completed_addr[1], 1867 completed_addr[2]); 1868 1869 case 0: 1870 SMC_RET4(handle, status, 0, 0, 0); 1871 1872 default: 1873 mailbox_clear_response(); 1874 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR); 1875 } 1876 1877 case INTEL_SIP_SMC_REG_READ: 1878 status = intel_secure_reg_read(x1, &retval); 1879 SMC_RET3(handle, status, retval, x1); 1880 1881 case INTEL_SIP_SMC_REG_WRITE: 1882 status = intel_secure_reg_write(x1, (uint32_t)x2, &retval); 1883 SMC_RET3(handle, status, retval, x1); 1884 1885 case INTEL_SIP_SMC_REG_UPDATE: 1886 status = intel_secure_reg_update(x1, (uint32_t)x2, 1887 (uint32_t)x3, &retval); 1888 SMC_RET3(handle, status, retval, x1); 1889 1890 case INTEL_SIP_SMC_RSU_STATUS: 1891 status = intel_rsu_status(rsu_respbuf, 1892 ARRAY_SIZE(rsu_respbuf)); 1893 if (status) { 1894 SMC_RET1(handle, status); 1895 } else { 1896 SMC_RET4(handle, rsu_respbuf[0], rsu_respbuf[1], 1897 rsu_respbuf[2], rsu_respbuf[3]); 1898 } 1899 1900 case INTEL_SIP_SMC_RSU_UPDATE: 1901 status = intel_rsu_update(x1); 1902 SMC_RET1(handle, status); 1903 1904 case INTEL_SIP_SMC_RSU_NOTIFY: 1905 status = intel_rsu_notify(x1); 1906 SMC_RET1(handle, status); 1907 1908 case INTEL_SIP_SMC_RSU_RETRY_COUNTER: 1909 status = intel_rsu_retry_counter((uint32_t *)rsu_respbuf, 1910 ARRAY_SIZE(rsu_respbuf), &retval); 1911 if (status) { 1912 SMC_RET1(handle, status); 1913 } else { 1914 SMC_RET2(handle, status, retval); 1915 } 1916 1917 case INTEL_SIP_SMC_RSU_DCMF_VERSION: 1918 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 1919 ((uint64_t)rsu_dcmf_ver[1] << 32) | rsu_dcmf_ver[0], 1920 ((uint64_t)rsu_dcmf_ver[3] << 32) | rsu_dcmf_ver[2]); 1921 1922 case INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION: 1923 status = intel_rsu_copy_dcmf_version(x1, x2); 1924 SMC_RET1(handle, status); 1925 1926 case INTEL_SIP_SMC_RSU_GET_DEVICE_INFO: 1927 status = intel_rsu_get_device_info((uint32_t *)rsu_respbuf, 1928 ARRAY_SIZE(rsu_respbuf)); 1929 if (status) { 1930 SMC_RET1(handle, status); 1931 } else { 1932 SMC_RET5(handle, status, rsu_respbuf[0], rsu_respbuf[1], 1933 rsu_respbuf[2], rsu_respbuf[3]); 1934 } 1935 1936 case INTEL_SIP_SMC_RSU_DCMF_STATUS: 1937 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, 1938 ((uint64_t)rsu_dcmf_stat[3] << 48) | 1939 ((uint64_t)rsu_dcmf_stat[2] << 32) | 1940 ((uint64_t)rsu_dcmf_stat[1] << 16) | 1941 rsu_dcmf_stat[0]); 1942 1943 case INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS: 1944 status = intel_rsu_copy_dcmf_status(x1); 1945 SMC_RET1(handle, status); 1946 1947 case INTEL_SIP_SMC_RSU_MAX_RETRY: 1948 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, rsu_max_retry); 1949 1950 case INTEL_SIP_SMC_RSU_COPY_MAX_RETRY: 1951 rsu_max_retry = x1; 1952 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_OK); 1953 1954 case INTEL_SIP_SMC_ECC_DBE: 1955 status = intel_ecc_dbe_notification(x1); 1956 SMC_RET1(handle, status); 1957 1958 case INTEL_SIP_SMC_SERVICE_COMPLETED: 1959 status = intel_smc_service_completed(x1, x2, x3, &rcv_id, 1960 &len_in_resp, &mbox_error); 1961 SMC_RET4(handle, status, mbox_error, x1, len_in_resp); 1962 1963 case INTEL_SIP_SMC_FIRMWARE_VERSION: 1964 status = intel_smc_fw_version(&retval); 1965 SMC_RET2(handle, status, retval); 1966 1967 case INTEL_SIP_SMC_MBOX_SEND_CMD: 1968 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1969 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1970 status = intel_mbox_send_cmd(x1, (uint32_t *)x2, x3, x4, x5, x6, 1971 &mbox_status, &len_in_resp); 1972 SMC_RET3(handle, status, mbox_status, len_in_resp); 1973 1974 case INTEL_SIP_SMC_GET_USERCODE: 1975 status = intel_smc_get_usercode(&retval); 1976 SMC_RET2(handle, status, retval); 1977 1978 case INTEL_SIP_SMC_FCS_CRYPTION: 1979 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1980 1981 if (x1 == FCS_MODE_DECRYPT) { 1982 status = intel_fcs_decryption(x2, x3, x4, x5, &send_id); 1983 } else if (x1 == FCS_MODE_ENCRYPT) { 1984 status = intel_fcs_encryption(x2, x3, x4, x5, &send_id); 1985 } else { 1986 status = INTEL_SIP_SMC_STATUS_REJECTED; 1987 } 1988 1989 SMC_RET3(handle, status, x4, x5); 1990 1991 case INTEL_SIP_SMC_FCS_CRYPTION_EXT: 1992 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1993 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1994 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1995 1996 if (x3 == FCS_MODE_DECRYPT) { 1997 status = intel_fcs_decryption_ext(smc_fid, 0, x1, x2, x4, x5, x6, 1998 (uint32_t *) &x7, &mbox_error, 0, 0, 0); 1999 } else if (x3 == FCS_MODE_ENCRYPT) { 2000 status = intel_fcs_encryption_ext(smc_fid, 0, x1, x2, x4, x5, x6, 2001 (uint32_t *) &x7, &mbox_error, 0, 0); 2002 } else { 2003 status = INTEL_SIP_SMC_STATUS_REJECTED; 2004 } 2005 2006 SMC_RET4(handle, status, mbox_error, x6, x7); 2007 2008 case INTEL_SIP_SMC_FCS_RANDOM_NUMBER: 2009 status = intel_fcs_random_number_gen(x1, &retval64, 2010 &mbox_error); 2011 SMC_RET4(handle, status, mbox_error, x1, retval64); 2012 2013 case INTEL_SIP_SMC_FCS_RANDOM_NUMBER_EXT: 2014 status = intel_fcs_random_number_gen_ext(x1, x2, x3, 2015 &send_id); 2016 SMC_RET1(handle, status); 2017 2018 case INTEL_SIP_SMC_FCS_SEND_CERTIFICATE: 2019 status = intel_fcs_send_cert(smc_fid, 0, x1, x2, &send_id); 2020 SMC_RET1(handle, status); 2021 2022 case INTEL_SIP_SMC_FCS_GET_PROVISION_DATA: 2023 status = intel_fcs_get_provision_data(&send_id); 2024 SMC_RET1(handle, status); 2025 2026 case INTEL_SIP_SMC_FCS_CNTR_SET_PREAUTH: 2027 status = intel_fcs_cntr_set_preauth(smc_fid, 0, x1, x2, x3, 2028 &mbox_error); 2029 SMC_RET2(handle, status, mbox_error); 2030 2031 case INTEL_SIP_SMC_HPS_SET_BRIDGES: 2032 status = intel_hps_set_bridges(x1, x2); 2033 SMC_RET1(handle, status); 2034 2035 case INTEL_SIP_SMC_HWMON_READTEMP: 2036 status = intel_hwmon_readtemp(x1, &retval); 2037 SMC_RET2(handle, status, retval); 2038 2039 case INTEL_SIP_SMC_HWMON_READVOLT: 2040 status = intel_hwmon_readvolt(x1, &retval); 2041 SMC_RET2(handle, status, retval); 2042 2043 case INTEL_SIP_SMC_FCS_PSGSIGMA_TEARDOWN: 2044 status = intel_fcs_sigma_teardown(x1, &mbox_error); 2045 SMC_RET2(handle, status, mbox_error); 2046 2047 case INTEL_SIP_SMC_FCS_CHIP_ID: 2048 status = intel_fcs_chip_id(&retval, &retval2, &mbox_error); 2049 SMC_RET4(handle, status, mbox_error, retval, retval2); 2050 2051 case INTEL_SIP_SMC_FCS_ATTESTATION_SUBKEY: 2052 status = intel_fcs_attestation_subkey(x1, x2, x3, 2053 (uint32_t *) &x4, &mbox_error); 2054 SMC_RET4(handle, status, mbox_error, x3, x4); 2055 2056 case INTEL_SIP_SMC_FCS_ATTESTATION_MEASUREMENTS: 2057 status = intel_fcs_get_measurement(x1, x2, x3, 2058 (uint32_t *) &x4, &mbox_error); 2059 SMC_RET4(handle, status, mbox_error, x3, x4); 2060 2061 case INTEL_SIP_SMC_FCS_GET_ATTESTATION_CERT: 2062 status = intel_fcs_get_attestation_cert(smc_fid, 0, x1, x2, 2063 (uint32_t *) &x3, &mbox_error); 2064 SMC_RET4(handle, status, mbox_error, x2, x3); 2065 2066 case INTEL_SIP_SMC_FCS_CREATE_CERT_ON_RELOAD: 2067 status = intel_fcs_create_cert_on_reload(smc_fid, 0, x1, &mbox_error); 2068 SMC_RET2(handle, status, mbox_error); 2069 2070 case INTEL_SIP_SMC_FCS_OPEN_CS_SESSION: 2071 status = intel_fcs_open_crypto_service_session(&retval, &mbox_error); 2072 SMC_RET3(handle, status, mbox_error, retval); 2073 2074 case INTEL_SIP_SMC_FCS_CLOSE_CS_SESSION: 2075 status = intel_fcs_close_crypto_service_session(x1, &mbox_error); 2076 SMC_RET2(handle, status, mbox_error); 2077 2078 case INTEL_SIP_SMC_FCS_IMPORT_CS_KEY: 2079 status = intel_fcs_import_crypto_service_key(x1, x2, &send_id); 2080 SMC_RET1(handle, status); 2081 2082 case INTEL_SIP_SMC_FCS_EXPORT_CS_KEY: 2083 status = intel_fcs_export_crypto_service_key(x1, x2, x3, 2084 (uint32_t *) &x4, &mbox_error); 2085 SMC_RET4(handle, status, mbox_error, x3, x4); 2086 2087 case INTEL_SIP_SMC_FCS_REMOVE_CS_KEY: 2088 status = intel_fcs_remove_crypto_service_key(x1, x2, 2089 &mbox_error); 2090 SMC_RET2(handle, status, mbox_error); 2091 2092 case INTEL_SIP_SMC_FCS_GET_CS_KEY_INFO: 2093 status = intel_fcs_get_crypto_service_key_info(x1, x2, x3, 2094 (uint32_t *) &x4, &mbox_error); 2095 SMC_RET4(handle, status, mbox_error, x3, x4); 2096 2097 case INTEL_SIP_SMC_FCS_GET_DIGEST_INIT: 2098 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2099 status = intel_fcs_get_digest_init(x1, x2, x3, 2100 x4, x5, &mbox_error); 2101 SMC_RET2(handle, status, mbox_error); 2102 2103 case INTEL_SIP_SMC_FCS_GET_DIGEST_UPDATE: 2104 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2105 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2106 status = intel_fcs_get_digest_update_finalize(smc_fid, 0, x1, x2, 2107 x3, x4, x5, (uint32_t *) &x6, false, 2108 &mbox_error, 0); 2109 SMC_RET4(handle, status, mbox_error, x5, x6); 2110 2111 case INTEL_SIP_SMC_FCS_GET_DIGEST_FINALIZE: 2112 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2113 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2114 status = intel_fcs_get_digest_update_finalize(smc_fid, 0, x1, x2, 2115 x3, x4, x5, (uint32_t *) &x6, true, 2116 &mbox_error, 0); 2117 SMC_RET4(handle, status, mbox_error, x5, x6); 2118 2119 case INTEL_SIP_SMC_FCS_GET_DIGEST_SMMU_UPDATE: 2120 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2121 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2122 status = intel_fcs_get_digest_smmu_update_finalize(x1, x2, x3, 2123 x4, x5, (uint32_t *) &x6, false, 2124 &mbox_error, &send_id); 2125 SMC_RET4(handle, status, mbox_error, x5, x6); 2126 2127 case INTEL_SIP_SMC_FCS_GET_DIGEST_SMMU_FINALIZE: 2128 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2129 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2130 status = intel_fcs_get_digest_smmu_update_finalize(x1, x2, x3, 2131 x4, x5, (uint32_t *) &x6, true, 2132 &mbox_error, &send_id); 2133 SMC_RET4(handle, status, mbox_error, x5, x6); 2134 2135 case INTEL_SIP_SMC_FCS_MAC_VERIFY_INIT: 2136 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2137 status = intel_fcs_mac_verify_init(x1, x2, x3, 2138 x4, x5, &mbox_error); 2139 SMC_RET2(handle, status, mbox_error); 2140 2141 case INTEL_SIP_SMC_FCS_MAC_VERIFY_UPDATE: 2142 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2143 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2144 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2145 status = intel_fcs_mac_verify_update_finalize(smc_fid, 0, x1, x2, 2146 x3, x4, x5, (uint32_t *) &x6, x7, false, 2147 &mbox_error, 0); 2148 SMC_RET4(handle, status, mbox_error, x5, x6); 2149 2150 case INTEL_SIP_SMC_FCS_MAC_VERIFY_FINALIZE: 2151 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2152 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2153 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2154 status = intel_fcs_mac_verify_update_finalize(smc_fid, 0, x1, x2, 2155 x3, x4, x5, (uint32_t *) &x6, x7, true, 2156 &mbox_error, 0); 2157 SMC_RET4(handle, status, mbox_error, x5, x6); 2158 2159 case INTEL_SIP_SMC_FCS_MAC_VERIFY_SMMU_UPDATE: 2160 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2161 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2162 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2163 status = intel_fcs_mac_verify_smmu_update_finalize(x1, x2, x3, 2164 x4, x5, (uint32_t *) &x6, x7, 2165 false, &mbox_error, &send_id); 2166 SMC_RET4(handle, status, mbox_error, x5, x6); 2167 2168 case INTEL_SIP_SMC_FCS_MAC_VERIFY_SMMU_FINALIZE: 2169 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2170 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2171 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2172 status = intel_fcs_mac_verify_smmu_update_finalize(x1, x2, x3, 2173 x4, x5, (uint32_t *) &x6, x7, 2174 true, &mbox_error, &send_id); 2175 SMC_RET4(handle, status, mbox_error, x5, x6); 2176 2177 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_INIT: 2178 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2179 status = intel_fcs_ecdsa_sha2_data_sign_init(x1, x2, x3, 2180 x4, x5, &mbox_error); 2181 SMC_RET2(handle, status, mbox_error); 2182 2183 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_UPDATE: 2184 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2185 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2186 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(smc_fid, 2187 0, x1, x2, x3, x4, x5, (uint32_t *) &x6, 2188 false, &mbox_error, 0); 2189 SMC_RET4(handle, status, mbox_error, x5, x6); 2190 2191 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE: 2192 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2193 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2194 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(smc_fid, 2195 0, x1, x2, x3, x4, x5, (uint32_t *) &x6, 2196 true, &mbox_error, 0); 2197 SMC_RET4(handle, status, mbox_error, x5, x6); 2198 2199 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_UPDATE: 2200 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2201 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2202 status = intel_fcs_ecdsa_sha2_data_sign_smmu_update_finalize(x1, 2203 x2, x3, x4, x5, (uint32_t *) &x6, false, 2204 &mbox_error, &send_id); 2205 SMC_RET4(handle, status, mbox_error, x5, x6); 2206 2207 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_FINALIZE: 2208 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2209 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2210 status = intel_fcs_ecdsa_sha2_data_sign_smmu_update_finalize(x1, 2211 x2, x3, x4, x5, (uint32_t *) &x6, true, 2212 &mbox_error, &send_id); 2213 SMC_RET4(handle, status, mbox_error, x5, x6); 2214 2215 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_INIT: 2216 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2217 status = intel_fcs_ecdsa_hash_sign_init(x1, x2, x3, 2218 x4, x5, &mbox_error); 2219 SMC_RET2(handle, status, mbox_error); 2220 2221 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_FINALIZE: 2222 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2223 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2224 status = intel_fcs_ecdsa_hash_sign_finalize(smc_fid, 0, x1, x2, 2225 x3, x4, x5, (uint32_t *) &x6, 2226 &mbox_error); 2227 SMC_RET4(handle, status, mbox_error, x5, x6); 2228 2229 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_INIT: 2230 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2231 status = intel_fcs_ecdsa_hash_sig_verify_init(x1, x2, x3, 2232 x4, x5, &mbox_error); 2233 SMC_RET2(handle, status, mbox_error); 2234 2235 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_FINALIZE: 2236 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2237 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2238 status = intel_fcs_ecdsa_hash_sig_verify_finalize(smc_fid, 0, x1, 2239 x2, x3, x4, x5, (uint32_t *) &x6, 2240 &mbox_error); 2241 SMC_RET4(handle, status, mbox_error, x5, x6); 2242 2243 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_INIT: 2244 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2245 status = intel_fcs_ecdsa_sha2_data_sig_verify_init(x1, x2, x3, 2246 x4, x5, &mbox_error); 2247 SMC_RET2(handle, status, mbox_error); 2248 2249 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_UPDATE: 2250 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2251 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2252 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2253 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize( 2254 smc_fid, 0, x1, x2, x3, x4, x5, 2255 (uint32_t *) &x6, x7, false, 2256 &mbox_error, 0); 2257 SMC_RET4(handle, status, mbox_error, x5, x6); 2258 2259 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_UPDATE: 2260 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2261 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2262 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2263 status = intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize( 2264 x1, x2, x3, x4, x5, (uint32_t *) &x6, 2265 x7, false, &mbox_error, &send_id); 2266 SMC_RET4(handle, status, mbox_error, x5, x6); 2267 2268 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_FINALIZE: 2269 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2270 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2271 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2272 status = intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize( 2273 x1, x2, x3, x4, x5, (uint32_t *) &x6, 2274 x7, true, &mbox_error, &send_id); 2275 SMC_RET4(handle, status, mbox_error, x5, x6); 2276 2277 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE: 2278 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2279 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2280 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2281 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize( 2282 smc_fid, 0, x1, x2, x3, x4, x5, 2283 (uint32_t *) &x6, x7, true, 2284 &mbox_error, 0); 2285 SMC_RET4(handle, status, mbox_error, x5, x6); 2286 2287 case INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_INIT: 2288 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2289 status = intel_fcs_ecdsa_get_pubkey_init(x1, x2, x3, 2290 x4, x5, &mbox_error); 2291 SMC_RET2(handle, status, mbox_error); 2292 2293 case INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_FINALIZE: 2294 status = intel_fcs_ecdsa_get_pubkey_finalize( 2295 INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_FINALIZE, 0, 2296 x1, x2, x3, (uint32_t *) &x4, &mbox_error); 2297 SMC_RET4(handle, status, mbox_error, x3, x4); 2298 2299 case INTEL_SIP_SMC_FCS_ECDH_REQUEST_INIT: 2300 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2301 status = intel_fcs_ecdh_request_init(x1, x2, x3, 2302 x4, x5, &mbox_error); 2303 SMC_RET2(handle, status, mbox_error); 2304 2305 case INTEL_SIP_SMC_FCS_ECDH_REQUEST_FINALIZE: 2306 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2307 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2308 status = intel_fcs_ecdh_request_finalize(smc_fid, 0, x1, x2, x3, 2309 x4, x5, (uint32_t *) &x6, &mbox_error); 2310 SMC_RET4(handle, status, mbox_error, x5, x6); 2311 2312 case INTEL_SIP_SMC_FCS_AES_CRYPT_INIT: 2313 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2314 status = intel_fcs_aes_crypt_init(x1, x2, x3, x4, x5, 2315 &mbox_error); 2316 SMC_RET2(handle, status, mbox_error); 2317 2318 case INTEL_SIP_SMC_FCS_AES_CRYPT_UPDATE: 2319 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2320 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2321 status = intel_fcs_aes_crypt_update_finalize(smc_fid, 0, x1, x2, 2322 x3, x4, x5, x6, 0, false, &send_id, 0, 0); 2323 SMC_RET1(handle, status); 2324 2325 case INTEL_SIP_SMC_FCS_AES_CRYPT_FINALIZE: 2326 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2327 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2328 status = intel_fcs_aes_crypt_update_finalize(smc_fid, 0, x1, x2, 2329 x3, x4, x5, x6, 0, true, &send_id, 0, 0); 2330 SMC_RET1(handle, status); 2331 2332 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 2333 case INTEL_SIP_SMC_FCS_SDM_REMAPPER_CONFIG: 2334 status = intel_smmu_hps_remapper_config(x1); 2335 SMC_RET1(handle, status); 2336 #endif 2337 2338 case INTEL_SIP_SMC_GET_ROM_PATCH_SHA384: 2339 status = intel_fcs_get_rom_patch_sha384(x1, &retval64, 2340 &mbox_error); 2341 SMC_RET4(handle, status, mbox_error, x1, retval64); 2342 2343 case INTEL_SIP_SMC_SVC_VERSION: 2344 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 2345 SIP_SVC_VERSION_MAJOR, 2346 SIP_SVC_VERSION_MINOR); 2347 2348 case INTEL_SIP_SMC_SEU_ERR_STATUS: 2349 status = intel_sdm_seu_err_read(seu_respbuf, 2350 ARRAY_SIZE(seu_respbuf)); 2351 if (status) { 2352 SMC_RET1(handle, status); 2353 } else { 2354 SMC_RET3(handle, seu_respbuf[0], seu_respbuf[1], seu_respbuf[2]); 2355 } 2356 2357 case INTEL_SIP_SMC_SAFE_INJECT_SEU_ERR: 2358 status = intel_sdm_safe_inject_seu_err((uint32_t *)&x1, (uint32_t)x2); 2359 SMC_RET1(handle, status); 2360 2361 case INTEL_SIP_SMC_ATF_BUILD_VER: 2362 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, VERSION_MAJOR, 2363 VERSION_MINOR, VERSION_PATCH); 2364 2365 default: 2366 return socfpga_sip_handler(smc_fid, x1, x2, x3, x4, 2367 cookie, handle, flags); 2368 } 2369 } 2370 2371 uintptr_t sip_smc_handler(uint32_t smc_fid, 2372 u_register_t x1, 2373 u_register_t x2, 2374 u_register_t x3, 2375 u_register_t x4, 2376 void *cookie, 2377 void *handle, 2378 u_register_t flags) 2379 { 2380 uint32_t cmd = smc_fid & INTEL_SIP_SMC_CMD_MASK; 2381 2382 if (cmd >= INTEL_SIP_SMC_CMD_V2_RANGE_BEGIN && 2383 cmd <= INTEL_SIP_SMC_CMD_V2_RANGE_END) { 2384 return sip_smc_handler_v2(smc_fid, x1, x2, x3, x4, 2385 cookie, handle, flags); 2386 } 2387 #if SIP_SVC_V3 2388 else if ((cmd >= INTEL_SIP_SMC_CMD_V3_RANGE_BEGIN) && 2389 (cmd <= INTEL_SIP_SMC_CMD_V3_RANGE_END)) { 2390 uintptr_t ret = sip_smc_handler_v3(smc_fid, x1, x2, x3, x4, 2391 cookie, handle, flags); 2392 return ret; 2393 } 2394 #endif 2395 else { 2396 return sip_smc_handler_v1(smc_fid, x1, x2, x3, x4, 2397 cookie, handle, flags); 2398 } 2399 } 2400 2401 DECLARE_RT_SVC( 2402 socfpga_sip_svc, 2403 OEN_SIP_START, 2404 OEN_SIP_END, 2405 SMC_TYPE_FAST, 2406 NULL, 2407 sip_smc_handler 2408 ); 2409 2410 DECLARE_RT_SVC( 2411 socfpga_sip_svc_std, 2412 OEN_SIP_START, 2413 OEN_SIP_END, 2414 SMC_TYPE_YIELD, 2415 NULL, 2416 sip_smc_handler 2417 ); 2418