| 45b52c20 | 02-Aug-2017 |
Eleanor Bonnici <Eleanor.bonnici@arm.com> |
Cortex-A57: Implement workaround for erratum 859972
Erratum 855972 applies to revision r1p3 or earlier Cortex-A57 CPUs. The
recommended workaround is to disable instruction prefetch.
Change-Id: I56
Cortex-A57: Implement workaround for erratum 859972
Erratum 855972 applies to revision r1p3 or earlier Cortex-A57 CPUs. The
recommended workaround is to disable instruction prefetch.
Change-Id: I56eeac0b753eb1432bd940083372ad6f7e93b16a
Signed-off-by: Eleanor Bonnici <Eleanor.bonnici@arm.com>
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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| 413115e1 | 06-Sep-2017 |
davidcunado-arm <david.cunado@arm.com> |
Merge pull request #1019 from etienne-lms/log-size
CPU_DATA_LOG2SIZE depends on cache line size |
| 216e58a3 | 04-Sep-2017 |
Roberto Vargas <roberto.vargas@arm.com> |
Reduce time lock in psci_do_cpu_off
psci_set_power_off_state only initializes a local variable, so there
isn't any reason why it should be done while the lock is held.
Change-Id: I1c62f4cd5d860d102
Reduce time lock in psci_do_cpu_off
psci_set_power_off_state only initializes a local variable, so there
isn't any reason why it should be done while the lock is held.
Change-Id: I1c62f4cd5d860d102532e5a5350152180d41d127
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
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| 86606eb5 | 01-Sep-2017 |
Etienne Carriere <etienne.carriere@linaro.org> |
cpu log buffer size depends on cache line size
Platform may use specific cache line sizes. Since CACHE_WRITEBACK_GRANULE
defines the platform specific cache line size, it is used to define the
size
cpu log buffer size depends on cache line size
Platform may use specific cache line sizes. Since CACHE_WRITEBACK_GRANULE
defines the platform specific cache line size, it is used to define the
size of the cpu data structure CPU_DATA_SIZE aligned on cache line size.
Introduce assembly macro 'mov_imm' for AArch32 to simplify implementation
of function '_cpu_data_by_index'.
Change-Id: Ic2d49ffe0c3e51649425fd9c8c99559c582ac5a1
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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| b15bab6b | 30-Aug-2017 |
danh-arm <dan.handley@arm.com> |
Merge pull request #1066 from islmit01/im/enable_cnp_bit
Enable CnP bit for ARMv8.2 CPUs |
| 80bcf981 | 09-Aug-2017 |
Eleanor Bonnici <Eleanor.bonnici@arm.com> |
CPU: Correct names of implementation-defined aux regs
At present, various CPU register macros that refer to CPUACTLR are named
ACTLR. This patch fixes that.
The previous register names are retained
CPU: Correct names of implementation-defined aux regs
At present, various CPU register macros that refer to CPUACTLR are named
ACTLR. This patch fixes that.
The previous register names are retained, but guarded by the
ERROR_DEPRECATED macro, so as not to break platforms that continue using
the old names.
Change-Id: Ia872196d81803f8f390b887d149e0fd054df519b
Signed-off-by: Eleanor Bonnici <Eleanor.bonnici@arm.com>
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| 01ebe3d2 | 25-Aug-2017 |
davidcunado-arm <david.cunado@arm.com> |
Merge pull request #1059 from kenkuang/intergration
fix a typo abort sctlr_el2 |
| 9fce2725 | 07-Aug-2017 |
Isla Mitchell <isla.mitchell@arm.com> |
Enable CnP bit for ARMv8.2 CPUs
This patch enables the CnP (Common not Private) bit for secure page
tables so that multiple PEs in the same Inner Shareable domain can use
the same translation table
Enable CnP bit for ARMv8.2 CPUs
This patch enables the CnP (Common not Private) bit for secure page
tables so that multiple PEs in the same Inner Shareable domain can use
the same translation table entries for a given stage of translation in
a particular translation regime. This only takes effect when ARM
Trusted Firmware is built with ARM_ARCH_MINOR >= 2.
ARM Trusted Firmware Design has been updated to include a description
of this feature usage.
Change-Id: I698305f047400119aa1900d34c65368022e410b8
Signed-off-by: Isla Mitchell <isla.mitchell@arm.com>
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| f45e232a | 16-Aug-2017 |
Jeenu Viswambharan <jeenu.viswambharan@arm.com> |
Add macro to test for minimum architecture version
The macro concisely expresses and requires architecture version to be at
least as required by its arguments. This would be useful when extending
Tr
Add macro to test for minimum architecture version
The macro concisely expresses and requires architecture version to be at
least as required by its arguments. This would be useful when extending
Trusted Firmware functionality for future architecture revisions.
Replace similar usage in the current code base with the new macro.
Change-Id: I9dcd0aa71a663eabd02ed9632b8ce87611fa5a57
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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| 5722b78c | 23-Aug-2017 |
Alistair Francis <alistair.francis@xilinx.com> |
psci_common: Resolve GCC static analysis false positive
Previously commit 555ebb34db8f3424c1b394df2f10ecf9c1f70901 attmpted to fix this
GCC issue:
services/std_svc/psci/psci_common.c: In function '
psci_common: Resolve GCC static analysis false positive
Previously commit 555ebb34db8f3424c1b394df2f10ecf9c1f70901 attmpted to fix this
GCC issue:
services/std_svc/psci/psci_common.c: In function 'psci_do_state_coordination':
services/std_svc/psci/psci_common.c:220:27: error: array subscript is above
array bounds [-Werror=array-bounds]
psci_req_local_pwr_states[pwrlvl - 1][cpu_idx] = req_pwr_state;
This fix doesn't work as asserts aren't built in non-debug build flows.
Let's use GCCs #pragma option (documented here:
https://gcc.gnu.org/onlinedocs/gcc/Diagnostic-Pragmas.html) to avoid
this false positive instead.
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
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| 2e09d4f8 | 23-Aug-2017 |
Ken Kuang <ken.kuang@spreadtrum.com> |
fix a typo about sctlr_el2
which will cause write_sctlr_el2 use all sctlr_el1 value except the EE bit
The code doesn't "Use SCTLR_EL1.EE value to initialise sctlr_el2"
but, read out SCTLR_EL1 and cl
fix a typo about sctlr_el2
which will cause write_sctlr_el2 use all sctlr_el1 value except the EE bit
The code doesn't "Use SCTLR_EL1.EE value to initialise sctlr_el2"
but, read out SCTLR_EL1 and clear EE bit, then set to sctlr_el2
Signed-off-by: Ken Kuang <ken.kuang@spreadtrum.com>
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| 54661cd2 | 24-Apr-2017 |
Summer Qin <summer.qin@arm.com> |
Add Trusted OS extra image parsing support for ARM standard platforms
Trusted OS may have extra images to be loaded. Load them one by one
and do the parsing. In this patch, ARM TF need to load up to
Add Trusted OS extra image parsing support for ARM standard platforms
Trusted OS may have extra images to be loaded. Load them one by one
and do the parsing. In this patch, ARM TF need to load up to 3 images
for optee os: header, pager and paged images. Header image is the info
about optee os and images. Pager image include pager code and data.
Paged image include the paging parts using virtual memory.
Change-Id: Ia3bcfa6d8a3ed7850deb5729654daca7b00be394
Signed-off-by: Summer Qin <summer.qin@arm.com>
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| 3e0cba52 | 01-Aug-2017 |
davidcunado-arm <david.cunado@arm.com> |
Merge pull request #1021 from vwadekar/psci-early-suspend-handler
lib: psci: early suspend handler for platforms |
| 235581cf | 01-Aug-2017 |
davidcunado-arm <david.cunado@arm.com> |
Merge pull request #1045 from sandrine-bailleux-arm/sb/xlat-lib-ctx
Fix sign of variable in xlat_tables_print() |
| 664e6931 | 01-Aug-2017 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
xlat lib v2: Fix sign of debug loop variable
This patch changes the sign of the loop variable used in
xlat_tables_print(). It needs to be unsigned because it is compared
against another unsigned int
xlat lib v2: Fix sign of debug loop variable
This patch changes the sign of the loop variable used in
xlat_tables_print(). It needs to be unsigned because it is compared
against another unsigned int.
Change-Id: I2b3cee7990dd75e8ebd2701de3860ead7cad8dc8
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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|
| 1862d620 | 10-Jul-2017 |
Varun Wadekar <vwadekar@nvidia.com> |
lib: psci: early suspend handler for platforms
This patch adds an early suspend handler, that executes with
SMP and data cache enabled. This handler allows platforms to
perform any early actions dur
lib: psci: early suspend handler for platforms
This patch adds an early suspend handler, that executes with
SMP and data cache enabled. This handler allows platforms to
perform any early actions during the CPU suspend entry sequence.
This handler is optional and platforms can choose to implement it
depending on their needs. The `pwr_domain_suspend` handler still
exists and platforms can keep on using it without any side effects.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| ddc5bfdb | 31-Jul-2017 |
davidcunado-arm <david.cunado@arm.com> |
Merge pull request #1035 from sandrine-bailleux-arm/sb/xlat-lib-ctx
Translation table library v2 improvements |
| d9f18155 | 31-Jul-2017 |
davidcunado-arm <david.cunado@arm.com> |
Merge pull request #1033 from davidcunado-arm/dc/psci_flush
Address edge case for stale PSCI CPU data in cache |
| 881cf374 | 26-Jul-2017 |
davidcunado-arm <david.cunado@arm.com> |
Merge pull request #1031 from robertovargas-arm/assert_format
Use standard UNIX file:line format in assert |
| 71341d23 | 19-Jul-2017 |
David Cunado <david.cunado@arm.com> |
Address edge case for stale PSCI CPU data in cache
There is a theoretical edge case during CPU_ON where the cache
may contain stale data for the target CPU data - this can occur
under the following
Address edge case for stale PSCI CPU data in cache
There is a theoretical edge case during CPU_ON where the cache
may contain stale data for the target CPU data - this can occur
under the following conditions:
- the target CPU is in another cluster from the current
- the target CPU was the last CPU to shutdown on its cluster
- the cluster was removed from coherency as part of the CPU shutdown
In this case the cache maintenace that was performed as part of the
target CPUs shutdown was not seen by the current CPU's cluster. And
so the cache may contain stale data for the target CPU.
This patch adds a cache maintenance operation (flush) for the
cache-line containing the target CPU data - this ensures that the
target CPU data is read from main memory.
Change-Id: If8cfd42639b03174f60669429b7f7a757027d0fb
Signed-off-by: David Cunado <david.cunado@arm.com>
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|
| 0044231d | 19-Jul-2017 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
xlat lib: Fix some types
Fix the type length and signedness of some of the constants and
variables used in the translation table library.
This patch supersedes Pull Request #1018:
https://github.co
xlat lib: Fix some types
Fix the type length and signedness of some of the constants and
variables used in the translation table library.
This patch supersedes Pull Request #1018:
https://github.com/ARM-software/arm-trusted-firmware/pull/1018
Change-Id: Ibd45faf7a4fb428a0bf71c752551d35800212fb2
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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| 7bba6884 | 19-Jul-2017 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Import ctzdi2.c from LLVM compiler-rt
When using __builtin_ctzll() in AArch32 code, the compiler may translate
that into a call to the __ctzdi2() function. In this case, the linking
phase fails beca
Import ctzdi2.c from LLVM compiler-rt
When using __builtin_ctzll() in AArch32 code, the compiler may translate
that into a call to the __ctzdi2() function. In this case, the linking
phase fails because TF doesn't provide an implementation for it.
This patch imports the implementation of the __ctzdi2() function from
LLVM's compiler-rt project and hooks it into TF's build system. The
ctzdi2.c file is an unmodified copy from the master branch as of
July 19 2017 (SVN revision: 308480).
Change-Id: I96766a025ba28e1afc6ef6a5c4ef91d85fc8f32b
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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| 347621bb | 11-Jul-2017 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
xlat lib v2: Remove hard-coded virtual address space size
Previous patches have made it possible to specify the physical and
virtual address spaces sizes for each translation context. However,
there
xlat lib v2: Remove hard-coded virtual address space size
Previous patches have made it possible to specify the physical and
virtual address spaces sizes for each translation context. However,
there are still some places in the code where the physical (resp.
virtual) address space size is assumed to be PLAT_PHY_ADDR_SPACE_SIZE
(resp. PLAT_VIRT_ADDR_SPACE_SIZE).
This patch removes them and reads the relevant address space size
from the translation context itself instead. This information is now
passed in argument to the enable_mmu_arch() function, which needs it
to configure the TCR_ELx.T0SZ field (in AArch64) or the TTBCR.T0SZ
field (in AArch32) appropriately.
Change-Id: I20b0e68b03a143e998695d42911d9954328a06aa
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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| d83f3579 | 31-May-2017 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
xlat lib v2: Refactor the functions enabling the MMU
This patch refactors both the AArch32 and AArch64 versions of the
function enable_mmu_arch().
In both versions, the code now computes the VMSA-r
xlat lib v2: Refactor the functions enabling the MMU
This patch refactors both the AArch32 and AArch64 versions of the
function enable_mmu_arch().
In both versions, the code now computes the VMSA-related system
registers upfront then program them in one go (rather than interleaving
the 2).
In the AArch64 version, this allows to reduce the amount of code
generated by the C preprocessor and limits it to the actual differences
between EL1 and EL3.
In the AArch32 version, this patch also removes the function
enable_mmu_internal_secure() and moves its code directly inside
enable_mmu_arch(), as it was its only caller.
Change-Id: I35c09b6db4404916cbb2e2fd3fda2ad59f935954
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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| 99f60798 | 31-May-2017 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
xlat lib v2: Remove init_xlat_tables_arch() function
In both the AArch32 and AArch64 versions, this function used to check
the sanity of the PLAT_PHY_ADDR_SPACE_SIZE in regard to the
architectural m
xlat lib v2: Remove init_xlat_tables_arch() function
In both the AArch32 and AArch64 versions, this function used to check
the sanity of the PLAT_PHY_ADDR_SPACE_SIZE in regard to the
architectural maximum value. Instead, export the
xlat_arch_get_max_supported_pa() function and move the debug
assertion in AArch-agnostic code.
The AArch64 used to also precalculate the TCR.PS field value, based
on the size of the physical address space. This is now done directly
by enable_mmu_arch(), which now receives the physical address space size
in argument.
Change-Id: Ie77ea92eb06db586f28784fdb479c6e27dd1acc1
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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