1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <assert.h> 9 #include <bl_common.h> 10 #include <console.h> 11 #include <debug.h> 12 #include <desc_image_load.h> 13 #include <dw_mmc.h> 14 #include <emmc.h> 15 #include <errno.h> 16 #include <hi6220.h> 17 #include <hisi_mcu.h> 18 #include <hisi_sram_map.h> 19 #include <mmio.h> 20 #ifdef SPD_opteed 21 #include <optee_utils.h> 22 #endif 23 #include <platform.h> 24 #include <platform_def.h> /* also includes hikey_def.h and hikey_layout.h*/ 25 #include <string.h> 26 27 #include "hikey_private.h" 28 29 /* 30 * The next 2 constants identify the extents of the code & RO data region. 31 * These addresses are used by the MMU setup code and therefore they must be 32 * page-aligned. It is the responsibility of the linker script to ensure that 33 * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses. 34 */ 35 #define BL2_RO_BASE (unsigned long)(&__RO_START__) 36 #define BL2_RO_LIMIT (unsigned long)(&__RO_END__) 37 38 #define BL2_RW_BASE (BL2_RO_LIMIT) 39 40 /* 41 * The next 2 constants identify the extents of the coherent memory region. 42 * These addresses are used by the MMU setup code and therefore they must be 43 * page-aligned. It is the responsibility of the linker script to ensure that 44 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to 45 * page-aligned addresses. 46 */ 47 #define BL2_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) 48 #define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) 49 50 static meminfo_t bl2_el3_tzram_layout; 51 52 enum { 53 BOOT_MODE_RECOVERY = 0, 54 BOOT_MODE_NORMAL, 55 BOOT_MODE_MASK = 1, 56 }; 57 58 /******************************************************************************* 59 * Transfer SCP_BL2 from Trusted RAM using the SCP Download protocol. 60 * Return 0 on success, -1 otherwise. 61 ******************************************************************************/ 62 int plat_hikey_bl2_handle_scp_bl2(image_info_t *scp_bl2_image_info) 63 { 64 /* Enable MCU SRAM */ 65 hisi_mcu_enable_sram(); 66 67 /* Load MCU binary into SRAM */ 68 hisi_mcu_load_image(scp_bl2_image_info->image_base, 69 scp_bl2_image_info->image_size); 70 /* Let MCU running */ 71 hisi_mcu_start_run(); 72 73 INFO("%s: MCU PC is at 0x%x\n", 74 __func__, mmio_read_32(AO_SC_MCU_SUBSYS_STAT2)); 75 INFO("%s: AO_SC_PERIPH_CLKSTAT4 is 0x%x\n", 76 __func__, mmio_read_32(AO_SC_PERIPH_CLKSTAT4)); 77 return 0; 78 } 79 80 /******************************************************************************* 81 * Gets SPSR for BL32 entry 82 ******************************************************************************/ 83 uint32_t hikey_get_spsr_for_bl32_entry(void) 84 { 85 /* 86 * The Secure Payload Dispatcher service is responsible for 87 * setting the SPSR prior to entry into the BL3-2 image. 88 */ 89 return 0; 90 } 91 92 /******************************************************************************* 93 * Gets SPSR for BL33 entry 94 ******************************************************************************/ 95 #ifndef AARCH32 96 uint32_t hikey_get_spsr_for_bl33_entry(void) 97 { 98 unsigned int mode; 99 uint32_t spsr; 100 101 /* Figure out what mode we enter the non-secure world in */ 102 mode = EL_IMPLEMENTED(2) ? MODE_EL2 : MODE_EL1; 103 104 /* 105 * TODO: Consider the possibility of specifying the SPSR in 106 * the FIP ToC and allowing the platform to have a say as 107 * well. 108 */ 109 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 110 return spsr; 111 } 112 #else 113 uint32_t hikey_get_spsr_for_bl33_entry(void) 114 { 115 unsigned int hyp_status, mode, spsr; 116 117 hyp_status = GET_VIRT_EXT(read_id_pfr1()); 118 119 mode = (hyp_status) ? MODE32_hyp : MODE32_svc; 120 121 /* 122 * TODO: Consider the possibility of specifying the SPSR in 123 * the FIP ToC and allowing the platform to have a say as 124 * well. 125 */ 126 spsr = SPSR_MODE32(mode, plat_get_ns_image_entrypoint() & 0x1, 127 SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS); 128 return spsr; 129 } 130 #endif /* AARCH32 */ 131 132 int hikey_bl2_handle_post_image_load(unsigned int image_id) 133 { 134 int err = 0; 135 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 136 #ifdef SPD_opteed 137 bl_mem_params_node_t *pager_mem_params = NULL; 138 bl_mem_params_node_t *paged_mem_params = NULL; 139 #endif 140 assert(bl_mem_params); 141 142 switch (image_id) { 143 #ifdef AARCH64 144 case BL32_IMAGE_ID: 145 #ifdef SPD_opteed 146 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 147 assert(pager_mem_params); 148 149 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); 150 assert(paged_mem_params); 151 152 err = parse_optee_header(&bl_mem_params->ep_info, 153 &pager_mem_params->image_info, 154 &paged_mem_params->image_info); 155 if (err != 0) { 156 WARN("OPTEE header parse error.\n"); 157 } 158 #endif 159 bl_mem_params->ep_info.spsr = hikey_get_spsr_for_bl32_entry(); 160 break; 161 #endif 162 163 case BL33_IMAGE_ID: 164 /* BL33 expects to receive the primary CPU MPID (through r0) */ 165 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); 166 bl_mem_params->ep_info.spsr = hikey_get_spsr_for_bl33_entry(); 167 break; 168 169 #ifdef SCP_BL2_BASE 170 case SCP_BL2_IMAGE_ID: 171 /* The subsequent handling of SCP_BL2 is platform specific */ 172 err = plat_hikey_bl2_handle_scp_bl2(&bl_mem_params->image_info); 173 if (err) { 174 WARN("Failure in platform-specific handling of SCP_BL2 image.\n"); 175 } 176 break; 177 #endif 178 } 179 180 return err; 181 } 182 183 /******************************************************************************* 184 * This function can be used by the platforms to update/use image 185 * information for given `image_id`. 186 ******************************************************************************/ 187 int bl2_plat_handle_post_image_load(unsigned int image_id) 188 { 189 return hikey_bl2_handle_post_image_load(image_id); 190 } 191 192 static void reset_dwmmc_clk(void) 193 { 194 unsigned int data; 195 196 /* disable mmc0 bus clock */ 197 mmio_write_32(PERI_SC_PERIPH_CLKDIS0, PERI_CLK0_MMC0); 198 do { 199 data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0); 200 } while (data & PERI_CLK0_MMC0); 201 /* enable mmc0 bus clock */ 202 mmio_write_32(PERI_SC_PERIPH_CLKEN0, PERI_CLK0_MMC0); 203 do { 204 data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0); 205 } while (!(data & PERI_CLK0_MMC0)); 206 /* reset mmc0 clock domain */ 207 mmio_write_32(PERI_SC_PERIPH_RSTEN0, PERI_RST0_MMC0); 208 209 /* bypass mmc0 clock phase */ 210 data = mmio_read_32(PERI_SC_PERIPH_CTRL2); 211 data |= 3; 212 mmio_write_32(PERI_SC_PERIPH_CTRL2, data); 213 214 /* disable low power */ 215 data = mmio_read_32(PERI_SC_PERIPH_CTRL13); 216 data |= 1 << 3; 217 mmio_write_32(PERI_SC_PERIPH_CTRL13, data); 218 do { 219 data = mmio_read_32(PERI_SC_PERIPH_RSTSTAT0); 220 } while (!(data & PERI_RST0_MMC0)); 221 222 /* unreset mmc0 clock domain */ 223 mmio_write_32(PERI_SC_PERIPH_RSTDIS0, PERI_RST0_MMC0); 224 do { 225 data = mmio_read_32(PERI_SC_PERIPH_RSTSTAT0); 226 } while (data & PERI_RST0_MMC0); 227 } 228 229 static void hikey_boardid_init(void) 230 { 231 u_register_t midr; 232 233 midr = read_midr(); 234 mmio_write_32(MEMORY_AXI_CHIP_ADDR, midr); 235 INFO("[BDID] [%x] midr: 0x%x\n", MEMORY_AXI_CHIP_ADDR, 236 (unsigned int)midr); 237 238 mmio_write_32(MEMORY_AXI_BOARD_TYPE_ADDR, 0); 239 mmio_write_32(MEMORY_AXI_BOARD_ID_ADDR, 0x2b); 240 241 mmio_write_32(ACPU_ARM64_FLAGA, 0x1234); 242 mmio_write_32(ACPU_ARM64_FLAGB, 0x5678); 243 } 244 245 static void hikey_sd_init(void) 246 { 247 /* switch pinmux to SD */ 248 mmio_write_32(IOMG_SD_CLK, IOMG_MUX_FUNC0); 249 mmio_write_32(IOMG_SD_CMD, IOMG_MUX_FUNC0); 250 mmio_write_32(IOMG_SD_DATA0, IOMG_MUX_FUNC0); 251 mmio_write_32(IOMG_SD_DATA1, IOMG_MUX_FUNC0); 252 mmio_write_32(IOMG_SD_DATA2, IOMG_MUX_FUNC0); 253 mmio_write_32(IOMG_SD_DATA3, IOMG_MUX_FUNC0); 254 255 mmio_write_32(IOCG_SD_CLK, IOCG_INPUT_16MA); 256 mmio_write_32(IOCG_SD_CMD, IOCG_INPUT_12MA); 257 mmio_write_32(IOCG_SD_DATA0, IOCG_INPUT_12MA); 258 mmio_write_32(IOCG_SD_DATA1, IOCG_INPUT_12MA); 259 mmio_write_32(IOCG_SD_DATA2, IOCG_INPUT_12MA); 260 mmio_write_32(IOCG_SD_DATA3, IOCG_INPUT_12MA); 261 262 /* set SD Card detect as nopull */ 263 mmio_write_32(IOCG_GPIO8, 0); 264 } 265 266 static void hikey_jumper_init(void) 267 { 268 /* set jumper detect as nopull */ 269 mmio_write_32(IOCG_GPIO24, 0); 270 /* set jumper detect as GPIO */ 271 mmio_write_32(IOMG_GPIO24, IOMG_MUX_FUNC0); 272 } 273 274 void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2, 275 u_register_t arg3, u_register_t arg4) 276 { 277 /* Initialize the console to provide early debug support */ 278 console_init(CONSOLE_BASE, PL011_UART_CLK_IN_HZ, PL011_BAUDRATE); 279 /* 280 * Allow BL2 to see the whole Trusted RAM. 281 */ 282 bl2_el3_tzram_layout.total_base = BL2_RW_BASE; 283 bl2_el3_tzram_layout.total_size = BL31_LIMIT - BL2_RW_BASE; 284 } 285 286 void bl2_el3_plat_arch_setup(void) 287 { 288 hikey_init_mmu_el3(bl2_el3_tzram_layout.total_base, 289 bl2_el3_tzram_layout.total_size, 290 BL2_RO_BASE, 291 BL2_RO_LIMIT, 292 BL2_COHERENT_RAM_BASE, 293 BL2_COHERENT_RAM_LIMIT); 294 } 295 296 void bl2_platform_setup(void) 297 { 298 dw_mmc_params_t params; 299 300 hikey_sp804_init(); 301 hikey_gpio_init(); 302 hikey_pmussi_init(); 303 hikey_hi6553_init(); 304 305 dsb(); 306 hikey_ddr_init(); 307 hikey_security_setup(); 308 309 /* Clear SRAM since it'll be used by MCU right now. */ 310 memset((void *)SRAM_BASE, 0, SRAM_SIZE); 311 clean_dcache_range(SRAM_BASE, SRAM_SIZE); 312 313 hikey_boardid_init(); 314 init_acpu_dvfs(); 315 hikey_rtc_init(); 316 hikey_sd_init(); 317 hikey_jumper_init(); 318 319 hikey_mmc_pll_init(); 320 321 reset_dwmmc_clk(); 322 memset(¶ms, 0, sizeof(dw_mmc_params_t)); 323 params.reg_base = DWMMC0_BASE; 324 params.desc_base = HIKEY_MMC_DESC_BASE; 325 params.desc_size = 1 << 20; 326 params.clk_rate = 24 * 1000 * 1000; 327 params.bus_width = EMMC_BUS_WIDTH_8; 328 params.flags = EMMC_FLAG_CMD23; 329 dw_mmc_init(¶ms); 330 331 hikey_io_setup(); 332 } 333