1 /* 2 * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __PLATFORM_DEF_H__ 8 #define __PLATFORM_DEF_H__ 9 10 #include <arm_def.h> 11 #include <board_arm_def.h> 12 #include <board_css_def.h> 13 #include <common_def.h> 14 #include <css_def.h> 15 #if TRUSTED_BOARD_BOOT 16 #include <mbedtls_config.h> 17 #endif 18 #include <soc_css_def.h> 19 #include <tzc400.h> 20 #include <v2m_def.h> 21 #include "../juno_def.h" 22 23 /* Required platform porting definitions */ 24 /* Juno supports system power domain */ 25 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 26 #define PLAT_NUM_PWR_DOMAINS (ARM_SYSTEM_COUNT + \ 27 JUNO_CLUSTER_COUNT + \ 28 PLATFORM_CORE_COUNT) 29 #define PLATFORM_CORE_COUNT (JUNO_CLUSTER0_CORE_COUNT + \ 30 JUNO_CLUSTER1_CORE_COUNT) 31 32 /* Cryptocell HW Base address */ 33 #define PLAT_CRYPTOCELL_BASE 0x60050000 34 35 /* 36 * Other platform porting definitions are provided by included headers 37 */ 38 39 /* 40 * Required ARM standard platform porting definitions 41 */ 42 #define PLAT_ARM_CLUSTER_COUNT JUNO_CLUSTER_COUNT 43 44 /* Use the bypass address */ 45 #define PLAT_ARM_TRUSTED_ROM_BASE V2M_FLASH0_BASE + BL1_ROM_BYPASS_OFFSET 46 47 /* 48 * Actual ROM size on Juno is 64 KB, but TBB currently requires at least 80 KB 49 * in debug mode. We can test TBB on Juno bypassing the ROM and using 128 KB of 50 * flash 51 */ 52 #if TRUSTED_BOARD_BOOT 53 #define PLAT_ARM_TRUSTED_ROM_SIZE 0x00020000 54 #else 55 #define PLAT_ARM_TRUSTED_ROM_SIZE 0x00010000 56 #endif /* TRUSTED_BOARD_BOOT */ 57 58 /* 59 * If ARM_BOARD_OPTIMISE_MEM=0 then Juno uses the default, unoptimised values 60 * defined for ARM development platforms. 61 */ 62 #if ARM_BOARD_OPTIMISE_MEM 63 /* 64 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 65 * plat_arm_mmap array defined for each BL stage. 66 */ 67 #ifdef IMAGE_BL1 68 # define PLAT_ARM_MMAP_ENTRIES 7 69 # define MAX_XLAT_TABLES 4 70 #endif 71 72 #ifdef IMAGE_BL2 73 #ifdef SPD_opteed 74 # define PLAT_ARM_MMAP_ENTRIES 11 75 # define MAX_XLAT_TABLES 5 76 #else 77 # define PLAT_ARM_MMAP_ENTRIES 10 78 # define MAX_XLAT_TABLES 4 79 #endif 80 #endif 81 82 #ifdef IMAGE_BL2U 83 # define PLAT_ARM_MMAP_ENTRIES 4 84 # define MAX_XLAT_TABLES 3 85 #endif 86 87 #ifdef IMAGE_BL31 88 # define PLAT_ARM_MMAP_ENTRIES 7 89 # define MAX_XLAT_TABLES 3 90 #endif 91 92 #ifdef IMAGE_BL32 93 # define PLAT_ARM_MMAP_ENTRIES 5 94 # define MAX_XLAT_TABLES 4 95 #endif 96 97 /* 98 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 99 * plus a little space for growth. 100 */ 101 #if TRUSTED_BOARD_BOOT 102 # define PLAT_ARM_MAX_BL1_RW_SIZE 0xA000 103 #else 104 # define PLAT_ARM_MAX_BL1_RW_SIZE 0x6000 105 #endif 106 107 /* 108 * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a 109 * little space for growth. 110 */ 111 #if TRUSTED_BOARD_BOOT 112 #if TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA 113 # define PLAT_ARM_MAX_BL2_SIZE 0x20000 114 #elif TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_ECDSA 115 # define PLAT_ARM_MAX_BL2_SIZE 0x1D000 116 #else 117 # define PLAT_ARM_MAX_BL2_SIZE 0x1C000 118 #endif 119 #else 120 # define PLAT_ARM_MAX_BL2_SIZE 0xE000 121 #endif 122 123 /* 124 * PLAT_ARM_MAX_BL31_SIZE is calculated using the current BL31 debug size plus a 125 * little space for growth. 126 * SCP_BL2 image is loaded into the space BL31 -> BL1_RW_BASE. 127 * For TBB use case, PLAT_ARM_MAX_BL1_RW_SIZE has been increased and therefore 128 * PLAT_ARM_MAX_BL31_SIZE has been increased to ensure SCP_BL2 has the same 129 * space available. 130 */ 131 #define PLAT_ARM_MAX_BL31_SIZE 0x1E000 132 133 #if JUNO_AARCH32_EL3_RUNTIME 134 /* 135 * PLAT_ARM_MAX_BL32_SIZE is calculated for SP_MIN as the AArch32 Secure 136 * Payload. We also need to take care of SCP_BL2 size as well, as the SCP_BL2 137 * is loaded into the space BL32 -> BL1_RW_BASE 138 */ 139 # define PLAT_ARM_MAX_BL32_SIZE 0x1E000 140 #endif 141 142 /* 143 * Since free SRAM space is scant, enable the ASSERTION message size 144 * optimization by fixing the PLAT_LOG_LEVEL_ASSERT to LOG_LEVEL_INFO (40). 145 */ 146 #define PLAT_LOG_LEVEL_ASSERT 40 147 148 #endif /* ARM_BOARD_OPTIMISE_MEM */ 149 150 /* CCI related constants */ 151 #define PLAT_ARM_CCI_BASE 0x2c090000 152 #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 4 153 #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 3 154 155 /* System timer related constants */ 156 #define PLAT_ARM_NSTIMER_FRAME_ID 1 157 158 /* TZC related constants */ 159 #define PLAT_ARM_TZC_BASE 0x2a4a0000 160 #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ 161 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CCI400) | \ 162 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_PCIE) | \ 163 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD0) | \ 164 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD1) | \ 165 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_USB) | \ 166 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_DMA330) | \ 167 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_THINLINKS) | \ 168 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_AP) | \ 169 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_GPU) | \ 170 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CORESIGHT)) 171 172 /* 173 * Required ARM CSS based platform porting definitions 174 */ 175 176 /* GIC related constants (no GICR in GIC-400) */ 177 #define PLAT_ARM_GICD_BASE 0x2c010000 178 #define PLAT_ARM_GICC_BASE 0x2c02f000 179 #define PLAT_ARM_GICH_BASE 0x2c04f000 180 #define PLAT_ARM_GICV_BASE 0x2c06f000 181 182 /* MHU related constants */ 183 #define PLAT_CSS_MHU_BASE 0x2b1f0000 184 185 /* 186 * Base address of the first memory region used for communication between AP 187 * and SCP. Used by the BOM and SCPI protocols. 188 */ 189 #if !CSS_USE_SCMI_SDS_DRIVER 190 /* 191 * Note that this is located at the same address as SCP_BOOT_CFG_ADDR, which 192 * means the SCP/AP configuration data gets overwritten when the AP initiates 193 * communication with the SCP. The configuration data is expected to be a 194 * 32-bit word on all CSS platforms. On Juno, part of this configuration is 195 * which CPU is the primary, according to the shift and mask definitions below. 196 */ 197 #define PLAT_CSS_SCP_COM_SHARED_MEM_BASE (ARM_TRUSTED_SRAM_BASE + 0x80) 198 #define PLAT_CSS_PRIMARY_CPU_SHIFT 8 199 #define PLAT_CSS_PRIMARY_CPU_BIT_WIDTH 4 200 #endif 201 202 /* 203 * PLAT_CSS_MAX_SCP_BL2_SIZE is calculated using the current 204 * SCP_BL2 size plus a little space for growth. 205 */ 206 #define PLAT_CSS_MAX_SCP_BL2_SIZE 0x14000 207 208 /* 209 * PLAT_CSS_MAX_SCP_BL2U_SIZE is calculated using the current 210 * SCP_BL2U size plus a little space for growth. 211 */ 212 #define PLAT_CSS_MAX_SCP_BL2U_SIZE 0x14000 213 214 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 215 CSS_G1S_IRQ_PROPS(grp), \ 216 ARM_G1S_IRQ_PROPS(grp), \ 217 INTR_PROP_DESC(JUNO_IRQ_DMA_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 218 grp, GIC_INTR_CFG_LEVEL), \ 219 INTR_PROP_DESC(JUNO_IRQ_HDLCD0_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 220 grp, GIC_INTR_CFG_LEVEL), \ 221 INTR_PROP_DESC(JUNO_IRQ_HDLCD1_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 222 grp, GIC_INTR_CFG_LEVEL), \ 223 INTR_PROP_DESC(JUNO_IRQ_USB_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 224 grp, GIC_INTR_CFG_LEVEL), \ 225 INTR_PROP_DESC(JUNO_IRQ_THIN_LINKS_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 226 grp, GIC_INTR_CFG_LEVEL), \ 227 INTR_PROP_DESC(JUNO_IRQ_SEC_I2C, GIC_HIGHEST_SEC_PRIORITY, \ 228 grp, GIC_INTR_CFG_LEVEL), \ 229 INTR_PROP_DESC(JUNO_IRQ_GPU_SMMU_1, GIC_HIGHEST_SEC_PRIORITY, \ 230 grp, GIC_INTR_CFG_LEVEL), \ 231 INTR_PROP_DESC(JUNO_IRQ_ETR_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 232 grp, GIC_INTR_CFG_LEVEL) 233 234 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 235 236 /* 237 * Required ARM CSS SoC based platform porting definitions 238 */ 239 240 /* CSS SoC NIC-400 Global Programmers View (GPV) */ 241 #define PLAT_SOC_CSS_NIC400_BASE 0x2a000000 242 243 #define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS 244 #define PLAT_ARM_SHARED_SDEI_EVENTS ARM_SDEI_SHARED_EVENTS 245 246 #endif /* __PLATFORM_DEF_H__ */ 247