1 /* 2 * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __PLATFORM_DEF_H__ 8 #define __PLATFORM_DEF_H__ 9 10 /* Enable the dynamic translation tables library. */ 11 #ifdef AARCH32 12 # if defined(IMAGE_BL32) && RESET_TO_SP_MIN 13 # define PLAT_XLAT_TABLES_DYNAMIC 1 14 # endif 15 #else 16 # if defined(IMAGE_BL31) && RESET_TO_BL31 17 # define PLAT_XLAT_TABLES_DYNAMIC 1 18 # endif 19 #endif /* AARCH32 */ 20 21 22 #include <arm_def.h> 23 #include <board_arm_def.h> 24 #include <board_css_def.h> 25 #include <common_def.h> 26 #include <css_def.h> 27 #if TRUSTED_BOARD_BOOT 28 #include <mbedtls_config.h> 29 #endif 30 #include <soc_css_def.h> 31 #include <tzc400.h> 32 #include <v2m_def.h> 33 #include "../juno_def.h" 34 35 /* Required platform porting definitions */ 36 /* Juno supports system power domain */ 37 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 38 #define PLAT_NUM_PWR_DOMAINS (ARM_SYSTEM_COUNT + \ 39 JUNO_CLUSTER_COUNT + \ 40 PLATFORM_CORE_COUNT) 41 #define PLATFORM_CORE_COUNT (JUNO_CLUSTER0_CORE_COUNT + \ 42 JUNO_CLUSTER1_CORE_COUNT) 43 44 /* Cryptocell HW Base address */ 45 #define PLAT_CRYPTOCELL_BASE 0x60050000 46 47 /* 48 * Other platform porting definitions are provided by included headers 49 */ 50 51 /* 52 * Required ARM standard platform porting definitions 53 */ 54 #define PLAT_ARM_CLUSTER_COUNT JUNO_CLUSTER_COUNT 55 56 /* Use the bypass address */ 57 #define PLAT_ARM_TRUSTED_ROM_BASE V2M_FLASH0_BASE + BL1_ROM_BYPASS_OFFSET 58 59 /* virtual address used by dynamic mem_protect for chunk_base */ 60 #define PLAT_ARM_MEM_PROTEC_VA_FRAME 0xc0000000 61 62 /* 63 * Actual ROM size on Juno is 64 KB, but TBB currently requires at least 80 KB 64 * in debug mode. We can test TBB on Juno bypassing the ROM and using 128 KB of 65 * flash 66 */ 67 #if TRUSTED_BOARD_BOOT 68 #define PLAT_ARM_TRUSTED_ROM_SIZE 0x00020000 69 #else 70 #define PLAT_ARM_TRUSTED_ROM_SIZE 0x00010000 71 #endif /* TRUSTED_BOARD_BOOT */ 72 73 /* 74 * If ARM_BOARD_OPTIMISE_MEM=0 then Juno uses the default, unoptimised values 75 * defined for ARM development platforms. 76 */ 77 #if ARM_BOARD_OPTIMISE_MEM 78 /* 79 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 80 * plat_arm_mmap array defined for each BL stage. 81 */ 82 #ifdef IMAGE_BL1 83 # define PLAT_ARM_MMAP_ENTRIES 7 84 # define MAX_XLAT_TABLES 4 85 #endif 86 87 #ifdef IMAGE_BL2 88 #ifdef SPD_opteed 89 # define PLAT_ARM_MMAP_ENTRIES 11 90 # define MAX_XLAT_TABLES 5 91 #else 92 # define PLAT_ARM_MMAP_ENTRIES 10 93 # define MAX_XLAT_TABLES 4 94 #endif 95 #endif 96 97 #ifdef IMAGE_BL2U 98 # define PLAT_ARM_MMAP_ENTRIES 4 99 # define MAX_XLAT_TABLES 3 100 #endif 101 102 #ifdef IMAGE_BL31 103 # define PLAT_ARM_MMAP_ENTRIES 7 104 # define MAX_XLAT_TABLES 3 105 #endif 106 107 #ifdef IMAGE_BL32 108 # define PLAT_ARM_MMAP_ENTRIES 6 109 # define MAX_XLAT_TABLES 4 110 #endif 111 112 /* 113 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 114 * plus a little space for growth. 115 */ 116 #if TRUSTED_BOARD_BOOT 117 # define PLAT_ARM_MAX_BL1_RW_SIZE 0xA000 118 #else 119 # define PLAT_ARM_MAX_BL1_RW_SIZE 0x6000 120 #endif 121 122 /* 123 * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a 124 * little space for growth. 125 */ 126 #if TRUSTED_BOARD_BOOT 127 #if TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA 128 # define PLAT_ARM_MAX_BL2_SIZE 0x20000 129 #elif TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_ECDSA 130 # define PLAT_ARM_MAX_BL2_SIZE 0x1D000 131 #else 132 # define PLAT_ARM_MAX_BL2_SIZE 0x1C000 133 #endif 134 #else 135 # define PLAT_ARM_MAX_BL2_SIZE 0xE000 136 #endif 137 138 /* 139 * PLAT_ARM_MAX_BL31_SIZE is calculated using the current BL31 debug size plus a 140 * little space for growth. 141 * SCP_BL2 image is loaded into the space BL31 -> BL1_RW_BASE. 142 * For TBB use case, PLAT_ARM_MAX_BL1_RW_SIZE has been increased and therefore 143 * PLAT_ARM_MAX_BL31_SIZE has been increased to ensure SCP_BL2 has the same 144 * space available. 145 */ 146 #define PLAT_ARM_MAX_BL31_SIZE 0x1E000 147 148 #if JUNO_AARCH32_EL3_RUNTIME 149 /* 150 * PLAT_ARM_MAX_BL32_SIZE is calculated for SP_MIN as the AArch32 Secure 151 * Payload. We also need to take care of SCP_BL2 size as well, as the SCP_BL2 152 * is loaded into the space BL32 -> BL1_RW_BASE 153 */ 154 # define PLAT_ARM_MAX_BL32_SIZE 0x1E000 155 #endif 156 157 /* 158 * Since free SRAM space is scant, enable the ASSERTION message size 159 * optimization by fixing the PLAT_LOG_LEVEL_ASSERT to LOG_LEVEL_INFO (40). 160 */ 161 #define PLAT_LOG_LEVEL_ASSERT 40 162 163 #endif /* ARM_BOARD_OPTIMISE_MEM */ 164 165 /* CCI related constants */ 166 #define PLAT_ARM_CCI_BASE 0x2c090000 167 #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 4 168 #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 3 169 170 /* System timer related constants */ 171 #define PLAT_ARM_NSTIMER_FRAME_ID 1 172 173 /* TZC related constants */ 174 #define PLAT_ARM_TZC_BASE 0x2a4a0000 175 #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ 176 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CCI400) | \ 177 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_PCIE) | \ 178 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD0) | \ 179 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD1) | \ 180 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_USB) | \ 181 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_DMA330) | \ 182 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_THINLINKS) | \ 183 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_AP) | \ 184 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_GPU) | \ 185 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CORESIGHT)) 186 187 /* 188 * Required ARM CSS based platform porting definitions 189 */ 190 191 /* GIC related constants (no GICR in GIC-400) */ 192 #define PLAT_ARM_GICD_BASE 0x2c010000 193 #define PLAT_ARM_GICC_BASE 0x2c02f000 194 #define PLAT_ARM_GICH_BASE 0x2c04f000 195 #define PLAT_ARM_GICV_BASE 0x2c06f000 196 197 /* MHU related constants */ 198 #define PLAT_CSS_MHU_BASE 0x2b1f0000 199 200 /* 201 * Base address of the first memory region used for communication between AP 202 * and SCP. Used by the BOM and SCPI protocols. 203 */ 204 #if !CSS_USE_SCMI_SDS_DRIVER 205 /* 206 * Note that this is located at the same address as SCP_BOOT_CFG_ADDR, which 207 * means the SCP/AP configuration data gets overwritten when the AP initiates 208 * communication with the SCP. The configuration data is expected to be a 209 * 32-bit word on all CSS platforms. On Juno, part of this configuration is 210 * which CPU is the primary, according to the shift and mask definitions below. 211 */ 212 #define PLAT_CSS_SCP_COM_SHARED_MEM_BASE (ARM_TRUSTED_SRAM_BASE + 0x80) 213 #define PLAT_CSS_PRIMARY_CPU_SHIFT 8 214 #define PLAT_CSS_PRIMARY_CPU_BIT_WIDTH 4 215 #endif 216 217 /* 218 * PLAT_CSS_MAX_SCP_BL2_SIZE is calculated using the current 219 * SCP_BL2 size plus a little space for growth. 220 */ 221 #define PLAT_CSS_MAX_SCP_BL2_SIZE 0x14000 222 223 /* 224 * PLAT_CSS_MAX_SCP_BL2U_SIZE is calculated using the current 225 * SCP_BL2U size plus a little space for growth. 226 */ 227 #define PLAT_CSS_MAX_SCP_BL2U_SIZE 0x14000 228 229 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 230 CSS_G1S_IRQ_PROPS(grp), \ 231 ARM_G1S_IRQ_PROPS(grp), \ 232 INTR_PROP_DESC(JUNO_IRQ_DMA_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 233 grp, GIC_INTR_CFG_LEVEL), \ 234 INTR_PROP_DESC(JUNO_IRQ_HDLCD0_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 235 grp, GIC_INTR_CFG_LEVEL), \ 236 INTR_PROP_DESC(JUNO_IRQ_HDLCD1_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 237 grp, GIC_INTR_CFG_LEVEL), \ 238 INTR_PROP_DESC(JUNO_IRQ_USB_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 239 grp, GIC_INTR_CFG_LEVEL), \ 240 INTR_PROP_DESC(JUNO_IRQ_THIN_LINKS_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 241 grp, GIC_INTR_CFG_LEVEL), \ 242 INTR_PROP_DESC(JUNO_IRQ_SEC_I2C, GIC_HIGHEST_SEC_PRIORITY, \ 243 grp, GIC_INTR_CFG_LEVEL), \ 244 INTR_PROP_DESC(JUNO_IRQ_GPU_SMMU_1, GIC_HIGHEST_SEC_PRIORITY, \ 245 grp, GIC_INTR_CFG_LEVEL), \ 246 INTR_PROP_DESC(JUNO_IRQ_ETR_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 247 grp, GIC_INTR_CFG_LEVEL) 248 249 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 250 251 /* 252 * Required ARM CSS SoC based platform porting definitions 253 */ 254 255 /* CSS SoC NIC-400 Global Programmers View (GPV) */ 256 #define PLAT_SOC_CSS_NIC400_BASE 0x2a000000 257 258 #define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS 259 #define PLAT_ARM_SHARED_SDEI_EVENTS ARM_SDEI_SHARED_EVENTS 260 261 #endif /* __PLATFORM_DEF_H__ */ 262