1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #include <arch_helpers.h> 7 #include <assert.h> 8 #include <bl_common.h> 9 #include <cassert.h> 10 #include <gic_common.h> 11 #include <gicv3.h> 12 #include <interrupt_mgmt.h> 13 #include <platform.h> 14 15 #ifdef IMAGE_BL31 16 17 /* 18 * The following platform GIC functions are weakly defined. They 19 * provide typical implementations that may be re-used by multiple 20 * platforms but may also be overridden by a platform if required. 21 */ 22 #pragma weak plat_ic_get_pending_interrupt_id 23 #pragma weak plat_ic_get_pending_interrupt_type 24 #pragma weak plat_ic_acknowledge_interrupt 25 #pragma weak plat_ic_get_interrupt_type 26 #pragma weak plat_ic_end_of_interrupt 27 #pragma weak plat_interrupt_type_to_line 28 29 #pragma weak plat_ic_get_running_priority 30 #pragma weak plat_ic_is_spi 31 #pragma weak plat_ic_is_ppi 32 #pragma weak plat_ic_is_sgi 33 #pragma weak plat_ic_get_interrupt_active 34 #pragma weak plat_ic_enable_interrupt 35 #pragma weak plat_ic_disable_interrupt 36 #pragma weak plat_ic_set_interrupt_priority 37 #pragma weak plat_ic_set_interrupt_type 38 #pragma weak plat_ic_raise_el3_sgi 39 #pragma weak plat_ic_set_spi_routing 40 #pragma weak plat_ic_set_interrupt_pending 41 #pragma weak plat_ic_clear_interrupt_pending 42 43 CASSERT((INTR_TYPE_S_EL1 == INTR_GROUP1S) && 44 (INTR_TYPE_NS == INTR_GROUP1NS) && 45 (INTR_TYPE_EL3 == INTR_GROUP0), assert_interrupt_type_mismatch); 46 47 /* 48 * This function returns the highest priority pending interrupt at 49 * the Interrupt controller 50 */ 51 uint32_t plat_ic_get_pending_interrupt_id(void) 52 { 53 unsigned int irqnr; 54 55 assert(IS_IN_EL3()); 56 irqnr = gicv3_get_pending_interrupt_id(); 57 return (gicv3_is_intr_id_special_identifier(irqnr)) ? 58 INTR_ID_UNAVAILABLE : irqnr; 59 } 60 61 /* 62 * This function returns the type of the highest priority pending interrupt 63 * at the Interrupt controller. In the case of GICv3, the Highest Priority 64 * Pending interrupt system register (`ICC_HPPIR0_EL1`) is read to determine 65 * the id of the pending interrupt. The type of interrupt depends upon the 66 * id value as follows. 67 * 1. id = PENDING_G1S_INTID (1020) is reported as a S-EL1 interrupt 68 * 2. id = PENDING_G1NS_INTID (1021) is reported as a Non-secure interrupt. 69 * 3. id = GIC_SPURIOUS_INTERRUPT (1023) is reported as an invalid interrupt 70 * type. 71 * 4. All other interrupt id's are reported as EL3 interrupt. 72 */ 73 uint32_t plat_ic_get_pending_interrupt_type(void) 74 { 75 unsigned int irqnr; 76 77 assert(IS_IN_EL3()); 78 irqnr = gicv3_get_pending_interrupt_type(); 79 80 switch (irqnr) { 81 case PENDING_G1S_INTID: 82 return INTR_TYPE_S_EL1; 83 case PENDING_G1NS_INTID: 84 return INTR_TYPE_NS; 85 case GIC_SPURIOUS_INTERRUPT: 86 return INTR_TYPE_INVAL; 87 default: 88 return INTR_TYPE_EL3; 89 } 90 } 91 92 /* 93 * This function returns the highest priority pending interrupt at 94 * the Interrupt controller and indicates to the Interrupt controller 95 * that the interrupt processing has started. 96 */ 97 uint32_t plat_ic_acknowledge_interrupt(void) 98 { 99 assert(IS_IN_EL3()); 100 return gicv3_acknowledge_interrupt(); 101 } 102 103 /* 104 * This function returns the type of the interrupt `id`, depending on how 105 * the interrupt has been configured in the interrupt controller 106 */ 107 uint32_t plat_ic_get_interrupt_type(uint32_t id) 108 { 109 assert(IS_IN_EL3()); 110 return gicv3_get_interrupt_type(id, plat_my_core_pos()); 111 } 112 113 /* 114 * This functions is used to indicate to the interrupt controller that 115 * the processing of the interrupt corresponding to the `id` has 116 * finished. 117 */ 118 void plat_ic_end_of_interrupt(uint32_t id) 119 { 120 assert(IS_IN_EL3()); 121 gicv3_end_of_interrupt(id); 122 } 123 124 /* 125 * An ARM processor signals interrupt exceptions through the IRQ and FIQ pins. 126 * The interrupt controller knows which pin/line it uses to signal a type of 127 * interrupt. It lets the interrupt management framework determine for a type of 128 * interrupt and security state, which line should be used in the SCR_EL3 to 129 * control its routing to EL3. The interrupt line is represented as the bit 130 * position of the IRQ or FIQ bit in the SCR_EL3. 131 */ 132 uint32_t plat_interrupt_type_to_line(uint32_t type, 133 uint32_t security_state) 134 { 135 assert(type == INTR_TYPE_S_EL1 || 136 type == INTR_TYPE_EL3 || 137 type == INTR_TYPE_NS); 138 139 assert(sec_state_is_valid(security_state)); 140 assert(IS_IN_EL3()); 141 142 switch (type) { 143 case INTR_TYPE_S_EL1: 144 /* 145 * The S-EL1 interrupts are signaled as IRQ in S-EL0/1 contexts 146 * and as FIQ in the NS-EL0/1/2 contexts 147 */ 148 if (security_state == SECURE) 149 return __builtin_ctz(SCR_IRQ_BIT); 150 else 151 return __builtin_ctz(SCR_FIQ_BIT); 152 case INTR_TYPE_NS: 153 /* 154 * The Non secure interrupts will be signaled as FIQ in S-EL0/1 155 * contexts and as IRQ in the NS-EL0/1/2 contexts. 156 */ 157 if (security_state == SECURE) 158 return __builtin_ctz(SCR_FIQ_BIT); 159 else 160 return __builtin_ctz(SCR_IRQ_BIT); 161 case INTR_TYPE_EL3: 162 /* 163 * The EL3 interrupts are signaled as FIQ in both S-EL0/1 and 164 * NS-EL0/1/2 contexts 165 */ 166 return __builtin_ctz(SCR_FIQ_BIT); 167 default: 168 panic(); 169 } 170 } 171 172 unsigned int plat_ic_get_running_priority(void) 173 { 174 return gicv3_get_running_priority(); 175 } 176 177 int plat_ic_is_spi(unsigned int id) 178 { 179 return (id >= MIN_SPI_ID) && (id <= MAX_SPI_ID); 180 } 181 182 int plat_ic_is_ppi(unsigned int id) 183 { 184 return (id >= MIN_PPI_ID) && (id < MIN_SPI_ID); 185 } 186 187 int plat_ic_is_sgi(unsigned int id) 188 { 189 return (id >= MIN_SGI_ID) && (id < MIN_PPI_ID); 190 } 191 192 unsigned int plat_ic_get_interrupt_active(unsigned int id) 193 { 194 return gicv3_get_interrupt_active(id, plat_my_core_pos()); 195 } 196 197 void plat_ic_enable_interrupt(unsigned int id) 198 { 199 gicv3_enable_interrupt(id, plat_my_core_pos()); 200 } 201 202 void plat_ic_disable_interrupt(unsigned int id) 203 { 204 gicv3_disable_interrupt(id, plat_my_core_pos()); 205 } 206 207 void plat_ic_set_interrupt_priority(unsigned int id, unsigned int priority) 208 { 209 gicv3_set_interrupt_priority(id, plat_my_core_pos(), priority); 210 } 211 212 int plat_ic_has_interrupt_type(unsigned int type) 213 { 214 assert((type == INTR_TYPE_EL3) || (type == INTR_TYPE_S_EL1) || 215 (type == INTR_TYPE_NS)); 216 return 1; 217 } 218 219 void plat_ic_set_interrupt_type(unsigned int id, unsigned int type) 220 { 221 gicv3_set_interrupt_type(id, plat_my_core_pos(), type); 222 } 223 224 void plat_ic_raise_el3_sgi(int sgi_num, u_register_t target) 225 { 226 /* Target must be a valid MPIDR in the system */ 227 assert(plat_core_pos_by_mpidr(target) >= 0); 228 229 /* Verify that this is a secure EL3 SGI */ 230 assert(plat_ic_get_interrupt_type(sgi_num) == INTR_TYPE_EL3); 231 232 gicv3_raise_secure_g0_sgi(sgi_num, target); 233 } 234 235 void plat_ic_set_spi_routing(unsigned int id, unsigned int routing_mode, 236 u_register_t mpidr) 237 { 238 unsigned int irm = 0; 239 240 switch (routing_mode) { 241 case INTR_ROUTING_MODE_PE: 242 assert(plat_core_pos_by_mpidr(mpidr) >= 0); 243 irm = GICV3_IRM_PE; 244 break; 245 case INTR_ROUTING_MODE_ANY: 246 irm = GICV3_IRM_ANY; 247 break; 248 default: 249 assert(0); 250 } 251 252 gicv3_set_spi_routing(id, irm, mpidr); 253 } 254 255 void plat_ic_set_interrupt_pending(unsigned int id) 256 { 257 /* Disallow setting SGIs pending */ 258 assert(id >= MIN_PPI_ID); 259 gicv3_set_interrupt_pending(id, plat_my_core_pos()); 260 } 261 262 void plat_ic_clear_interrupt_pending(unsigned int id) 263 { 264 /* Disallow setting SGIs pending */ 265 assert(id >= MIN_PPI_ID); 266 gicv3_clear_interrupt_pending(id, plat_my_core_pos()); 267 } 268 269 unsigned int plat_ic_set_priority_mask(unsigned int mask) 270 { 271 return gicv3_set_pmr(mask); 272 } 273 274 unsigned int plat_ic_get_interrupt_id(unsigned int raw) 275 { 276 unsigned int id = (raw & INT_ID_MASK); 277 278 return (gicv3_is_intr_id_special_identifier(id) ? 279 INTR_ID_UNAVAILABLE : id); 280 } 281 #endif 282 #ifdef IMAGE_BL32 283 284 #pragma weak plat_ic_get_pending_interrupt_id 285 #pragma weak plat_ic_acknowledge_interrupt 286 #pragma weak plat_ic_end_of_interrupt 287 288 /* In AArch32, the secure group1 interrupts are targeted to Secure PL1 */ 289 #ifdef AARCH32 290 #define IS_IN_EL1() IS_IN_SECURE() 291 #endif 292 293 /* 294 * This function returns the highest priority pending interrupt at 295 * the Interrupt controller 296 */ 297 uint32_t plat_ic_get_pending_interrupt_id(void) 298 { 299 unsigned int irqnr; 300 301 assert(IS_IN_EL1()); 302 irqnr = gicv3_get_pending_interrupt_id_sel1(); 303 return (irqnr == GIC_SPURIOUS_INTERRUPT) ? 304 INTR_ID_UNAVAILABLE : irqnr; 305 } 306 307 /* 308 * This function returns the highest priority pending interrupt at 309 * the Interrupt controller and indicates to the Interrupt controller 310 * that the interrupt processing has started. 311 */ 312 uint32_t plat_ic_acknowledge_interrupt(void) 313 { 314 assert(IS_IN_EL1()); 315 return gicv3_acknowledge_interrupt_sel1(); 316 } 317 318 /* 319 * This functions is used to indicate to the interrupt controller that 320 * the processing of the interrupt corresponding to the `id` has 321 * finished. 322 */ 323 void plat_ic_end_of_interrupt(uint32_t id) 324 { 325 assert(IS_IN_EL1()); 326 gicv3_end_of_interrupt_sel1(id); 327 } 328 #endif 329