1/* 2 * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6#include <arch.h> 7#include <asm_macros.S> 8#include <bl_common.h> 9#include <cortex_a53.h> 10#include <cpu_macros.S> 11#include <debug.h> 12#include <errata_report.h> 13#include <plat_macros.S> 14 15#if A53_DISABLE_NON_TEMPORAL_HINT 16#undef ERRATA_A53_836870 17#define ERRATA_A53_836870 1 18#endif 19 20 /* --------------------------------------------- 21 * Disable L1 data cache and unified L2 cache 22 * --------------------------------------------- 23 */ 24func cortex_a53_disable_dcache 25 mrs x1, sctlr_el3 26 bic x1, x1, #SCTLR_C_BIT 27 msr sctlr_el3, x1 28 isb 29 ret 30endfunc cortex_a53_disable_dcache 31 32 /* --------------------------------------------- 33 * Disable intra-cluster coherency 34 * --------------------------------------------- 35 */ 36func cortex_a53_disable_smp 37 mrs x0, CORTEX_A53_ECTLR_EL1 38 bic x0, x0, #CORTEX_A53_ECTLR_SMP_BIT 39 msr CORTEX_A53_ECTLR_EL1, x0 40 isb 41 dsb sy 42 ret 43endfunc cortex_a53_disable_smp 44 45 /* -------------------------------------------------- 46 * Errata Workaround for Cortex A53 Errata #826319. 47 * This applies only to revision <= r0p2 of Cortex A53. 48 * Inputs: 49 * x0: variant[4:7] and revision[0:3] of current cpu. 50 * Shall clobber: x0-x17 51 * -------------------------------------------------- 52 */ 53func errata_a53_826319_wa 54 /* 55 * Compare x0 against revision r0p2 56 */ 57 mov x17, x30 58 bl check_errata_826319 59 cbz x0, 1f 60 mrs x1, CORTEX_A53_L2ACTLR_EL1 61 bic x1, x1, #CORTEX_A53_L2ACTLR_ENABLE_UNIQUECLEAN 62 orr x1, x1, #CORTEX_A53_L2ACTLR_DISABLE_CLEAN_PUSH 63 msr CORTEX_A53_L2ACTLR_EL1, x1 641: 65 ret x17 66endfunc errata_a53_826319_wa 67 68func check_errata_826319 69 mov x1, #0x02 70 b cpu_rev_var_ls 71endfunc check_errata_826319 72 73 /* --------------------------------------------------------------------- 74 * Disable the cache non-temporal hint. 75 * 76 * This ignores the Transient allocation hint in the MAIR and treats 77 * allocations the same as non-transient allocation types. As a result, 78 * the LDNP and STNP instructions in AArch64 behave the same as the 79 * equivalent LDP and STP instructions. 80 * 81 * This is relevant only for revisions <= r0p3 of Cortex-A53. 82 * From r0p4 and onwards, the bit to disable the hint is enabled by 83 * default at reset. 84 * 85 * Inputs: 86 * x0: variant[4:7] and revision[0:3] of current cpu. 87 * Shall clobber: x0-x17 88 * --------------------------------------------------------------------- 89 */ 90func a53_disable_non_temporal_hint 91 /* 92 * Compare x0 against revision r0p3 93 */ 94 mov x17, x30 95 bl check_errata_disable_non_temporal_hint 96 cbz x0, 1f 97 mrs x1, CORTEX_A53_CPUACTLR_EL1 98 orr x1, x1, #CORTEX_A53_CPUACTLR_EL1_DTAH 99 msr CORTEX_A53_CPUACTLR_EL1, x1 1001: 101 ret x17 102endfunc a53_disable_non_temporal_hint 103 104func check_errata_disable_non_temporal_hint 105 mov x1, #0x03 106 b cpu_rev_var_ls 107endfunc check_errata_disable_non_temporal_hint 108 109 /* -------------------------------------------------- 110 * Errata Workaround for Cortex A53 Errata #855873. 111 * 112 * This applies only to revisions >= r0p3 of Cortex A53. 113 * Earlier revisions of the core are affected as well, but don't 114 * have the chicken bit in the CPUACTLR register. It is expected that 115 * the rich OS takes care of that, especially as the workaround is 116 * shared with other erratas in those revisions of the CPU. 117 * Inputs: 118 * x0: variant[4:7] and revision[0:3] of current cpu. 119 * Shall clobber: x0-x17 120 * -------------------------------------------------- 121 */ 122func errata_a53_855873_wa 123 /* 124 * Compare x0 against revision r0p3 and higher 125 */ 126 mov x17, x30 127 bl check_errata_855873 128 cbz x0, 1f 129 130 mrs x1, CORTEX_A53_CPUACTLR_EL1 131 orr x1, x1, #CORTEX_A53_CPUACTLR_EL1_ENDCCASCI 132 msr CORTEX_A53_CPUACTLR_EL1, x1 1331: 134 ret x17 135endfunc errata_a53_855873_wa 136 137func check_errata_855873 138 mov x1, #0x03 139 b cpu_rev_var_hs 140endfunc check_errata_855873 141 142/* 143 * Errata workaround for Cortex A53 Errata #835769. 144 * This applies to revisions <= r0p4 of Cortex A53. 145 * This workaround is statically enabled at build time. 146 */ 147func check_errata_835769 148 mov x1, #0x04 149 b cpu_rev_var_ls 150endfunc check_errata_835769 151 152/* 153 * Errata workaround for Cortex A53 Errata #843419. 154 * This applies to revisions <= r0p4 of Cortex A53. 155 * This workaround is statically enabled at build time. 156 */ 157func check_errata_843419 158 mov x1, #ERRATA_APPLIES 159 mov x2, #ERRATA_NOT_APPLIES 160 cmp x0, #0x04 161 csel x0, x1, x2, ls 162 /* 163 * Fix potentially available for revision r0p4. 164 * If r0p4 check for fix in REVIDR, else exit. 165 */ 166 b.ne exit_check_errata_843419 167 /* Load REVIDR. */ 168 mrs x3, revidr_el1 169 /* If REVIDR[8] is set (fix exists) set ERRATA_NOT_APPLIES, else exit. */ 170 tbz x3, #8, exit_check_errata_843419 171 mov x0, x2 172exit_check_errata_843419: 173 ret 174endfunc check_errata_843419 175 176 /* ------------------------------------------------- 177 * The CPU Ops reset function for Cortex-A53. 178 * Shall clobber: x0-x19 179 * ------------------------------------------------- 180 */ 181func cortex_a53_reset_func 182 mov x19, x30 183 bl cpu_get_rev_var 184 mov x18, x0 185 186 187#if ERRATA_A53_826319 188 mov x0, x18 189 bl errata_a53_826319_wa 190#endif 191 192#if ERRATA_A53_836870 193 mov x0, x18 194 bl a53_disable_non_temporal_hint 195#endif 196 197#if ERRATA_A53_855873 198 mov x0, x18 199 bl errata_a53_855873_wa 200#endif 201 202 /* --------------------------------------------- 203 * Enable the SMP bit. 204 * --------------------------------------------- 205 */ 206 mrs x0, CORTEX_A53_ECTLR_EL1 207 orr x0, x0, #CORTEX_A53_ECTLR_SMP_BIT 208 msr CORTEX_A53_ECTLR_EL1, x0 209 isb 210 ret x19 211endfunc cortex_a53_reset_func 212 213func cortex_a53_core_pwr_dwn 214 mov x18, x30 215 216 /* --------------------------------------------- 217 * Turn off caches. 218 * --------------------------------------------- 219 */ 220 bl cortex_a53_disable_dcache 221 222 /* --------------------------------------------- 223 * Flush L1 caches. 224 * --------------------------------------------- 225 */ 226 mov x0, #DCCISW 227 bl dcsw_op_level1 228 229 /* --------------------------------------------- 230 * Come out of intra cluster coherency 231 * --------------------------------------------- 232 */ 233 mov x30, x18 234 b cortex_a53_disable_smp 235endfunc cortex_a53_core_pwr_dwn 236 237func cortex_a53_cluster_pwr_dwn 238 mov x18, x30 239 240 /* --------------------------------------------- 241 * Turn off caches. 242 * --------------------------------------------- 243 */ 244 bl cortex_a53_disable_dcache 245 246 /* --------------------------------------------- 247 * Flush L1 caches. 248 * --------------------------------------------- 249 */ 250 mov x0, #DCCISW 251 bl dcsw_op_level1 252 253 /* --------------------------------------------- 254 * Disable the optional ACP. 255 * --------------------------------------------- 256 */ 257 bl plat_disable_acp 258 259 /* --------------------------------------------- 260 * Flush L2 caches. 261 * --------------------------------------------- 262 */ 263 mov x0, #DCCISW 264 bl dcsw_op_level2 265 266 /* --------------------------------------------- 267 * Come out of intra cluster coherency 268 * --------------------------------------------- 269 */ 270 mov x30, x18 271 b cortex_a53_disable_smp 272endfunc cortex_a53_cluster_pwr_dwn 273 274#if REPORT_ERRATA 275/* 276 * Errata printing function for Cortex A53. Must follow AAPCS. 277 */ 278func cortex_a53_errata_report 279 stp x8, x30, [sp, #-16]! 280 281 bl cpu_get_rev_var 282 mov x8, x0 283 284 /* 285 * Report all errata. The revision-variant information is passed to 286 * checking functions of each errata. 287 */ 288 report_errata ERRATA_A53_826319, cortex_a53, 826319 289 report_errata ERRATA_A53_835769, cortex_a53, 835769 290 report_errata ERRATA_A53_836870, cortex_a53, disable_non_temporal_hint 291 report_errata ERRATA_A53_843419, cortex_a53, 843419 292 report_errata ERRATA_A53_855873, cortex_a53, 855873 293 294 ldp x8, x30, [sp], #16 295 ret 296endfunc cortex_a53_errata_report 297#endif 298 299 /* --------------------------------------------- 300 * This function provides cortex_a53 specific 301 * register information for crash reporting. 302 * It needs to return with x6 pointing to 303 * a list of register names in ascii and 304 * x8 - x15 having values of registers to be 305 * reported. 306 * --------------------------------------------- 307 */ 308.section .rodata.cortex_a53_regs, "aS" 309cortex_a53_regs: /* The ascii list of register names to be reported */ 310 .asciz "cpuectlr_el1", "cpumerrsr_el1", "l2merrsr_el1", \ 311 "cpuactlr_el1", "" 312 313func cortex_a53_cpu_reg_dump 314 adr x6, cortex_a53_regs 315 mrs x8, CORTEX_A53_ECTLR_EL1 316 mrs x9, CORTEX_A53_MERRSR_EL1 317 mrs x10, CORTEX_A53_L2MERRSR_EL1 318 mrs x11, CORTEX_A53_CPUACTLR_EL1 319 ret 320endfunc cortex_a53_cpu_reg_dump 321 322declare_cpu_ops cortex_a53, CORTEX_A53_MIDR, \ 323 cortex_a53_reset_func, \ 324 cortex_a53_core_pwr_dwn, \ 325 cortex_a53_cluster_pwr_dwn 326