fix(arm): move HW_CONFIG relocation into BL31

Refactor DT relocation logic from BL2 to BL31 for non-secure DRAM.
Previously, BL2 was responsible for copying the DT into SRAM and DRAM,
resulting in d

fix(arm): move HW_CONFIG relocation into BL31

Refactor DT relocation logic from BL2 to BL31 for non-secure DRAM.
Previously, BL2 was responsible for copying the DT into SRAM and DRAM,
resulting in duplicate code in BL31 to cater for the `RESET_TO_BL31`
case. By moving the re-location logic to BL31, we simplify handling of
the non-secure DT and TL.

Change-Id: Id239f9410669afe4b223fa8d8bb093084a0e5e1b
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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fix(cpus): workaround for Cortex-A720 erratum 2844092

Cortex-A720 erratum 2844092 is a Cat B erratum that is present
in revisions r0p0, r0p1 and is fixed in r0p2.

The workaround is to set bit[11] o

fix(cpus): workaround for Cortex-A720 erratum 2844092

Cortex-A720 erratum 2844092 is a Cat B erratum that is present
in revisions r0p0, r0p1 and is fixed in r0p2.

The workaround is to set bit[11] of CPUACTLR4_EL1 register.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2439421/latest

Change-Id: I3d8eacb26cba42774f1f31c3aae2a0e6fecec614
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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fix(cpus): workaround for Cortex-X4 erratum 2816013

Cortex-X4 erratum 2816013 is a Cat B erratum that applies
to all revisions <= r0p1 and is fixed in r0p2. This erratum
is only present when memory

fix(cpus): workaround for Cortex-X4 erratum 2816013

Cortex-X4 erratum 2816013 is a Cat B erratum that applies
to all revisions <= r0p1 and is fixed in r0p2. This erratum
is only present when memory tagging is enabled.

The workaround is to set CPUACTLR5_EL1[14] to 1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2432808/latest

Change-Id: I546044bde6e5eedd0abf61643d25e2dd2036df5c
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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feat(trbe): introduce trbe_disable() function

This patch adds trbe_disable() which disables Trace buffer access
from lower ELs in all security state. This function makes Secure
state the owner of Tr

feat(trbe): introduce trbe_disable() function

This patch adds trbe_disable() which disables Trace buffer access
from lower ELs in all security state. This function makes Secure
state the owner of Trace buffer and access from EL2/EL1 generate
trap exceptions to EL3.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: If3e3bd621684b3c28f44c3ed2fe3df30b143f8cd

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feat(spe): introduce spe_disable() function

Introduce a function to disable SPE feature for Non-secure state and do
the default setting of making Secure state the owner of profiling
buffers and trap

feat(spe): introduce spe_disable() function

Introduce a function to disable SPE feature for Non-secure state and do
the default setting of making Secure state the owner of profiling
buffers and trap access of profiling and profiling buffer control
registers from lower ELs to EL3.

This functionality is required to handle asymmetric cores where SPE has
to disabled at runtime.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I2f99e922e8df06bfc900c153137aef7c9dcfd759

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chore(spe): rename spe_disable() to spe_stop()

During CPU power down, we stop the profiling by calling spe_disable()
function. From TF-A point of view, enable/disable means the avaibility
of the fea

chore(spe): rename spe_disable() to spe_stop()

During CPU power down, we stop the profiling by calling spe_disable()
function. From TF-A point of view, enable/disable means the avaibility
of the feature for lower EL. In this case we are not actully disabling
the feautre but stoping it before power down.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I6e3b39c5c35d330c51e7ac715446a8b36bf9531f

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Merge changes from topic "jc/refact_el1_ctx" into integration

* changes:
refactor(cm): convert el1-ctx assembly offset entries to c structure
feat(cm): add explicit context entries for ERRATA_SP

Merge changes from topic "jc/refact_el1_ctx" into integration

* changes:
refactor(cm): convert el1-ctx assembly offset entries to c structure
feat(cm): add explicit context entries for ERRATA_SPECULATIVE_AT

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Merge "feat(fvp): add flash areas for secure partition" into integration

feat(fvp): add flash areas for secure partition

To support UEFI secure variable service,
StandaloneMm which runs in BL32 should know flash areas.
Add flash memory areas and system register region
so

feat(fvp): add flash areas for secure partition

To support UEFI secure variable service,
StandaloneMm which runs in BL32 should know flash areas.
Add flash memory areas and system register region
so that StandaloneMm access to flash storages.

Change-Id: I803bda9664a17a0b978ebff90974eaf5442a91cd
Signed-off-by: levi.yun <yeoreum.yun@arm.com>

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refactor(cm): convert el1-ctx assembly offset entries to c structure

Currently the EL1 part of the context structure (el1_sysregs_t),
is coupled with feature flags reducing the context memory alloca

refactor(cm): convert el1-ctx assembly offset entries to c structure

Currently the EL1 part of the context structure (el1_sysregs_t),
is coupled with feature flags reducing the context memory allocation
for platforms, that don't enable/support all the architectural
features at once.

Similar to the el2 context optimization commit-"d6af234" this patch
further improves this section by converting the assembly context-offset
entries into a c structure. It relies on garbage collection of the
linker removing unreferenced structures from memory, as well as aiding
in readability and future maintenance. Additionally, it eliminates
the #ifs usage in 'context_mgmt.c' source file.

Change-Id: If6075931cec994bc89231241337eccc7042c5ede
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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feat(cm): add explicit context entries for ERRATA_SPECULATIVE_AT

* Currently, "ERRATA_SPECUALTIVE_AT" errata is enabled by default
for few cores and they need context entries for saving and
rest

feat(cm): add explicit context entries for ERRATA_SPECULATIVE_AT

* Currently, "ERRATA_SPECUALTIVE_AT" errata is enabled by default
for few cores and they need context entries for saving and
restoring EL1 regs "SCTLR_EL1 and TCR_EL1" registers at all times.

* This prevents the mechanism of decoupling EL1 and EL2 registers,
as EL3 firmware shouldn't be handling both simultaneously.

* Depending on the build configuration either EL1 or EL2 context
structures need to included, which would result in saving a good
amount of context memory.

* In order to achieve this it's essential to have explicit context
entries for registers supporting "ERRATA_SPECULATIVE_AT".

* This patch adds two context entries under "errata_speculative_at"
structure to assist this errata and thereby allows decoupling
EL1 and EL2 context structures.

Change-Id: Ia50626eea8fb64899a2e2d81622adbe07fe77d65
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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refactor(cpus): remove cpu specific errata funcs

Errata printing is done directly via generic_errata_report.
This commit removes the unused \_cpu\()_errata_report
functions for all cores, and remove

refactor(cpus): remove cpu specific errata funcs

Errata printing is done directly via generic_errata_report.
This commit removes the unused \_cpu\()_errata_report
functions for all cores, and removes errata_func from cpu_ops.

Change-Id: I04fefbde5f0ff63b1f1cd17c864557a14070d68c
Signed-off-by: Ryan Everett <ryan.everett@arm.com>

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refactor(cpus): directly invoke errata reporter

In all non-trivial cases the CPU specific errata functions
already call generic_errata_report, this cuts out the middleman
by directly calling generic

refactor(cpus): directly invoke errata reporter

In all non-trivial cases the CPU specific errata functions
already call generic_errata_report, this cuts out the middleman
by directly calling generic_errata_report from
print_errata_status.

The CPU specific errata functions (cpu_ops->errata_func)
can now be removed from all cores, and this field can be
removed from cpu_ops.

Also removes the now unused old errata reporting
function and macros.

Change-Id: Ie4a4fd60429aca37cf434e79c0ce2992a5ff5d68
Signed-off-by: Ryan Everett <ryan.everett@arm.com>

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Merge "feat(handoff): fix register convention r1/x1 value on transfer list" into integration

Merge "fix(xlat): correct attribute retrieval in a RME enabled system" into integration

Merge "feat(fgt2): add support for FEAT_FGT2" into integration

feat(tc): enable Last-level cache (LLC)

The EXTLLC bit in CPUECTLR_EL1 register indicates that an external
Last-level cache is present in the system.

This bit is not set for CPUs on TC3 platform de

feat(tc): enable Last-level cache (LLC)

The EXTLLC bit in CPUECTLR_EL1 register indicates that an external
Last-level cache is present in the system.

This bit is not set for CPUs on TC3 platform despite there is
presence of LLC in MCN, so set them.

Change-Id: I5f889e67dce2b1d00e4ee66a8c255cf7911825b0
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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feat(cpus): add sysreg_bitfield_insert_from_gpr macro

A macro 'sysreg_bitfield_insert_from_gpr' is introduced for inserting
bitfield from a general register.

Change-Id: I7288a13d70d98e23dc7a93287b0

feat(cpus): add sysreg_bitfield_insert_from_gpr macro

A macro 'sysreg_bitfield_insert_from_gpr' is introduced for inserting
bitfield from a general register.

Change-Id: I7288a13d70d98e23dc7a93287b04b493ffce9171
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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feat(handoff): fix register convention r1/x1 value on transfer list

According to recently firmware handsoff spec [1]'s "Register usage at handoff
boundary", Transfer List's signature value was chang

feat(handoff): fix register convention r1/x1 value on transfer list

According to recently firmware handsoff spec [1]'s "Register usage at handoff
boundary", Transfer List's signature value was changed from 0x40_b10b
(3 bytes) to 4a0f_b10b (4 bytes).

As updating of TL's signature, register value of x1/r1 should be:

In aarch32's r1 value should be
R1[23:0]: set to the TL signature (4a0f_b10b -> masked range value: 0f_b10b)
R1[31:24]: version of the register convention == 1
and
In aarch64's x1 value should be
X1[31:0]: set to the TL signature (4a0f_b10b)
X1[39:32]: version of the register convention == 1
X1[63:40]: MBZ
(See the [2] and [3]).

Therefore, it requires to separate mask and shift value for register
convention version field when sets each r1/x1.

This patch fix two problems:
1. breaking X1 value with updated specification in aarch64
- change of length of signature field.

2. previous error value set in R1 in arm32.
- length of signature should be 24, but it uses 32bit signature.

This change is breaking change. It requires some patch for other
softwares (u-boot[4], optee[5]).

Link: https://github.com/FirmwareHandoff/firmware_handoff [1]
Link: https://github.com/FirmwareHandoff/firmware_handoff/issues/32 [2]
Link: https://github.com/FirmwareHandoff/firmware_handoff/commit/5aa7aa1d3a1db75213e458d392b751f0707de027 [3]
Link: https://lists.denx.de/pipermail/u-boot/2024-July/558628.html [4]
Link: https://github.com/OP-TEE/optee_os/pull/6933 [5]
Signed-off-by: Levi Yun <yeoreum.yun@arm.com>
Change-Id: Ie417e054a7a4c192024a2679419e99efeded1705

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fix(xlat): correct attribute retrieval in a RME enabled system

In a system enabled with RME, the function
'xlat_get_mem_attributes_internal' fails to accurately provide
'output PA space' for Realm a

fix(xlat): correct attribute retrieval in a RME enabled system

In a system enabled with RME, the function
'xlat_get_mem_attributes_internal' fails to accurately provide
'output PA space' for Realm and Root memory because it does not
consider the 'nse' bit in page table descriptor.
This patch resolves the issue by extracting the 'nse' bit value.
As a result, it ensures correct retrieval of attributes
in RME-enabled systems while maintaining unaffected attribute
retrieval for non-RME systems.

Change-Id: If2d01545b921c9074f48c52a98027ff331e14237
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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feat(fgt2): add support for FEAT_FGT2

This patch disables trapping to EL3 when the FEAT_FGT2
specific trap registers are accessed by setting the
SCR_EL3.FGTEn2 bit

Signed-off-by: Arvind Ram Prakash

feat(fgt2): add support for FEAT_FGT2

This patch disables trapping to EL3 when the FEAT_FGT2
specific trap registers are accessed by setting the
SCR_EL3.FGTEn2 bit

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I6d2b614affb9067b2bc3d7bf0ae7d169d031592a

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feat(debugv8p9): add support for FEAT_Debugv8p9

This patch enables FEAT_Debugv8p9 and prevents EL1/0 from
trapping to EL3 when accessing MDSELR_EL1 register by
setting the MDCR_EL3.EBWE bit.

Signed

feat(debugv8p9): add support for FEAT_Debugv8p9

This patch enables FEAT_Debugv8p9 and prevents EL1/0 from
trapping to EL3 when accessing MDSELR_EL1 register by
setting the MDCR_EL3.EBWE bit.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I3613af1dd8cb8c0d3c33dc959f170846c0b9695a

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feat(nxp-clk): set rate for clock fixed divider

Add set rate support for fixed divider clock modules of whose role is to
reduce the source frequency by a factor.

Change-Id: I8a29a2c5b1a829db0c39640

feat(nxp-clk): set rate for clock fixed divider

Add set rate support for fixed divider clock modules of whose role is to
reduce the source frequency by a factor.

Change-Id: I8a29a2c5b1a829db0c396407c3517c9e66caaa93
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add A53 clock objects

These objects are needed to allow early enablement of the A53 core
clock.

Change-Id: I44d81975c8eba8cc6cfd18aeb6c9b324edaa3f01
Signed-off-by: Ghennadi Procopciu

feat(nxp-clk): add A53 clock objects

These objects are needed to allow early enablement of the A53 core
clock.

Change-Id: I44d81975c8eba8cc6cfd18aeb6c9b324edaa3f01
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): set rate for PLL divider objects

Add implementation for ARM PLL divider rate set mechanism.

Change-Id: I78f4418bcbb5ea0a6ef64675e44bd074d2230ea3
Signed-off-by: Ghennadi Procopciuc <g

feat(nxp-clk): set rate for PLL divider objects

Add implementation for ARM PLL divider rate set mechanism.

Change-Id: I78f4418bcbb5ea0a6ef64675e44bd074d2230ea3
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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