feat(nxp-clk): add get_rate for partition objects

The partition-related objects do not participate in clock rate
calculation, except the s32cc_part_block_link_t, whose call is forwarded
to the paren

feat(nxp-clk): add get_rate for partition objects

The partition-related objects do not participate in clock rate
calculation, except the s32cc_part_block_link_t, whose call is forwarded
to the parent object.

Change-Id: Id9e7fa49c3c1fb5b30b4c1b97fc8441bc967578a
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add get_rate for clock muxes

From the get rate callback perspective, all types of clock muxes should
return the frequency of the selected source, regardless of whether it is
an MC_CGM

feat(nxp-clk): add get_rate for clock muxes

From the get rate callback perspective, all types of clock muxes should
return the frequency of the selected source, regardless of whether it is
an MC_CGM or PLL mux.

Change-Id: I24ae821013b0844e4d62793fde12b53b043a9776
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add get_rate for s32cc_pll_out_div

The get rate callback is needed for s32cc_pll_out_div to get the A53
cores and DDR rate.

Change-Id: Ife7860c9941e819b612d7948dac9843bdf0c31c4
Signe

feat(nxp-clk): add get_rate for s32cc_pll_out_div

The get rate callback is needed for s32cc_pll_out_div to get the A53
cores and DDR rate.

Change-Id: Ife7860c9941e819b612d7948dac9843bdf0c31c4
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add get_rate for s32cc_fixed_div

The get rate callback is needed for s32cc_fixed_div to allow the
frequency compilation for modules attached to a fixed divider like
LINFLEXD_CLK.

Cha

feat(nxp-clk): add get_rate for s32cc_fixed_div

The get rate callback is needed for s32cc_fixed_div to allow the
frequency compilation for modules attached to a fixed divider like
LINFLEXD_CLK.

Change-Id: Ibc3e52f7f1127bba0dd793be0a26bdff15260824
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add get_rate for s32cc_dfs_div

Add the option to obtain the rate of an s32cc_dfs_div object. As in the
case of the PLL, the output divider of a DFS will return its targeted
frequency

feat(nxp-clk): add get_rate for s32cc_dfs_div

Add the option to obtain the rate of an s32cc_dfs_div object. As in the
case of the PLL, the output divider of a DFS will return its targeted
frequency if the module is disabled and calculate the rate based on the
settings found in its registers if the module is turned on.

Change-Id: Id6db92dbdf03f8119875476ad8f7aa268ff6ea93
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add get_rate for s32cc_dfs

Add the option to obtain the rate of an s32cc_dfs object. The DFS rate
depends on the module to which it's connected. Therefore, it will always
return the r

feat(nxp-clk): add get_rate for s32cc_dfs

Add the option to obtain the rate of an s32cc_dfs object. The DFS rate
depends on the module to which it's connected. Therefore, it will always
return the rate of its parent.

Change-Id: Ie3becd36721f541d0fab11b2fb57aacd66d48220
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add get_rate for s32cc_pll

Add the option to obtain the rate of an s32cc_pll object. The rate of
the PLL can be obtained regardless of its hardware state. The targeted
frequency is re

feat(nxp-clk): add get_rate for s32cc_pll

Add the option to obtain the rate of an s32cc_pll object. The rate of
the PLL can be obtained regardless of its hardware state. The targeted
frequency is returned in case the PLL is off. Otherwise, the frequency
is determined based on settings found in its registers.

Change-Id: Id200d0eff149109a724eee69b063bf750d5cba2e
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add get_rate for s32cc_clk

Add the option to obtain the rate of an s32cc_clk object. s32cc_clk are
usually links to either another s32cc_clk or a different clock module.
Therefore, th

feat(nxp-clk): add get_rate for s32cc_clk

Add the option to obtain the rate of an s32cc_clk object. s32cc_clk are
usually links to either another s32cc_clk or a different clock module.
Therefore, this function routes the request.

Change-Id: I0c1174cb861d2062882319e46cb6ca97bad70aab
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add a basic get_rate implementation

Replace the dummy implementation of clk_ops.get_rate with a basic
version that only handles the oscillator objects. Subsequent commits
will add mor

feat(nxp-clk): add a basic get_rate implementation

Replace the dummy implementation of clk_ops.get_rate with a basic
version that only handles the oscillator objects. Subsequent commits
will add more objects to this list.

Change-Id: I8c1bbbfa6b116fdcf5a1f1353bdb52b474bac831
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(s32g274a): split early clock initialization

Initializing all early clocks before the MMU is enabled can impact boot
time. Therefore, splitting the setup into A53 clocks and peripheral
clocks ca

feat(s32g274a): split early clock initialization

Initializing all early clocks before the MMU is enabled can impact boot
time. Therefore, splitting the setup into A53 clocks and peripheral
clocks can be beneficial, with the peripheral clocks configured after
fully initializing the MMU.

Change-Id: I19644227b66effab8e2c43e64e057ea0c8625ebc
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): dynamic map of the clock modules

Add all clock modules as entries in MMU using dynamic regions.

Change-Id: I56f724ced4bd024554c7b38afd14ea420de80cc6
Signed-off-by: Ghennadi Procopciu

feat(nxp-clk): dynamic map of the clock modules

Add all clock modules as entries in MMU using dynamic regions.

Change-Id: I56f724ced4bd024554c7b38afd14ea420de80cc6
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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fix(nxp-clk): function parameter should not be modified

The function 'update_stack_depth' modifies the value of the 'depth'
parameter passed by reference. Typically, the caller recevies this
paramet

fix(nxp-clk): function parameter should not be modified

The function 'update_stack_depth' modifies the value of the 'depth'
parameter passed by reference. Typically, the caller recevies this
parameter by value, and it is then passed to 'update_stack_depth' by
reference. This violates MISRA 17.8 rule. To address this issue, a new
local variable is introduced to store the value of 'depth'.

Change-Id: Ia37f4ede9e6558f778bdda17b7b195f1f50d0c30
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): enable the DDR clock

Enable the DDR clock by setting up its reset block, the associated
partition and configuring the clock tree above the MC_CGM mux.

Change-Id: Idfed24b3e74a189df87

feat(nxp-clk): enable the DDR clock

Enable the DDR clock by setting up its reset block, the associated
partition and configuring the clock tree above the MC_CGM mux.

Change-Id: Idfed24b3e74a189df87f9782886a91b906cd2022
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add objects needed for DDR clock

The DDR clock can be powered by either a PLL or an oscillator. An MC_CGM
mux selects between these two clock sources. A reset block, part of
partition

feat(nxp-clk): add objects needed for DDR clock

The DDR clock can be powered by either a PLL or an oscillator. An MC_CGM
mux selects between these two clock sources. A reset block, part of
partition 0, is also connected to this IP block. Therefore, all the
dependencies mentioned above must be configured to have a working clock.

Change-Id: Ia841428db9acb95c59ea851b6afeb0b7ff9230a2
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): setup the DDR PLL

Add the DDR PLL instance and configure it to operate at its maximum
allowed frequency.

Change-Id: I96efd68687de78f70759f631d10a0f611c234c8d
Signed-off-by: Ghennadi

feat(nxp-clk): setup the DDR PLL

Add the DDR PLL instance and configure it to operate at its maximum
allowed frequency.

Change-Id: I96efd68687de78f70759f631d10a0f611c234c8d
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add MC_ME utilities

MC_ME is one of the leading hardware blocks responsible for partitions'
transition to and from a reset state. Not being the only one involved in
this role, it must

feat(nxp-clk): add MC_ME utilities

MC_ME is one of the leading hardware blocks responsible for partitions'
transition to and from a reset state. Not being the only one involved in
this role, it must cooperate with some other modules (MC_RGM, RDC) to
successfully bring a peripheral out of the reset state. As a result, the
partition management is isolated into a dedicated file, as parts of it
will later contribute to peripheral reset control.

Change-Id: I6a9dbf28008b1677bc847bbafa474b489c999d05
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add partition reset utilities

MC_RGM is a hardware block involved in resetting peripherals and
partitions. Here, the accessories for partition reset are added.

Change-Id: If00755fe0e

feat(nxp-clk): add partition reset utilities

MC_RGM is a hardware block involved in resetting peripherals and
partitions. Here, the accessories for partition reset are added.

Change-Id: If00755fe0e93ba2e4841f95ed5ae3c87db20bebf
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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fix(s32g274a): workaround for ERR051700 erratum

ERR051700 erratum is present on all S32CC-based SoCs and relates to
reset. Releasing multiple Software Resettable Domains (SRDs) from
reset simultaneo

fix(s32g274a): workaround for ERR051700 erratum

ERR051700 erratum is present on all S32CC-based SoCs and relates to
reset. Releasing multiple Software Resettable Domains (SRDs) from
reset simultaneously, may cause a false error in the fault control
unit.

The workaround is to clear the SRD resets sequentially instead of
simultaneously.

Change-Id: I883bc223bf6834907259e6964a5702d7186e4c7f
Signed-off-by: Alexandru-Catalin Ionita <alexandru-catalin.ionita@nxp.com>
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): refactor clock enablement

Simplify the clock enablement mechanism from a usage perspective. With
this new approach, enabling a clock cascades the turn-on sequence of all
its parent cl

feat(nxp-clk): refactor clock enablement

Simplify the clock enablement mechanism from a usage perspective. With
this new approach, enabling a clock cascades the turn-on sequence of all
its parent clocks in the clock tree. Therefore, enabling the A53 clock
will also turn on the A53 PLL and the oscillator that feeds it.

Change-Id: Ifc2bee3e9edbb4baced34f9e809a961562f7d0a6
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add get_parent callback

Bring in the implementation for the struct clk_ops->get_parent callback
for the S32G clock driver. The parent is established depending on the
clock object type

feat(nxp-clk): add get_parent callback

Bring in the implementation for the struct clk_ops->get_parent callback
for the S32G clock driver. The parent is established depending on the
clock object type. Usually, this is determined based on the parent
field, but not always.

Change-Id: I76a3d2636dc23ba2d547d058b8650dd0e99fe1fa
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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fix(nxp-clk): broken UART clock initalization

The UART clock initialization failed because the clock mux enablement
mechanism did not correctly recognize the PERIPH PLL mux. Therefore, it
was report

fix(nxp-clk): broken UART clock initalization

The UART clock initialization failed because the clock mux enablement
mechanism did not correctly recognize the PERIPH PLL mux. Therefore, it
was reported as an unknown mux ID.

Change-Id: I6cc72c87a8462a2ed2e7c360f59a74961bb2f3a1
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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Merge changes from topic "nxp-drivers/add-linflex-clk" into integration

* changes:
feat(nxp-clk): enable UART clock
feat(nxp-clk): add PERIPH PLL enablement

feat(nxp-clk): enable UART clock

Before this change, the internal oscillator clocked the UART with a
frequency of 48MHz. With the necessary support added, the UART clock
rate is increased to 125MHz

feat(nxp-clk): enable UART clock

Before this change, the internal oscillator clocked the UART with a
frequency of 48MHz. With the necessary support added, the UART clock
rate is increased to 125MHz by changing the clock source from FIRC to
PERIPH PLL PHI3.

Change-Id: I3160dc6860ebf441c9bea8eaf9d8d12de48bd647
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add PERIPH PLL enablement

Peripheral PLL is one of the platform's PLLs, providing a clock for
peripherals such as UART, QSPI, uSDHC, SPI and CAN. Its source can be
either the FIRC or

feat(nxp-clk): add PERIPH PLL enablement

Peripheral PLL is one of the platform's PLLs, providing a clock for
peripherals such as UART, QSPI, uSDHC, SPI and CAN. Its source can be
either the FIRC or FXOSC oscillators. It has eight outputs (PHIs) and
their frequencies can be controlled programmatically using output
dividers. An additional output clocks the PERIPH DFS using the VCO
frequency of the PERIPH PLL.

Change-Id: I637294b2da94f35e95dc1750dad36c129a276bb9
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-drivers): add Linflex flush callback

Implement a flush callback for the Linflex UART driver to avoid cases
where the BL31 stage reinitializes the console while there is ongoing TX
initiated

feat(nxp-drivers): add Linflex flush callback

Implement a flush callback for the Linflex UART driver to avoid cases
where the BL31 stage reinitializes the console while there is ongoing TX
initiated by the BL2.

Change-Id: Ic49852f809198362de1f993474c7c45f1439dc98
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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