1 /* 2 * Copyright 2024-2025 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #include <errno.h> 7 #include <common/debug.h> 8 #include <drivers/clk.h> 9 #include <lib/mmio.h> 10 #include <lib/xlat_tables/xlat_tables_v2.h> 11 #include <s32cc-clk-ids.h> 12 #include <s32cc-clk-modules.h> 13 #include <s32cc-clk-regs.h> 14 #include <s32cc-clk-utils.h> 15 #include <s32cc-mc-me.h> 16 17 #define MAX_STACK_DEPTH (40U) 18 19 /* This is used for floating-point precision calculations. */ 20 #define FP_PRECISION (100000000UL) 21 22 struct s32cc_clk_drv { 23 uintptr_t fxosc_base; 24 uintptr_t armpll_base; 25 uintptr_t periphpll_base; 26 uintptr_t armdfs_base; 27 uintptr_t cgm0_base; 28 uintptr_t cgm1_base; 29 uintptr_t cgm5_base; 30 uintptr_t ddrpll_base; 31 uintptr_t mc_me; 32 uintptr_t mc_rgm; 33 uintptr_t rdc; 34 }; 35 36 static int set_module_rate(const struct s32cc_clk_obj *module, 37 unsigned long rate, unsigned long *orate, 38 unsigned int *depth); 39 static int get_module_rate(const struct s32cc_clk_obj *module, 40 const struct s32cc_clk_drv *drv, 41 unsigned long *rate, 42 unsigned int depth); 43 44 static int update_stack_depth(unsigned int *depth) 45 { 46 if (*depth == 0U) { 47 return -ENOMEM; 48 } 49 50 (*depth)--; 51 return 0; 52 } 53 54 static struct s32cc_clk_drv *get_drv(void) 55 { 56 static struct s32cc_clk_drv driver = { 57 .fxosc_base = FXOSC_BASE_ADDR, 58 .armpll_base = ARMPLL_BASE_ADDR, 59 .periphpll_base = PERIPHPLL_BASE_ADDR, 60 .armdfs_base = ARM_DFS_BASE_ADDR, 61 .cgm0_base = CGM0_BASE_ADDR, 62 .cgm1_base = CGM1_BASE_ADDR, 63 .cgm5_base = MC_CGM5_BASE_ADDR, 64 .ddrpll_base = DDRPLL_BASE_ADDR, 65 .mc_me = MC_ME_BASE_ADDR, 66 .mc_rgm = MC_RGM_BASE_ADDR, 67 .rdc = RDC_BASE_ADDR, 68 }; 69 70 return &driver; 71 } 72 73 static int enable_module(struct s32cc_clk_obj *module, 74 const struct s32cc_clk_drv *drv, 75 unsigned int depth); 76 77 static struct s32cc_clk_obj *get_clk_parent(const struct s32cc_clk_obj *module) 78 { 79 const struct s32cc_clk *clk = s32cc_obj2clk(module); 80 81 if (clk->module != NULL) { 82 return clk->module; 83 } 84 85 if (clk->pclock != NULL) { 86 return &clk->pclock->desc; 87 } 88 89 return NULL; 90 } 91 92 static int get_base_addr(enum s32cc_clk_source id, const struct s32cc_clk_drv *drv, 93 uintptr_t *base) 94 { 95 int ret = 0; 96 97 switch (id) { 98 case S32CC_FXOSC: 99 *base = drv->fxosc_base; 100 break; 101 case S32CC_ARM_PLL: 102 *base = drv->armpll_base; 103 break; 104 case S32CC_PERIPH_PLL: 105 *base = drv->periphpll_base; 106 break; 107 case S32CC_DDR_PLL: 108 *base = drv->ddrpll_base; 109 break; 110 case S32CC_ARM_DFS: 111 *base = drv->armdfs_base; 112 break; 113 case S32CC_CGM0: 114 *base = drv->cgm0_base; 115 break; 116 case S32CC_CGM1: 117 *base = drv->cgm1_base; 118 break; 119 case S32CC_CGM5: 120 *base = drv->cgm5_base; 121 break; 122 case S32CC_FIRC: 123 break; 124 case S32CC_SIRC: 125 break; 126 default: 127 ret = -EINVAL; 128 break; 129 } 130 131 if (ret != 0) { 132 ERROR("Unknown clock source id: %u\n", id); 133 } 134 135 return ret; 136 } 137 138 static void enable_fxosc(const struct s32cc_clk_drv *drv) 139 { 140 uintptr_t fxosc_base = drv->fxosc_base; 141 uint32_t ctrl; 142 143 ctrl = mmio_read_32(FXOSC_CTRL(fxosc_base)); 144 if ((ctrl & FXOSC_CTRL_OSCON) != U(0)) { 145 return; 146 } 147 148 ctrl = FXOSC_CTRL_COMP_EN; 149 ctrl &= ~FXOSC_CTRL_OSC_BYP; 150 ctrl |= FXOSC_CTRL_EOCV(0x1); 151 ctrl |= FXOSC_CTRL_GM_SEL(0x7); 152 mmio_write_32(FXOSC_CTRL(fxosc_base), ctrl); 153 154 /* Switch ON the crystal oscillator. */ 155 mmio_setbits_32(FXOSC_CTRL(fxosc_base), FXOSC_CTRL_OSCON); 156 157 /* Wait until the clock is stable. */ 158 while ((mmio_read_32(FXOSC_STAT(fxosc_base)) & FXOSC_STAT_OSC_STAT) == U(0)) { 159 } 160 } 161 162 static int enable_osc(struct s32cc_clk_obj *module, 163 const struct s32cc_clk_drv *drv, 164 unsigned int depth) 165 { 166 const struct s32cc_osc *osc = s32cc_obj2osc(module); 167 unsigned int ldepth = depth; 168 int ret = 0; 169 170 ret = update_stack_depth(&ldepth); 171 if (ret != 0) { 172 return ret; 173 } 174 175 switch (osc->source) { 176 case S32CC_FXOSC: 177 enable_fxosc(drv); 178 break; 179 /* FIRC and SIRC oscillators are enabled by default */ 180 case S32CC_FIRC: 181 break; 182 case S32CC_SIRC: 183 break; 184 default: 185 ERROR("Invalid oscillator %d\n", osc->source); 186 ret = -EINVAL; 187 break; 188 }; 189 190 return ret; 191 } 192 193 static struct s32cc_clk_obj *get_pll_parent(const struct s32cc_clk_obj *module) 194 { 195 const struct s32cc_pll *pll = s32cc_obj2pll(module); 196 197 if (pll->source == NULL) { 198 ERROR("Failed to identify PLL's parent\n"); 199 } 200 201 return pll->source; 202 } 203 204 static int get_pll_mfi_mfn(unsigned long pll_vco, unsigned long ref_freq, 205 uint32_t *mfi, uint32_t *mfn) 206 207 { 208 unsigned long vco; 209 unsigned long mfn64; 210 211 /* FRAC-N mode */ 212 *mfi = (uint32_t)(pll_vco / ref_freq); 213 214 /* MFN formula : (double)(pll_vco % ref_freq) / ref_freq * 18432.0 */ 215 mfn64 = pll_vco % ref_freq; 216 mfn64 *= FP_PRECISION; 217 mfn64 /= ref_freq; 218 mfn64 *= 18432UL; 219 mfn64 /= FP_PRECISION; 220 221 if (mfn64 > UINT32_MAX) { 222 return -EINVAL; 223 } 224 225 *mfn = (uint32_t)mfn64; 226 227 vco = ((unsigned long)*mfn * FP_PRECISION) / 18432UL; 228 vco += (unsigned long)*mfi * FP_PRECISION; 229 vco *= ref_freq; 230 vco /= FP_PRECISION; 231 232 if (vco != pll_vco) { 233 ERROR("Failed to find MFI and MFN settings for PLL freq %lu. Nearest freq = %lu\n", 234 pll_vco, vco); 235 return -EINVAL; 236 } 237 238 return 0; 239 } 240 241 static struct s32cc_clkmux *get_pll_mux(const struct s32cc_pll *pll) 242 { 243 const struct s32cc_clk_obj *source = pll->source; 244 const struct s32cc_clk *clk; 245 246 if (source == NULL) { 247 ERROR("Failed to identify PLL's parent\n"); 248 return NULL; 249 } 250 251 if (source->type != s32cc_clk_t) { 252 ERROR("The parent of the PLL isn't a clock\n"); 253 return NULL; 254 } 255 256 clk = s32cc_obj2clk(source); 257 258 if (clk->module == NULL) { 259 ERROR("The clock isn't connected to a module\n"); 260 return NULL; 261 } 262 263 source = clk->module; 264 265 if ((source->type != s32cc_clkmux_t) && 266 (source->type != s32cc_shared_clkmux_t)) { 267 ERROR("The parent of the PLL isn't a MUX\n"); 268 return NULL; 269 } 270 271 return s32cc_obj2clkmux(source); 272 } 273 274 static void disable_odiv(uintptr_t pll_addr, uint32_t div_index) 275 { 276 mmio_clrbits_32(PLLDIG_PLLODIV(pll_addr, div_index), PLLDIG_PLLODIV_DE); 277 } 278 279 static void enable_odiv(uintptr_t pll_addr, uint32_t div_index) 280 { 281 mmio_setbits_32(PLLDIG_PLLODIV(pll_addr, div_index), PLLDIG_PLLODIV_DE); 282 } 283 284 static void disable_odivs(uintptr_t pll_addr, uint32_t ndivs) 285 { 286 uint32_t i; 287 288 for (i = 0; i < ndivs; i++) { 289 disable_odiv(pll_addr, i); 290 } 291 } 292 293 static void enable_pll_hw(uintptr_t pll_addr) 294 { 295 /* Enable the PLL. */ 296 mmio_write_32(PLLDIG_PLLCR(pll_addr), 0x0); 297 298 /* Poll until PLL acquires lock. */ 299 while ((mmio_read_32(PLLDIG_PLLSR(pll_addr)) & PLLDIG_PLLSR_LOCK) == 0U) { 300 } 301 } 302 303 static void disable_pll_hw(uintptr_t pll_addr) 304 { 305 mmio_write_32(PLLDIG_PLLCR(pll_addr), PLLDIG_PLLCR_PLLPD); 306 } 307 308 static int program_pll(const struct s32cc_pll *pll, uintptr_t pll_addr, 309 const struct s32cc_clk_drv *drv, uint32_t sclk_id, 310 unsigned long sclk_freq) 311 { 312 uint32_t rdiv = 1, mfi, mfn; 313 int ret; 314 315 ret = get_pll_mfi_mfn(pll->vco_freq, sclk_freq, &mfi, &mfn); 316 if (ret != 0) { 317 return -EINVAL; 318 } 319 320 /* Disable ODIVs*/ 321 disable_odivs(pll_addr, pll->ndividers); 322 323 /* Disable PLL */ 324 disable_pll_hw(pll_addr); 325 326 /* Program PLLCLKMUX */ 327 mmio_write_32(PLLDIG_PLLCLKMUX(pll_addr), sclk_id); 328 329 /* Program VCO */ 330 mmio_clrsetbits_32(PLLDIG_PLLDV(pll_addr), 331 PLLDIG_PLLDV_RDIV_MASK | PLLDIG_PLLDV_MFI_MASK, 332 PLLDIG_PLLDV_RDIV_SET(rdiv) | PLLDIG_PLLDV_MFI(mfi)); 333 334 mmio_write_32(PLLDIG_PLLFD(pll_addr), 335 PLLDIG_PLLFD_MFN_SET(mfn) | PLLDIG_PLLFD_SMDEN); 336 337 enable_pll_hw(pll_addr); 338 339 return ret; 340 } 341 342 static int enable_pll(struct s32cc_clk_obj *module, 343 const struct s32cc_clk_drv *drv, 344 unsigned int depth) 345 { 346 const struct s32cc_pll *pll = s32cc_obj2pll(module); 347 const struct s32cc_clkmux *mux; 348 uintptr_t pll_addr = UL(0x0); 349 unsigned int ldepth = depth; 350 unsigned long sclk_freq; 351 uint32_t sclk_id; 352 int ret; 353 354 ret = update_stack_depth(&ldepth); 355 if (ret != 0) { 356 return ret; 357 } 358 359 mux = get_pll_mux(pll); 360 if (mux == NULL) { 361 return -EINVAL; 362 } 363 364 if (pll->instance != mux->module) { 365 ERROR("MUX type is not in sync with PLL ID\n"); 366 return -EINVAL; 367 } 368 369 ret = get_base_addr(pll->instance, drv, &pll_addr); 370 if (ret != 0) { 371 ERROR("Failed to detect PLL instance\n"); 372 return ret; 373 } 374 375 switch (mux->source_id) { 376 case S32CC_CLK_FIRC: 377 sclk_freq = 48U * MHZ; 378 sclk_id = 0; 379 break; 380 case S32CC_CLK_FXOSC: 381 sclk_freq = 40U * MHZ; 382 sclk_id = 1; 383 break; 384 default: 385 ERROR("Invalid source selection for PLL 0x%lx\n", 386 pll_addr); 387 return -EINVAL; 388 }; 389 390 return program_pll(pll, pll_addr, drv, sclk_id, sclk_freq); 391 } 392 393 static inline struct s32cc_pll *get_div_pll(const struct s32cc_pll_out_div *pdiv) 394 { 395 const struct s32cc_clk_obj *parent; 396 397 parent = pdiv->parent; 398 if (parent == NULL) { 399 ERROR("Failed to identify PLL divider's parent\n"); 400 return NULL; 401 } 402 403 if (parent->type != s32cc_pll_t) { 404 ERROR("The parent of the divider is not a PLL instance\n"); 405 return NULL; 406 } 407 408 return s32cc_obj2pll(parent); 409 } 410 411 static void config_pll_out_div(uintptr_t pll_addr, uint32_t div_index, uint32_t dc) 412 { 413 uint32_t pllodiv; 414 uint32_t pdiv; 415 416 pllodiv = mmio_read_32(PLLDIG_PLLODIV(pll_addr, div_index)); 417 pdiv = PLLDIG_PLLODIV_DIV(pllodiv); 418 419 if (((pdiv + 1U) == dc) && ((pllodiv & PLLDIG_PLLODIV_DE) != 0U)) { 420 return; 421 } 422 423 if ((pllodiv & PLLDIG_PLLODIV_DE) != 0U) { 424 disable_odiv(pll_addr, div_index); 425 } 426 427 pllodiv = PLLDIG_PLLODIV_DIV_SET(dc - 1U); 428 mmio_write_32(PLLDIG_PLLODIV(pll_addr, div_index), pllodiv); 429 430 enable_odiv(pll_addr, div_index); 431 } 432 433 static struct s32cc_clk_obj *get_pll_div_parent(const struct s32cc_clk_obj *module) 434 { 435 const struct s32cc_pll_out_div *pdiv = s32cc_obj2plldiv(module); 436 437 if (pdiv->parent == NULL) { 438 ERROR("Failed to identify PLL DIV's parent\n"); 439 } 440 441 return pdiv->parent; 442 } 443 444 static int enable_pll_div(struct s32cc_clk_obj *module, 445 const struct s32cc_clk_drv *drv, 446 unsigned int depth) 447 { 448 const struct s32cc_pll_out_div *pdiv = s32cc_obj2plldiv(module); 449 uintptr_t pll_addr = 0x0ULL; 450 unsigned int ldepth = depth; 451 const struct s32cc_pll *pll; 452 uint32_t dc; 453 int ret; 454 455 ret = update_stack_depth(&ldepth); 456 if (ret != 0) { 457 return ret; 458 } 459 460 pll = get_div_pll(pdiv); 461 if (pll == NULL) { 462 ERROR("The parent of the PLL DIV is invalid\n"); 463 return 0; 464 } 465 466 ret = get_base_addr(pll->instance, drv, &pll_addr); 467 if (ret != 0) { 468 ERROR("Failed to detect PLL instance\n"); 469 return -EINVAL; 470 } 471 472 dc = (uint32_t)(pll->vco_freq / pdiv->freq); 473 474 config_pll_out_div(pll_addr, pdiv->index, dc); 475 476 return 0; 477 } 478 479 static int cgm_mux_clk_config(uintptr_t cgm_addr, uint32_t mux, uint32_t source, 480 bool safe_clk) 481 { 482 uint32_t css, csc; 483 484 css = mmio_read_32(CGM_MUXn_CSS(cgm_addr, mux)); 485 486 /* Already configured */ 487 if ((MC_CGM_MUXn_CSS_SELSTAT(css) == source) && 488 (MC_CGM_MUXn_CSS_SWTRG(css) == MC_CGM_MUXn_CSS_SWTRG_SUCCESS) && 489 ((css & MC_CGM_MUXn_CSS_SWIP) == 0U) && !safe_clk) { 490 return 0; 491 } 492 493 /* Ongoing clock switch? */ 494 while ((mmio_read_32(CGM_MUXn_CSS(cgm_addr, mux)) & 495 MC_CGM_MUXn_CSS_SWIP) != 0U) { 496 } 497 498 csc = mmio_read_32(CGM_MUXn_CSC(cgm_addr, mux)); 499 500 /* Clear previous source. */ 501 csc &= ~(MC_CGM_MUXn_CSC_SELCTL_MASK); 502 503 if (!safe_clk) { 504 /* Select the clock source and trigger the clock switch. */ 505 csc |= MC_CGM_MUXn_CSC_SELCTL(source) | MC_CGM_MUXn_CSC_CLK_SW; 506 } else { 507 /* Switch to safe clock */ 508 csc |= MC_CGM_MUXn_CSC_SAFE_SW; 509 } 510 511 mmio_write_32(CGM_MUXn_CSC(cgm_addr, mux), csc); 512 513 /* Wait for configuration bit to auto-clear. */ 514 while ((mmio_read_32(CGM_MUXn_CSC(cgm_addr, mux)) & 515 MC_CGM_MUXn_CSC_CLK_SW) != 0U) { 516 } 517 518 /* Is the clock switch completed? */ 519 while ((mmio_read_32(CGM_MUXn_CSS(cgm_addr, mux)) & 520 MC_CGM_MUXn_CSS_SWIP) != 0U) { 521 } 522 523 /* 524 * Check if the switch succeeded. 525 * Check switch trigger cause and the source. 526 */ 527 css = mmio_read_32(CGM_MUXn_CSS(cgm_addr, mux)); 528 if (!safe_clk) { 529 if ((MC_CGM_MUXn_CSS_SWTRG(css) == MC_CGM_MUXn_CSS_SWTRG_SUCCESS) && 530 (MC_CGM_MUXn_CSS_SELSTAT(css) == source)) { 531 return 0; 532 } 533 534 ERROR("Failed to change the source of mux %" PRIu32 " to %" PRIu32 " (CGM=%lu)\n", 535 mux, source, cgm_addr); 536 } else { 537 if (((MC_CGM_MUXn_CSS_SWTRG(css) == MC_CGM_MUXn_CSS_SWTRG_SAFE_CLK) || 538 (MC_CGM_MUXn_CSS_SWTRG(css) == MC_CGM_MUXn_CSS_SWTRG_SAFE_CLK_INACTIVE)) && 539 ((MC_CGM_MUXn_CSS_SAFE_SW & css) != 0U)) { 540 return 0; 541 } 542 543 ERROR("The switch of mux %" PRIu32 " (CGM=%lu) to safe clock failed\n", 544 mux, cgm_addr); 545 } 546 547 return -EINVAL; 548 } 549 550 static int enable_cgm_mux(const struct s32cc_clkmux *mux, 551 const struct s32cc_clk_drv *drv) 552 { 553 uintptr_t cgm_addr = UL(0x0); 554 uint32_t mux_hw_clk; 555 int ret; 556 557 ret = get_base_addr(mux->module, drv, &cgm_addr); 558 if (ret != 0) { 559 return ret; 560 } 561 562 mux_hw_clk = (uint32_t)S32CC_CLK_ID(mux->source_id); 563 564 return cgm_mux_clk_config(cgm_addr, mux->index, 565 mux_hw_clk, false); 566 } 567 568 static struct s32cc_clk_obj *get_mux_parent(const struct s32cc_clk_obj *module) 569 { 570 const struct s32cc_clkmux *mux = s32cc_obj2clkmux(module); 571 struct s32cc_clk *clk; 572 573 if (mux == NULL) { 574 return NULL; 575 } 576 577 clk = s32cc_get_arch_clk(mux->source_id); 578 if (clk == NULL) { 579 ERROR("Invalid parent (%lu) for mux %" PRIu8 "\n", 580 mux->source_id, mux->index); 581 return NULL; 582 } 583 584 return &clk->desc; 585 } 586 587 static int enable_mux(struct s32cc_clk_obj *module, 588 const struct s32cc_clk_drv *drv, 589 unsigned int depth) 590 { 591 const struct s32cc_clkmux *mux = s32cc_obj2clkmux(module); 592 unsigned int ldepth = depth; 593 const struct s32cc_clk *clk; 594 int ret = 0; 595 596 ret = update_stack_depth(&ldepth); 597 if (ret != 0) { 598 return ret; 599 } 600 601 if (mux == NULL) { 602 return -EINVAL; 603 } 604 605 clk = s32cc_get_arch_clk(mux->source_id); 606 if (clk == NULL) { 607 ERROR("Invalid parent (%lu) for mux %" PRIu8 "\n", 608 mux->source_id, mux->index); 609 return -EINVAL; 610 } 611 612 switch (mux->module) { 613 /* PLL mux will be enabled by PLL setup */ 614 case S32CC_ARM_PLL: 615 case S32CC_PERIPH_PLL: 616 case S32CC_DDR_PLL: 617 break; 618 case S32CC_CGM1: 619 ret = enable_cgm_mux(mux, drv); 620 break; 621 case S32CC_CGM0: 622 ret = enable_cgm_mux(mux, drv); 623 break; 624 case S32CC_CGM5: 625 ret = enable_cgm_mux(mux, drv); 626 break; 627 default: 628 ERROR("Unknown mux parent type: %d\n", mux->module); 629 ret = -EINVAL; 630 break; 631 }; 632 633 return ret; 634 } 635 636 static struct s32cc_clk_obj *get_dfs_parent(const struct s32cc_clk_obj *module) 637 { 638 const struct s32cc_dfs *dfs = s32cc_obj2dfs(module); 639 640 if (dfs->parent == NULL) { 641 ERROR("Failed to identify DFS's parent\n"); 642 } 643 644 return dfs->parent; 645 } 646 647 static int enable_dfs(struct s32cc_clk_obj *module, 648 const struct s32cc_clk_drv *drv, 649 unsigned int depth) 650 { 651 unsigned int ldepth = depth; 652 int ret = 0; 653 654 ret = update_stack_depth(&ldepth); 655 if (ret != 0) { 656 return ret; 657 } 658 659 return 0; 660 } 661 662 static int get_dfs_freq(const struct s32cc_clk_obj *module, 663 const struct s32cc_clk_drv *drv, 664 unsigned long *rate, unsigned int depth) 665 { 666 const struct s32cc_dfs *dfs = s32cc_obj2dfs(module); 667 unsigned int ldepth = depth; 668 uintptr_t dfs_addr; 669 int ret; 670 671 ret = update_stack_depth(&ldepth); 672 if (ret != 0) { 673 return ret; 674 } 675 676 ret = get_base_addr(dfs->instance, drv, &dfs_addr); 677 if (ret != 0) { 678 ERROR("Failed to detect the DFS instance\n"); 679 return ret; 680 } 681 682 return get_module_rate(dfs->parent, drv, rate, ldepth); 683 } 684 685 static struct s32cc_dfs *get_div_dfs(const struct s32cc_dfs_div *dfs_div) 686 { 687 const struct s32cc_clk_obj *parent = dfs_div->parent; 688 689 if (parent->type != s32cc_dfs_t) { 690 ERROR("DFS DIV doesn't have a DFS as parent\n"); 691 return NULL; 692 } 693 694 return s32cc_obj2dfs(parent); 695 } 696 697 static struct s32cc_pll *dfsdiv2pll(const struct s32cc_dfs_div *dfs_div) 698 { 699 const struct s32cc_clk_obj *parent; 700 const struct s32cc_dfs *dfs; 701 702 dfs = get_div_dfs(dfs_div); 703 if (dfs == NULL) { 704 return NULL; 705 } 706 707 parent = dfs->parent; 708 if (parent->type != s32cc_pll_t) { 709 return NULL; 710 } 711 712 return s32cc_obj2pll(parent); 713 } 714 715 static int get_dfs_mfi_mfn(unsigned long dfs_freq, const struct s32cc_dfs_div *dfs_div, 716 uint32_t *mfi, uint32_t *mfn) 717 { 718 uint64_t factor64, tmp64, ofreq; 719 uint32_t factor32; 720 721 unsigned long in = dfs_freq; 722 unsigned long out = dfs_div->freq; 723 724 /** 725 * factor = (IN / OUT) / 2 726 * MFI = integer(factor) 727 * MFN = (factor - MFI) * 36 728 */ 729 factor64 = ((((uint64_t)in) * FP_PRECISION) / ((uint64_t)out)) / 2ULL; 730 tmp64 = factor64 / FP_PRECISION; 731 if (tmp64 > UINT32_MAX) { 732 return -EINVAL; 733 } 734 735 factor32 = (uint32_t)tmp64; 736 *mfi = factor32; 737 738 tmp64 = ((factor64 - ((uint64_t)*mfi * FP_PRECISION)) * 36UL) / FP_PRECISION; 739 if (tmp64 > UINT32_MAX) { 740 return -EINVAL; 741 } 742 743 *mfn = (uint32_t)tmp64; 744 745 /* div_freq = in / (2 * (*mfi + *mfn / 36.0)) */ 746 factor64 = (((uint64_t)*mfn) * FP_PRECISION) / 36ULL; 747 factor64 += ((uint64_t)*mfi) * FP_PRECISION; 748 factor64 *= 2ULL; 749 ofreq = (((uint64_t)in) * FP_PRECISION) / factor64; 750 751 if (ofreq != dfs_div->freq) { 752 ERROR("Failed to find MFI and MFN settings for DFS DIV freq %lu\n", 753 dfs_div->freq); 754 ERROR("Nearest freq = %" PRIx64 "\n", ofreq); 755 return -EINVAL; 756 } 757 758 return 0; 759 } 760 761 static int init_dfs_port(uintptr_t dfs_addr, uint32_t port, 762 uint32_t mfi, uint32_t mfn) 763 { 764 uint32_t portsr, portolsr; 765 uint32_t mask, old_mfi, old_mfn; 766 uint32_t dvport; 767 bool init_dfs; 768 769 dvport = mmio_read_32(DFS_DVPORTn(dfs_addr, port)); 770 771 old_mfi = DFS_DVPORTn_MFI(dvport); 772 old_mfn = DFS_DVPORTn_MFN(dvport); 773 774 portsr = mmio_read_32(DFS_PORTSR(dfs_addr)); 775 portolsr = mmio_read_32(DFS_PORTOLSR(dfs_addr)); 776 777 /* Skip configuration if it's not needed */ 778 if (((portsr & BIT_32(port)) != 0U) && 779 ((portolsr & BIT_32(port)) == 0U) && 780 (mfi == old_mfi) && (mfn == old_mfn)) { 781 return 0; 782 } 783 784 init_dfs = (portsr == 0U); 785 786 if (init_dfs) { 787 mask = DFS_PORTRESET_MASK; 788 } else { 789 mask = DFS_PORTRESET_SET(BIT_32(port)); 790 } 791 792 mmio_write_32(DFS_PORTOLSR(dfs_addr), mask); 793 mmio_write_32(DFS_PORTRESET(dfs_addr), mask); 794 795 while ((mmio_read_32(DFS_PORTSR(dfs_addr)) & mask) != 0U) { 796 } 797 798 if (init_dfs) { 799 mmio_write_32(DFS_CTL(dfs_addr), DFS_CTL_RESET); 800 } 801 802 mmio_write_32(DFS_DVPORTn(dfs_addr, port), 803 DFS_DVPORTn_MFI_SET(mfi) | DFS_DVPORTn_MFN_SET(mfn)); 804 805 if (init_dfs) { 806 /* DFS clk enable programming */ 807 mmio_clrbits_32(DFS_CTL(dfs_addr), DFS_CTL_RESET); 808 } 809 810 mmio_clrbits_32(DFS_PORTRESET(dfs_addr), BIT_32(port)); 811 812 while ((mmio_read_32(DFS_PORTSR(dfs_addr)) & BIT_32(port)) != BIT_32(port)) { 813 } 814 815 portolsr = mmio_read_32(DFS_PORTOLSR(dfs_addr)); 816 if ((portolsr & DFS_PORTOLSR_LOL(port)) != 0U) { 817 ERROR("Failed to lock DFS divider\n"); 818 return -EINVAL; 819 } 820 821 return 0; 822 } 823 824 static struct s32cc_clk_obj * 825 get_dfs_div_parent(const struct s32cc_clk_obj *module) 826 { 827 const struct s32cc_dfs_div *dfs_div = s32cc_obj2dfsdiv(module); 828 829 if (dfs_div->parent == NULL) { 830 ERROR("Failed to identify DFS divider's parent\n"); 831 } 832 833 return dfs_div->parent; 834 } 835 836 static int enable_dfs_div(struct s32cc_clk_obj *module, 837 const struct s32cc_clk_drv *drv, 838 unsigned int depth) 839 { 840 const struct s32cc_dfs_div *dfs_div = s32cc_obj2dfsdiv(module); 841 unsigned int ldepth = depth; 842 const struct s32cc_pll *pll; 843 const struct s32cc_dfs *dfs; 844 uintptr_t dfs_addr = 0UL; 845 uint32_t mfi, mfn; 846 int ret = 0; 847 848 ret = update_stack_depth(&ldepth); 849 if (ret != 0) { 850 return ret; 851 } 852 853 dfs = get_div_dfs(dfs_div); 854 if (dfs == NULL) { 855 return -EINVAL; 856 } 857 858 pll = dfsdiv2pll(dfs_div); 859 if (pll == NULL) { 860 ERROR("Failed to identify DFS divider's parent\n"); 861 return -EINVAL; 862 } 863 864 ret = get_base_addr(dfs->instance, drv, &dfs_addr); 865 if ((ret != 0) || (dfs_addr == 0UL)) { 866 return -EINVAL; 867 } 868 869 ret = get_dfs_mfi_mfn(pll->vco_freq, dfs_div, &mfi, &mfn); 870 if (ret != 0) { 871 return -EINVAL; 872 } 873 874 return init_dfs_port(dfs_addr, dfs_div->index, mfi, mfn); 875 } 876 877 typedef int (*enable_clk_t)(struct s32cc_clk_obj *module, 878 const struct s32cc_clk_drv *drv, 879 unsigned int depth); 880 881 static int enable_part(struct s32cc_clk_obj *module, 882 const struct s32cc_clk_drv *drv, 883 unsigned int depth) 884 { 885 const struct s32cc_part *part = s32cc_obj2part(module); 886 uint32_t part_no = part->partition_id; 887 888 if ((drv->mc_me == 0UL) || (drv->mc_rgm == 0UL) || (drv->rdc == 0UL)) { 889 return -EINVAL; 890 } 891 892 return mc_me_enable_partition(drv->mc_me, drv->mc_rgm, drv->rdc, part_no); 893 } 894 895 static int enable_part_block(struct s32cc_clk_obj *module, 896 const struct s32cc_clk_drv *drv, 897 unsigned int depth) 898 { 899 const struct s32cc_part_block *block = s32cc_obj2partblock(module); 900 const struct s32cc_part *part = block->part; 901 uint32_t part_no = part->partition_id; 902 unsigned int ldepth = depth; 903 uint32_t cofb; 904 int ret; 905 906 ret = update_stack_depth(&ldepth); 907 if (ret != 0) { 908 return ret; 909 } 910 911 if ((block->block >= s32cc_part_block0) && 912 (block->block <= s32cc_part_block15)) { 913 cofb = (uint32_t)block->block - (uint32_t)s32cc_part_block0; 914 mc_me_enable_part_cofb(drv->mc_me, part_no, cofb, block->status); 915 } else { 916 ERROR("Unknown partition block type: %d\n", block->block); 917 return -EINVAL; 918 } 919 920 return 0; 921 } 922 923 static struct s32cc_clk_obj * 924 get_part_block_parent(const struct s32cc_clk_obj *module) 925 { 926 const struct s32cc_part_block *block = s32cc_obj2partblock(module); 927 928 return &block->part->desc; 929 } 930 931 static int enable_module_with_refcount(struct s32cc_clk_obj *module, 932 const struct s32cc_clk_drv *drv, 933 unsigned int depth); 934 935 static int enable_part_block_link(struct s32cc_clk_obj *module, 936 const struct s32cc_clk_drv *drv, 937 unsigned int depth) 938 { 939 const struct s32cc_part_block_link *link = s32cc_obj2partblocklink(module); 940 struct s32cc_part_block *block = link->block; 941 unsigned int ldepth = depth; 942 int ret; 943 944 ret = update_stack_depth(&ldepth); 945 if (ret != 0) { 946 return ret; 947 } 948 949 /* Move the enablement algorithm to partition tree */ 950 return enable_module_with_refcount(&block->desc, drv, ldepth); 951 } 952 953 static struct s32cc_clk_obj * 954 get_part_block_link_parent(const struct s32cc_clk_obj *module) 955 { 956 const struct s32cc_part_block_link *link = s32cc_obj2partblocklink(module); 957 958 return link->parent; 959 } 960 961 static int no_enable(struct s32cc_clk_obj *module, 962 const struct s32cc_clk_drv *drv, 963 unsigned int depth) 964 { 965 return 0; 966 } 967 968 static int exec_cb_with_refcount(enable_clk_t en_cb, struct s32cc_clk_obj *mod, 969 const struct s32cc_clk_drv *drv, bool leaf_node, 970 unsigned int depth) 971 { 972 unsigned int ldepth = depth; 973 int ret = 0; 974 975 if (mod == NULL) { 976 return 0; 977 } 978 979 ret = update_stack_depth(&ldepth); 980 if (ret != 0) { 981 return ret; 982 } 983 984 /* Refcount will be updated as part of the recursivity */ 985 if (leaf_node) { 986 return en_cb(mod, drv, ldepth); 987 } 988 989 if (mod->refcount == 0U) { 990 ret = en_cb(mod, drv, ldepth); 991 } 992 993 if (ret == 0) { 994 mod->refcount++; 995 } 996 997 return ret; 998 } 999 1000 static struct s32cc_clk_obj *get_module_parent(const struct s32cc_clk_obj *module); 1001 1002 static int enable_module(struct s32cc_clk_obj *module, 1003 const struct s32cc_clk_drv *drv, 1004 unsigned int depth) 1005 { 1006 struct s32cc_clk_obj *parent = get_module_parent(module); 1007 static const enable_clk_t enable_clbs[12] = { 1008 [s32cc_clk_t] = no_enable, 1009 [s32cc_osc_t] = enable_osc, 1010 [s32cc_pll_t] = enable_pll, 1011 [s32cc_pll_out_div_t] = enable_pll_div, 1012 [s32cc_clkmux_t] = enable_mux, 1013 [s32cc_shared_clkmux_t] = enable_mux, 1014 [s32cc_dfs_t] = enable_dfs, 1015 [s32cc_dfs_div_t] = enable_dfs_div, 1016 [s32cc_part_t] = enable_part, 1017 [s32cc_part_block_t] = enable_part_block, 1018 [s32cc_part_block_link_t] = enable_part_block_link, 1019 }; 1020 unsigned int ldepth = depth; 1021 uint32_t index; 1022 int ret = 0; 1023 1024 ret = update_stack_depth(&ldepth); 1025 if (ret != 0) { 1026 return ret; 1027 } 1028 1029 if (drv == NULL) { 1030 return -EINVAL; 1031 } 1032 1033 index = (uint32_t)module->type; 1034 1035 if (index >= ARRAY_SIZE(enable_clbs)) { 1036 ERROR("Undefined module type: %d\n", module->type); 1037 return -EINVAL; 1038 } 1039 1040 if (enable_clbs[index] == NULL) { 1041 ERROR("Undefined callback for the clock type: %d\n", 1042 module->type); 1043 return -EINVAL; 1044 } 1045 1046 parent = get_module_parent(module); 1047 1048 ret = exec_cb_with_refcount(enable_module, parent, drv, 1049 false, ldepth); 1050 if (ret != 0) { 1051 return ret; 1052 } 1053 1054 ret = exec_cb_with_refcount(enable_clbs[index], module, drv, 1055 true, ldepth); 1056 if (ret != 0) { 1057 return ret; 1058 } 1059 1060 return ret; 1061 } 1062 1063 static int enable_module_with_refcount(struct s32cc_clk_obj *module, 1064 const struct s32cc_clk_drv *drv, 1065 unsigned int depth) 1066 { 1067 return exec_cb_with_refcount(enable_module, module, drv, false, depth); 1068 } 1069 1070 static int s32cc_clk_enable(unsigned long id) 1071 { 1072 const struct s32cc_clk_drv *drv = get_drv(); 1073 unsigned int depth = MAX_STACK_DEPTH; 1074 struct s32cc_clk *clk; 1075 1076 clk = s32cc_get_arch_clk(id); 1077 if (clk == NULL) { 1078 return -EINVAL; 1079 } 1080 1081 return enable_module_with_refcount(&clk->desc, drv, depth); 1082 } 1083 1084 static void s32cc_clk_disable(unsigned long id) 1085 { 1086 } 1087 1088 static bool s32cc_clk_is_enabled(unsigned long id) 1089 { 1090 return false; 1091 } 1092 1093 static int set_osc_freq(const struct s32cc_clk_obj *module, unsigned long rate, 1094 unsigned long *orate, unsigned int *depth) 1095 { 1096 struct s32cc_osc *osc = s32cc_obj2osc(module); 1097 int ret; 1098 1099 ret = update_stack_depth(depth); 1100 if (ret != 0) { 1101 return ret; 1102 } 1103 1104 if ((osc->freq != 0UL) && (rate != osc->freq)) { 1105 ERROR("Already initialized oscillator. freq = %lu\n", 1106 osc->freq); 1107 return -EINVAL; 1108 } 1109 1110 osc->freq = rate; 1111 *orate = osc->freq; 1112 1113 return 0; 1114 } 1115 1116 static int get_osc_freq(const struct s32cc_clk_obj *module, 1117 const struct s32cc_clk_drv *drv, 1118 unsigned long *rate, unsigned int depth) 1119 { 1120 const struct s32cc_osc *osc = s32cc_obj2osc(module); 1121 unsigned int ldepth = depth; 1122 int ret; 1123 1124 ret = update_stack_depth(&ldepth); 1125 if (ret != 0) { 1126 return ret; 1127 } 1128 1129 if (osc->freq == 0UL) { 1130 ERROR("Uninitialized oscillator\n"); 1131 return -EINVAL; 1132 } 1133 1134 *rate = osc->freq; 1135 1136 return 0; 1137 } 1138 1139 static int set_clk_freq(const struct s32cc_clk_obj *module, unsigned long rate, 1140 unsigned long *orate, unsigned int *depth) 1141 { 1142 const struct s32cc_clk *clk = s32cc_obj2clk(module); 1143 int ret; 1144 1145 ret = update_stack_depth(depth); 1146 if (ret != 0) { 1147 return ret; 1148 } 1149 1150 if ((clk->min_freq != 0UL) && (clk->max_freq != 0UL) && 1151 ((rate < clk->min_freq) || (rate > clk->max_freq))) { 1152 ERROR("%lu frequency is out of the allowed range: [%lu:%lu]\n", 1153 rate, clk->min_freq, clk->max_freq); 1154 return -EINVAL; 1155 } 1156 1157 if (clk->module != NULL) { 1158 return set_module_rate(clk->module, rate, orate, depth); 1159 } 1160 1161 if (clk->pclock != NULL) { 1162 return set_clk_freq(&clk->pclock->desc, rate, orate, depth); 1163 } 1164 1165 return -EINVAL; 1166 } 1167 1168 static int get_clk_freq(const struct s32cc_clk_obj *module, 1169 const struct s32cc_clk_drv *drv, unsigned long *rate, 1170 unsigned int depth) 1171 { 1172 const struct s32cc_clk *clk = s32cc_obj2clk(module); 1173 unsigned int ldepth = depth; 1174 int ret; 1175 1176 ret = update_stack_depth(&ldepth); 1177 if (ret != 0) { 1178 return ret; 1179 } 1180 1181 if (clk == NULL) { 1182 ERROR("Invalid clock\n"); 1183 return -EINVAL; 1184 } 1185 1186 if (clk->module != NULL) { 1187 return get_module_rate(clk->module, drv, rate, ldepth); 1188 } 1189 1190 if (clk->pclock == NULL) { 1191 ERROR("Invalid clock parent\n"); 1192 return -EINVAL; 1193 } 1194 1195 return get_clk_freq(&clk->pclock->desc, drv, rate, ldepth); 1196 } 1197 1198 static int set_pll_freq(const struct s32cc_clk_obj *module, unsigned long rate, 1199 unsigned long *orate, unsigned int *depth) 1200 { 1201 struct s32cc_pll *pll = s32cc_obj2pll(module); 1202 int ret; 1203 1204 ret = update_stack_depth(depth); 1205 if (ret != 0) { 1206 return ret; 1207 } 1208 1209 if ((pll->vco_freq != 0UL) && (pll->vco_freq != rate)) { 1210 ERROR("PLL frequency was already set\n"); 1211 return -EINVAL; 1212 } 1213 1214 pll->vco_freq = rate; 1215 *orate = pll->vco_freq; 1216 1217 return 0; 1218 } 1219 1220 static int get_pll_freq(const struct s32cc_clk_obj *module, 1221 const struct s32cc_clk_drv *drv, 1222 unsigned long *rate, unsigned int depth) 1223 { 1224 const struct s32cc_pll *pll = s32cc_obj2pll(module); 1225 const struct s32cc_clk *source; 1226 uint32_t mfi, mfn, rdiv, plldv; 1227 unsigned long prate, clk_src; 1228 unsigned int ldepth = depth; 1229 uintptr_t pll_addr = 0UL; 1230 uint64_t t1, t2; 1231 uint32_t pllpd; 1232 int ret; 1233 1234 ret = update_stack_depth(&ldepth); 1235 if (ret != 0) { 1236 return ret; 1237 } 1238 1239 ret = get_base_addr(pll->instance, drv, &pll_addr); 1240 if (ret != 0) { 1241 ERROR("Failed to detect PLL instance\n"); 1242 return ret; 1243 } 1244 1245 /* Disabled PLL */ 1246 pllpd = mmio_read_32(PLLDIG_PLLCR(pll_addr)) & PLLDIG_PLLCR_PLLPD; 1247 if (pllpd != 0U) { 1248 *rate = pll->vco_freq; 1249 return 0; 1250 } 1251 1252 clk_src = mmio_read_32(PLLDIG_PLLCLKMUX(pll_addr)); 1253 switch (clk_src) { 1254 case 0: 1255 clk_src = S32CC_CLK_FIRC; 1256 break; 1257 case 1: 1258 clk_src = S32CC_CLK_FXOSC; 1259 break; 1260 default: 1261 ERROR("Failed to identify PLL source id %" PRIu64 "\n", clk_src); 1262 return -EINVAL; 1263 }; 1264 1265 source = s32cc_get_arch_clk(clk_src); 1266 if (source == NULL) { 1267 ERROR("Failed to get PLL source clock\n"); 1268 return -EINVAL; 1269 } 1270 1271 ret = get_module_rate(&source->desc, drv, &prate, ldepth); 1272 if (ret != 0) { 1273 ERROR("Failed to get PLL's parent frequency\n"); 1274 return ret; 1275 } 1276 1277 plldv = mmio_read_32(PLLDIG_PLLDV(pll_addr)); 1278 mfi = PLLDIG_PLLDV_MFI(plldv); 1279 rdiv = PLLDIG_PLLDV_RDIV(plldv); 1280 if (rdiv == 0U) { 1281 rdiv = 1; 1282 } 1283 1284 /* Frac-N mode */ 1285 mfn = PLLDIG_PLLFD_MFN_SET(mmio_read_32(PLLDIG_PLLFD(pll_addr))); 1286 1287 /* PLL VCO frequency in Fractional mode when PLLDV[RDIV] is not 0 */ 1288 t1 = prate / rdiv; 1289 t2 = (mfi * FP_PRECISION) + (mfn * FP_PRECISION / 18432U); 1290 1291 *rate = t1 * t2 / FP_PRECISION; 1292 1293 return 0; 1294 } 1295 1296 static int set_pll_div_freq(const struct s32cc_clk_obj *module, unsigned long rate, 1297 unsigned long *orate, unsigned int *depth) 1298 { 1299 struct s32cc_pll_out_div *pdiv = s32cc_obj2plldiv(module); 1300 const struct s32cc_pll *pll; 1301 unsigned long prate, dc; 1302 int ret; 1303 1304 ret = update_stack_depth(depth); 1305 if (ret != 0) { 1306 return ret; 1307 } 1308 1309 if (pdiv->parent == NULL) { 1310 ERROR("Failed to identify PLL divider's parent\n"); 1311 return -EINVAL; 1312 } 1313 1314 pll = s32cc_obj2pll(pdiv->parent); 1315 if (pll == NULL) { 1316 ERROR("The parent of the PLL DIV is invalid\n"); 1317 return -EINVAL; 1318 } 1319 1320 prate = pll->vco_freq; 1321 1322 /** 1323 * The PLL is not initialized yet, so let's take a risk 1324 * and accept the proposed rate. 1325 */ 1326 if (prate == 0UL) { 1327 pdiv->freq = rate; 1328 *orate = rate; 1329 return 0; 1330 } 1331 1332 /* Decline in case the rate cannot fit PLL's requirements. */ 1333 dc = prate / rate; 1334 if ((prate / dc) != rate) { 1335 return -EINVAL; 1336 } 1337 1338 pdiv->freq = rate; 1339 *orate = pdiv->freq; 1340 1341 return 0; 1342 } 1343 1344 static int get_pll_div_freq(const struct s32cc_clk_obj *module, 1345 const struct s32cc_clk_drv *drv, 1346 unsigned long *rate, unsigned int depth) 1347 { 1348 const struct s32cc_pll_out_div *pdiv = s32cc_obj2plldiv(module); 1349 const struct s32cc_pll *pll; 1350 unsigned int ldepth = depth; 1351 uintptr_t pll_addr = 0UL; 1352 unsigned long pfreq; 1353 uint32_t pllodiv; 1354 uint32_t dc; 1355 int ret; 1356 1357 ret = update_stack_depth(&ldepth); 1358 if (ret != 0) { 1359 return ret; 1360 } 1361 1362 pll = get_div_pll(pdiv); 1363 if (pll == NULL) { 1364 ERROR("The parent of the PLL DIV is invalid\n"); 1365 return -EINVAL; 1366 } 1367 1368 ret = get_base_addr(pll->instance, drv, &pll_addr); 1369 if (ret != 0) { 1370 ERROR("Failed to detect PLL instance\n"); 1371 return -EINVAL; 1372 } 1373 1374 ret = get_module_rate(pdiv->parent, drv, &pfreq, ldepth); 1375 if (ret != 0) { 1376 ERROR("Failed to get the frequency of PLL %" PRIxPTR "\n", 1377 pll_addr); 1378 return ret; 1379 } 1380 1381 pllodiv = mmio_read_32(PLLDIG_PLLODIV(pll_addr, pdiv->index)); 1382 1383 /* Disabled module */ 1384 if ((pllodiv & PLLDIG_PLLODIV_DE) == 0U) { 1385 *rate = pdiv->freq; 1386 return 0; 1387 } 1388 1389 dc = PLLDIG_PLLODIV_DIV(pllodiv); 1390 *rate = (pfreq * FP_PRECISION) / (dc + 1U) / FP_PRECISION; 1391 1392 return 0; 1393 } 1394 1395 static int set_fixed_div_freq(const struct s32cc_clk_obj *module, unsigned long rate, 1396 unsigned long *orate, unsigned int *depth) 1397 { 1398 const struct s32cc_fixed_div *fdiv = s32cc_obj2fixeddiv(module); 1399 int ret; 1400 1401 ret = update_stack_depth(depth); 1402 if (ret != 0) { 1403 return ret; 1404 } 1405 1406 if (fdiv->parent == NULL) { 1407 ERROR("The divider doesn't have a valid parent\b"); 1408 return -EINVAL; 1409 } 1410 1411 ret = set_module_rate(fdiv->parent, rate * fdiv->rate_div, orate, depth); 1412 1413 /* Update the output rate based on the parent's rate */ 1414 *orate /= fdiv->rate_div; 1415 1416 return ret; 1417 } 1418 1419 static int get_fixed_div_freq(const struct s32cc_clk_obj *module, 1420 const struct s32cc_clk_drv *drv, 1421 unsigned long *rate, unsigned int depth) 1422 { 1423 const struct s32cc_fixed_div *fdiv = s32cc_obj2fixeddiv(module); 1424 unsigned long pfreq; 1425 int ret; 1426 1427 ret = get_module_rate(fdiv->parent, drv, &pfreq, depth); 1428 if (ret != 0) { 1429 return ret; 1430 } 1431 1432 *rate = (pfreq * FP_PRECISION / fdiv->rate_div) / FP_PRECISION; 1433 return 0; 1434 } 1435 1436 static int set_mux_freq(const struct s32cc_clk_obj *module, unsigned long rate, 1437 unsigned long *orate, unsigned int *depth) 1438 { 1439 const struct s32cc_clkmux *mux = s32cc_obj2clkmux(module); 1440 const struct s32cc_clk *clk = s32cc_get_arch_clk(mux->source_id); 1441 int ret; 1442 1443 ret = update_stack_depth(depth); 1444 if (ret != 0) { 1445 return ret; 1446 } 1447 1448 if (clk == NULL) { 1449 ERROR("Mux (id:%" PRIu8 ") without a valid source (%lu)\n", 1450 mux->index, mux->source_id); 1451 return -EINVAL; 1452 } 1453 1454 return set_module_rate(&clk->desc, rate, orate, depth); 1455 } 1456 1457 static int get_mux_freq(const struct s32cc_clk_obj *module, 1458 const struct s32cc_clk_drv *drv, 1459 unsigned long *rate, unsigned int depth) 1460 { 1461 const struct s32cc_clkmux *mux = s32cc_obj2clkmux(module); 1462 const struct s32cc_clk *clk = s32cc_get_arch_clk(mux->source_id); 1463 unsigned int ldepth = depth; 1464 int ret; 1465 1466 ret = update_stack_depth(&ldepth); 1467 if (ret != 0) { 1468 return ret; 1469 } 1470 1471 if (clk == NULL) { 1472 ERROR("Mux (id:%" PRIu8 ") without a valid source (%lu)\n", 1473 mux->index, mux->source_id); 1474 return -EINVAL; 1475 } 1476 1477 return get_clk_freq(&clk->desc, drv, rate, ldepth); 1478 } 1479 1480 static int set_dfs_div_freq(const struct s32cc_clk_obj *module, unsigned long rate, 1481 unsigned long *orate, unsigned int *depth) 1482 { 1483 struct s32cc_dfs_div *dfs_div = s32cc_obj2dfsdiv(module); 1484 const struct s32cc_dfs *dfs; 1485 int ret; 1486 1487 ret = update_stack_depth(depth); 1488 if (ret != 0) { 1489 return ret; 1490 } 1491 1492 if (dfs_div->parent == NULL) { 1493 ERROR("Failed to identify DFS divider's parent\n"); 1494 return -EINVAL; 1495 } 1496 1497 /* Sanity check */ 1498 dfs = s32cc_obj2dfs(dfs_div->parent); 1499 if (dfs->parent == NULL) { 1500 ERROR("Failed to identify DFS's parent\n"); 1501 return -EINVAL; 1502 } 1503 1504 if ((dfs_div->freq != 0U) && (dfs_div->freq != rate)) { 1505 ERROR("DFS DIV frequency was already set to %lu\n", 1506 dfs_div->freq); 1507 return -EINVAL; 1508 } 1509 1510 dfs_div->freq = rate; 1511 *orate = rate; 1512 1513 return ret; 1514 } 1515 1516 static unsigned long compute_dfs_div_freq(unsigned long pfreq, uint32_t mfi, uint32_t mfn) 1517 { 1518 unsigned long freq; 1519 1520 /** 1521 * Formula for input and output clocks of each port divider. 1522 * See 'Digital Frequency Synthesizer' chapter from Reference Manual. 1523 * 1524 * freq = pfreq / (2 * (mfi + mfn / 36.0)); 1525 */ 1526 freq = (mfi * FP_PRECISION) + (mfn * FP_PRECISION / 36UL); 1527 freq *= 2UL; 1528 freq = pfreq * FP_PRECISION / freq; 1529 1530 return freq; 1531 } 1532 1533 static int get_dfs_div_freq(const struct s32cc_clk_obj *module, 1534 const struct s32cc_clk_drv *drv, 1535 unsigned long *rate, unsigned int depth) 1536 { 1537 const struct s32cc_dfs_div *dfs_div = s32cc_obj2dfsdiv(module); 1538 unsigned int ldepth = depth; 1539 const struct s32cc_dfs *dfs; 1540 uint32_t dvport, mfi, mfn; 1541 uintptr_t dfs_addr = 0UL; 1542 unsigned long pfreq; 1543 int ret; 1544 1545 ret = update_stack_depth(&ldepth); 1546 if (ret != 0) { 1547 return ret; 1548 } 1549 1550 dfs = get_div_dfs(dfs_div); 1551 if (dfs == NULL) { 1552 return -EINVAL; 1553 } 1554 1555 ret = get_module_rate(dfs_div->parent, drv, &pfreq, ldepth); 1556 if (ret != 0) { 1557 return ret; 1558 } 1559 1560 ret = get_base_addr(dfs->instance, drv, &dfs_addr); 1561 if (ret != 0) { 1562 ERROR("Failed to detect the DFS instance\n"); 1563 return ret; 1564 } 1565 1566 dvport = mmio_read_32(DFS_DVPORTn(dfs_addr, dfs_div->index)); 1567 1568 mfi = DFS_DVPORTn_MFI(dvport); 1569 mfn = DFS_DVPORTn_MFN(dvport); 1570 1571 /* Disabled port */ 1572 if ((mfi == 0U) && (mfn == 0U)) { 1573 *rate = dfs_div->freq; 1574 return 0; 1575 } 1576 1577 *rate = compute_dfs_div_freq(pfreq, mfi, mfn); 1578 return 0; 1579 } 1580 1581 static int set_module_rate(const struct s32cc_clk_obj *module, 1582 unsigned long rate, unsigned long *orate, 1583 unsigned int *depth) 1584 { 1585 int ret = 0; 1586 1587 ret = update_stack_depth(depth); 1588 if (ret != 0) { 1589 return ret; 1590 } 1591 1592 ret = -EINVAL; 1593 1594 switch (module->type) { 1595 case s32cc_clk_t: 1596 ret = set_clk_freq(module, rate, orate, depth); 1597 break; 1598 case s32cc_osc_t: 1599 ret = set_osc_freq(module, rate, orate, depth); 1600 break; 1601 case s32cc_pll_t: 1602 ret = set_pll_freq(module, rate, orate, depth); 1603 break; 1604 case s32cc_pll_out_div_t: 1605 ret = set_pll_div_freq(module, rate, orate, depth); 1606 break; 1607 case s32cc_fixed_div_t: 1608 ret = set_fixed_div_freq(module, rate, orate, depth); 1609 break; 1610 case s32cc_clkmux_t: 1611 ret = set_mux_freq(module, rate, orate, depth); 1612 break; 1613 case s32cc_shared_clkmux_t: 1614 ret = set_mux_freq(module, rate, orate, depth); 1615 break; 1616 case s32cc_dfs_t: 1617 ERROR("Setting the frequency of a DFS is not allowed!"); 1618 break; 1619 case s32cc_dfs_div_t: 1620 ret = set_dfs_div_freq(module, rate, orate, depth); 1621 break; 1622 default: 1623 break; 1624 } 1625 1626 return ret; 1627 } 1628 1629 static int get_module_rate(const struct s32cc_clk_obj *module, 1630 const struct s32cc_clk_drv *drv, 1631 unsigned long *rate, 1632 unsigned int depth) 1633 { 1634 unsigned int ldepth = depth; 1635 int ret = 0; 1636 1637 ret = update_stack_depth(&ldepth); 1638 if (ret != 0) { 1639 return ret; 1640 } 1641 1642 switch (module->type) { 1643 case s32cc_osc_t: 1644 ret = get_osc_freq(module, drv, rate, ldepth); 1645 break; 1646 case s32cc_clk_t: 1647 ret = get_clk_freq(module, drv, rate, ldepth); 1648 break; 1649 case s32cc_pll_t: 1650 ret = get_pll_freq(module, drv, rate, ldepth); 1651 break; 1652 case s32cc_dfs_t: 1653 ret = get_dfs_freq(module, drv, rate, ldepth); 1654 break; 1655 case s32cc_dfs_div_t: 1656 ret = get_dfs_div_freq(module, drv, rate, ldepth); 1657 break; 1658 case s32cc_fixed_div_t: 1659 ret = get_fixed_div_freq(module, drv, rate, ldepth); 1660 break; 1661 case s32cc_pll_out_div_t: 1662 ret = get_pll_div_freq(module, drv, rate, ldepth); 1663 break; 1664 case s32cc_clkmux_t: 1665 ret = get_mux_freq(module, drv, rate, ldepth); 1666 break; 1667 case s32cc_shared_clkmux_t: 1668 ret = get_mux_freq(module, drv, rate, ldepth); 1669 break; 1670 default: 1671 ret = -EINVAL; 1672 break; 1673 } 1674 1675 return ret; 1676 } 1677 1678 static int s32cc_clk_set_rate(unsigned long id, unsigned long rate, 1679 unsigned long *orate) 1680 { 1681 unsigned int depth = MAX_STACK_DEPTH; 1682 const struct s32cc_clk *clk; 1683 int ret; 1684 1685 clk = s32cc_get_arch_clk(id); 1686 if (clk == NULL) { 1687 return -EINVAL; 1688 } 1689 1690 ret = set_module_rate(&clk->desc, rate, orate, &depth); 1691 if (ret != 0) { 1692 ERROR("Failed to set frequency (%lu MHz) for clock %lu\n", 1693 rate, id); 1694 } 1695 1696 return ret; 1697 } 1698 1699 static unsigned long s32cc_clk_get_rate(unsigned long id) 1700 { 1701 const struct s32cc_clk_drv *drv = get_drv(); 1702 unsigned int depth = MAX_STACK_DEPTH; 1703 const struct s32cc_clk *clk; 1704 unsigned long rate = 0UL; 1705 int ret; 1706 1707 clk = s32cc_get_arch_clk(id); 1708 if (clk == NULL) { 1709 return 0; 1710 } 1711 1712 ret = get_module_rate(&clk->desc, drv, &rate, depth); 1713 if (ret != 0) { 1714 ERROR("Failed to get frequency (%lu MHz) for clock %lu\n", 1715 rate, id); 1716 return 0; 1717 } 1718 1719 return rate; 1720 } 1721 1722 static struct s32cc_clk_obj *get_no_parent(const struct s32cc_clk_obj *module) 1723 { 1724 return NULL; 1725 } 1726 1727 typedef struct s32cc_clk_obj *(*get_parent_clb_t)(const struct s32cc_clk_obj *clk_obj); 1728 1729 static struct s32cc_clk_obj *get_module_parent(const struct s32cc_clk_obj *module) 1730 { 1731 static const get_parent_clb_t parents_clbs[12] = { 1732 [s32cc_clk_t] = get_clk_parent, 1733 [s32cc_osc_t] = get_no_parent, 1734 [s32cc_pll_t] = get_pll_parent, 1735 [s32cc_pll_out_div_t] = get_pll_div_parent, 1736 [s32cc_clkmux_t] = get_mux_parent, 1737 [s32cc_shared_clkmux_t] = get_mux_parent, 1738 [s32cc_dfs_t] = get_dfs_parent, 1739 [s32cc_dfs_div_t] = get_dfs_div_parent, 1740 [s32cc_part_t] = get_no_parent, 1741 [s32cc_part_block_t] = get_part_block_parent, 1742 [s32cc_part_block_link_t] = get_part_block_link_parent, 1743 }; 1744 uint32_t index; 1745 1746 if (module == NULL) { 1747 return NULL; 1748 } 1749 1750 index = (uint32_t)module->type; 1751 1752 if (index >= ARRAY_SIZE(parents_clbs)) { 1753 ERROR("Undefined module type: %d\n", module->type); 1754 return NULL; 1755 } 1756 1757 if (parents_clbs[index] == NULL) { 1758 ERROR("Undefined parent getter for type: %d\n", module->type); 1759 return NULL; 1760 } 1761 1762 return parents_clbs[index](module); 1763 } 1764 1765 static int s32cc_clk_get_parent(unsigned long id) 1766 { 1767 struct s32cc_clk *parent_clk; 1768 const struct s32cc_clk_obj *parent; 1769 const struct s32cc_clk *clk; 1770 unsigned long parent_id; 1771 int ret; 1772 1773 clk = s32cc_get_arch_clk(id); 1774 if (clk == NULL) { 1775 return -EINVAL; 1776 } 1777 1778 parent = get_module_parent(clk->module); 1779 if (parent == NULL) { 1780 return -EINVAL; 1781 } 1782 1783 parent_clk = s32cc_obj2clk(parent); 1784 if (parent_clk == NULL) { 1785 return -EINVAL; 1786 } 1787 1788 ret = s32cc_get_clk_id(parent_clk, &parent_id); 1789 if (ret != 0) { 1790 return ret; 1791 } 1792 1793 if (parent_id > (unsigned long)INT_MAX) { 1794 return -E2BIG; 1795 } 1796 1797 return (int)parent_id; 1798 } 1799 1800 static int s32cc_clk_set_parent(unsigned long id, unsigned long parent_id) 1801 { 1802 const struct s32cc_clk *parent; 1803 const struct s32cc_clk *clk; 1804 bool valid_source = false; 1805 struct s32cc_clkmux *mux; 1806 uint8_t i; 1807 1808 clk = s32cc_get_arch_clk(id); 1809 if (clk == NULL) { 1810 return -EINVAL; 1811 } 1812 1813 parent = s32cc_get_arch_clk(parent_id); 1814 if (parent == NULL) { 1815 return -EINVAL; 1816 } 1817 1818 if (!is_s32cc_clk_mux(clk)) { 1819 ERROR("Clock %lu is not a mux\n", id); 1820 return -EINVAL; 1821 } 1822 1823 mux = s32cc_clk2mux(clk); 1824 if (mux == NULL) { 1825 ERROR("Failed to cast clock %lu to clock mux\n", id); 1826 return -EINVAL; 1827 } 1828 1829 for (i = 0; i < mux->nclks; i++) { 1830 if (mux->clkids[i] == parent_id) { 1831 valid_source = true; 1832 break; 1833 } 1834 } 1835 1836 if (!valid_source) { 1837 ERROR("Clock %lu is not a valid clock for mux %lu\n", 1838 parent_id, id); 1839 return -EINVAL; 1840 } 1841 1842 mux->source_id = parent_id; 1843 1844 return 0; 1845 } 1846 1847 static int s32cc_clk_mmap_regs(const struct s32cc_clk_drv *drv) 1848 { 1849 const uintptr_t base_addrs[11] = { 1850 drv->fxosc_base, 1851 drv->armpll_base, 1852 drv->periphpll_base, 1853 drv->armdfs_base, 1854 drv->cgm0_base, 1855 drv->cgm1_base, 1856 drv->cgm5_base, 1857 drv->ddrpll_base, 1858 drv->mc_me, 1859 drv->mc_rgm, 1860 drv->rdc, 1861 }; 1862 size_t i; 1863 int ret; 1864 1865 for (i = 0U; i < ARRAY_SIZE(base_addrs); i++) { 1866 ret = mmap_add_dynamic_region(base_addrs[i], base_addrs[i], 1867 PAGE_SIZE, 1868 MT_DEVICE | MT_RW | MT_SECURE); 1869 if (ret != 0) { 1870 ERROR("Failed to map clock module 0x%" PRIuPTR "\n", 1871 base_addrs[i]); 1872 return ret; 1873 } 1874 } 1875 1876 return 0; 1877 } 1878 1879 int s32cc_clk_register_drv(bool mmap_regs) 1880 { 1881 static const struct clk_ops s32cc_clk_ops = { 1882 .enable = s32cc_clk_enable, 1883 .disable = s32cc_clk_disable, 1884 .is_enabled = s32cc_clk_is_enabled, 1885 .get_rate = s32cc_clk_get_rate, 1886 .set_rate = s32cc_clk_set_rate, 1887 .get_parent = s32cc_clk_get_parent, 1888 .set_parent = s32cc_clk_set_parent, 1889 }; 1890 const struct s32cc_clk_drv *drv; 1891 1892 clk_register(&s32cc_clk_ops); 1893 1894 drv = get_drv(); 1895 if (drv == NULL) { 1896 return -EINVAL; 1897 } 1898 1899 if (mmap_regs) { 1900 return s32cc_clk_mmap_regs(drv); 1901 } 1902 1903 return 0; 1904 } 1905 1906