| 9e4609f1 | 24-Apr-2019 |
Christoph Müllner <christophm30@gmail.com> |
build_macros: Add mechanism to prevent bin generation.
On certain platforms it does not make sense to generate
TF-A binary images. For example a platform could make use of serveral
memory areas, whi
build_macros: Add mechanism to prevent bin generation.
On certain platforms it does not make sense to generate
TF-A binary images. For example a platform could make use of serveral
memory areas, which are non-continuous and the resulting binary
therefore would suffer from the padding-bytes.
Typically these platforms use the ELF image.
This patch introduces a variable DISABLE_BIN_GENERATION, which
can be set to '1' in the platform makefile to prevent the binary
generation.
Signed-off-by: Christoph Müllner <christophm30@gmail.com>
Change-Id: I62948e88bab685bb055fe6167d9660d14e604462
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|
| 29162843 | 30-Apr-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge changes from topic "lm/stack_protector" into integration
* changes:
juno: Add security sources for tsp-juno
Add support for default stack-protector flag |
| fd7b287c | 26-Mar-2019 |
Louis Mayencourt <louis.mayencourt@arm.com> |
Add support for default stack-protector flag
The current stack-protector support is for none, "strong" or "all".
The default use of the flag enables the stack-protection to all
functions that declar
Add support for default stack-protector flag
The current stack-protector support is for none, "strong" or "all".
The default use of the flag enables the stack-protection to all
functions that declare a character array of eight bytes or more in
length on their stack.
This option can be tuned with the --param=ssp-buffer-size=N option.
Change-Id: I11ad9568187d58de1b962b8ae04edd1dc8578fb0
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
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|
| f15e7adb | 29-Apr-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge changes from topic "avenger96" into integration
* changes:
fdts: Fix DTC warnings for STM32MP1 platform
docs: plat: stm32mp1: Document the usage of DTB_FILE_NAME variable
stm32mp1: Add A
Merge changes from topic "avenger96" into integration
* changes:
fdts: Fix DTC warnings for STM32MP1 platform
docs: plat: stm32mp1: Document the usage of DTB_FILE_NAME variable
stm32mp1: Add Avenger96 board support
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|
| f657fa99 | 26-Apr-2019 |
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> |
docs: plat: stm32mp1: Document the usage of DTB_FILE_NAME variable
Since STM32MP1 platform supports different boards, it is necessary
to build for a particular board. With the current instructions,
docs: plat: stm32mp1: Document the usage of DTB_FILE_NAME variable
Since STM32MP1 platform supports different boards, it is necessary
to build for a particular board. With the current instructions, the
user has to modify the DTB_FILE_NAME variable in platform.mk for
building for a particular board, but this can be avoided by passing
the appropriate board DTB name via DTB_FILE_NAME make variable.
Hence document the same in platform doc.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Change-Id: I16797e7256c7eb699a7b8846356fe430d0fe0aa1
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|
| 8742f857 | 26-Apr-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge changes from topic "rk3288" into integration
* changes:
rockchip: document platform
rockchip: add support for rk3288
rockchip: add common aarch32 support
rockchip: rk3328: drop double
Merge changes from topic "rk3288" into integration
* changes:
rockchip: document platform
rockchip: add support for rk3288
rockchip: add common aarch32 support
rockchip: rk3328: drop double declaration of entry_point storage
rockchip: Allow socs with undefined wfe check bits
rockchip: move pmusram assembler code to a aarch64 subdir
sp_min: allow inclusion of a platform-specific linker script
sp_min: make sp_min_warm_entrypoint public
drivers: ti: uart: add a aarch32 variant
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| 55617251 | 19-Apr-2019 |
Heiko Stuebner <heiko@sntech.de> |
rockchip: document platform
This adds a rockchip.rst to docs/plat documenting the general
approach to using the Rockchip ATF platforms together with the
supported bootloaders and also adds myself as
rockchip: document platform
This adds a rockchip.rst to docs/plat documenting the general
approach to using the Rockchip ATF platforms together with the
supported bootloaders and also adds myself as maintainer after
making sure Tony Xie is ok with that.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Change-Id: Idce53d15eff4ac6de05bbb35d86e57ed50d0cbb9
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| c1491eba | 24-Apr-2019 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Doc: Update link to TBBR-CLIENT specification
Change-Id: Iafa79b6f7891d3eebec9908a8f7725131202beb3
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com> |
| d87af648 | 23-Apr-2019 |
Antonio Niño Díaz <antonio.ninodiaz@arm.com> |
Merge "Cortex A9: Fix typo in errata 794073 workaround" into integration |
| 1989a19c | 19-Apr-2019 |
Yann Gautier <yann.gautier@st.com> |
stm32mp1: add OP-TEE support
Support booting OP-TEE as BL32 boot stage and secure runtime
service.
OP-TEE executes in internal RAM and uses a secure DDR area to store
the pager pagestore. Memory ma
stm32mp1: add OP-TEE support
Support booting OP-TEE as BL32 boot stage and secure runtime
service.
OP-TEE executes in internal RAM and uses a secure DDR area to store
the pager pagestore. Memory mapping and TZC are configured accordingly
prior OP-TEE boot. OP-TEE image is expected in OP-TEE v2 format where
a header file describes the effective boot images. This change
post processes header file content to get OP-TEE load addresses
and set OP-TEE boot arguments.
Change-Id: I02ef8b915e4be3e95b27029357d799d70e01cd44
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
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|
| b4e9ab9c | 18-Apr-2019 |
Louis Mayencourt <louis.mayencourt@arm.com> |
Cortex A9: Fix typo in errata 794073 workaround
Change-Id: I22568caf83b9846cd7b59241fcec34a395825399
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com> |
| 0e985d70 | 09-Apr-2019 |
Louis Mayencourt <louis.mayencourt@arm.com> |
DSU: Implement workaround for errata 798953
Under certain near idle conditions, DSU may miss response transfers on
the ACE master or Peripheral port, leading to deadlock. This workaround
disables hi
DSU: Implement workaround for errata 798953
Under certain near idle conditions, DSU may miss response transfers on
the ACE master or Peripheral port, leading to deadlock. This workaround
disables high-level clock gating of the DSU to prevent this.
Change-Id: I820911d61570bacb38dd325b3519bc8d12caa14b
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
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| cba71b70 | 05-Apr-2019 |
Louis Mayencourt <louis.mayencourt@arm.com> |
Cortex-A35: Implement workaround for errata 855472
Under specific conditions, the processor might issue an eviction and an
L2 cache clean operation to the interconnect in the wrong order. Set
the CP
Cortex-A35: Implement workaround for errata 855472
Under specific conditions, the processor might issue an eviction and an
L2 cache clean operation to the interconnect in the wrong order. Set
the CPUACTLR.ENDCCASCI bit to 1 to avoid this.
Change-Id: Ide7393adeae04581fa70eb9173b742049fc3e050
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
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|
| 6cf7b218 | 12-Apr-2019 |
Antonio Niño Díaz <antonio.ninodiaz@arm.com> |
Merge "Cortex A9:errata 794073 workaround" into integration |
| 72db70ca | 12-Apr-2019 |
Antonio Niño Díaz <antonio.ninodiaz@arm.com> |
Merge changes from topic "av/tls-heap" into integration
* changes:
Mbed TLS: Remove weak heap implementation
sgm: Fix bl2 sources |
| dd4cf2c7 | 10-Apr-2019 |
Joel Hutton <Joel.Hutton@arm.com> |
Cortex A9:errata 794073 workaround
On Cortex A9 an errata can cause the processor to violate the rules for
speculative fetches when the MMU is off but branch prediction has not
been disabled. The wo
Cortex A9:errata 794073 workaround
On Cortex A9 an errata can cause the processor to violate the rules for
speculative fetches when the MMU is off but branch prediction has not
been disabled. The workaround for this is to execute an Invalidate
Entire Branch Prediction Array (BPIALL) followed by a DSB.
see:http://arminfo.emea.arm.com/help/topic/com.arm.doc.uan0009d/UAN0009_cortex_a9_errata_r4.pdf
for more details.
Change-Id: I9146c1fa7563a79f4e15b6251617b9620a587c93
Signed-off-by: Joel Hutton <Joel.Hutton@arm.com>
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|
| 2374ab17 | 10-Apr-2019 |
Ambroise Vincent <ambroise.vincent@arm.com> |
Mbed TLS: Remove weak heap implementation
The implementation of the heap function plat_get_mbedtls_heap() becomes
mandatory for platforms supporting TRUSTED_BOARD_BOOT.
The shared Mbed TLS heap def
Mbed TLS: Remove weak heap implementation
The implementation of the heap function plat_get_mbedtls_heap() becomes
mandatory for platforms supporting TRUSTED_BOARD_BOOT.
The shared Mbed TLS heap default weak function implementation is
converted to a helper function get_mbedtls_heap_helper() which can be
used by the platforms for their own function implementation.
Change-Id: Ic8f2994e25e3d9fcd371a21ac459fdcafe07433e
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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|
| 573b4cd2 | 11-Apr-2019 |
Paul Beesley <paul.beesley@arm.com> |
doc: Clarify cert_create build when USE_TBBR_DEFS=0
The user guide documentation for the cert_create tool needs to
mention that a platform must have a platform_oid.h header file
in order to successf
doc: Clarify cert_create build when USE_TBBR_DEFS=0
The user guide documentation for the cert_create tool needs to
mention that a platform must have a platform_oid.h header file
in order to successfully build the cert_create tool when
USE_TBBR_DEFS is 0.
Change-Id: I77f86a022d207e88a79c97741be3eafbfa0c86f1
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
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|
| 01e7e0ca | 09-Apr-2019 |
Antonio Niño Díaz <antonio.ninodiaz@arm.com> |
Merge "Add support for Cortex-A76AE CPU" into integration |
| 9ccc5a57 | 04-Apr-2019 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
Add support for Cortex-A76AE CPU
Change-Id: I0a81f4ea94d41245cd5150de341b51fc70babffe
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com> |
| 699475ac | 22-Feb-2019 |
Joel Hutton <Joel.Hutton@Arm.com> |
Document changes to auth-framework
The data structures in the auth-framework were changed by the previous
patch, and need to be updated.
Change-Id: Icfad2ac688d03d32aa93e45f930a375abbc164a9
Signed-
Document changes to auth-framework
The data structures in the auth-framework were changed by the previous
patch, and need to be updated.
Change-Id: Icfad2ac688d03d32aa93e45f930a375abbc164a9
Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
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|
| c48991e1 | 11-Feb-2019 |
Paul Beesley <paul.beesley@arm.com> |
doc: Fix heading levels for changelog
The change-log.rst file does not use the same symbols
as the other documents when organising its headings,
sub-headings and so on. In order to compile these
doc
doc: Fix heading levels for changelog
The change-log.rst file does not use the same symbols
as the other documents when organising its headings,
sub-headings and so on. In order to compile these
documents together with Sphinx, forming a top-level
index and a consistent structure, it is necessary to
normalise these.
Change-Id: Ib4620ff03a9e76fec9e36e95549016c7b3fe12bb
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
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|
| 18d4d113 | 03-Apr-2019 |
Antonio Niño Díaz <antonio.ninodiaz@arm.com> |
Merge pull request #1918 from lmayencourt/lm/contrib_guidelines
doc: Update contribution guidelines |
| 63fdda2d | 22-Mar-2019 |
Louis Mayencourt <louis.mayencourt@arm.com> |
doc: Update contribution guidelines
Update the documentation for trustedfirmware.org migration
Change-Id: Ibb7052b0becbec3326164f1503806ca2c2fd4dcc
Signed-off-by: Louis Mayencourt <louis.mayencourt
doc: Update contribution guidelines
Update the documentation for trustedfirmware.org migration
Change-Id: Ibb7052b0becbec3326164f1503806ca2c2fd4dcc
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
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| 9b5a8aa5 | 01-Apr-2019 |
Remi Pommarel <repk@triplefau.lt> |
plat: gxl: Add documentation on building GXL image
Also adds a maintainer for GXL.
Signed-off-by: Remi Pommarel <repk@triplefau.lt> |