1/* 2 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <platform_def.h> 8 9#include <arch.h> 10#include <asm_macros.S> 11#include <bl31/ea_handle.h> 12#include <bl31/interrupt_mgmt.h> 13#include <common/runtime_svc.h> 14#include <context.h> 15#include <lib/el3_runtime/cpu_data.h> 16#include <lib/smccc.h> 17 18 .globl runtime_exceptions 19 20 .globl sync_exception_sp_el0 21 .globl irq_sp_el0 22 .globl fiq_sp_el0 23 .globl serror_sp_el0 24 25 .globl sync_exception_sp_elx 26 .globl irq_sp_elx 27 .globl fiq_sp_elx 28 .globl serror_sp_elx 29 30 .globl sync_exception_aarch64 31 .globl irq_aarch64 32 .globl fiq_aarch64 33 .globl serror_aarch64 34 35 .globl sync_exception_aarch32 36 .globl irq_aarch32 37 .globl fiq_aarch32 38 .globl serror_aarch32 39 40 /* 41 * Macro that prepares entry to EL3 upon taking an exception. 42 * 43 * With RAS_EXTENSION, this macro synchronizes pending errors with an ESB 44 * instruction. When an error is thus synchronized, the handling is 45 * delegated to platform EA handler. 46 * 47 * Without RAS_EXTENSION, this macro just saves x30, and unmasks 48 * Asynchronous External Aborts. 49 */ 50 .macro check_and_unmask_ea 51#if RAS_EXTENSION 52 /* Synchronize pending External Aborts */ 53 esb 54 55 /* Unmask the SError interrupt */ 56 msr daifclr, #DAIF_ABT_BIT 57 58 /* 59 * Explicitly save x30 so as to free up a register and to enable 60 * branching 61 */ 62 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 63 64 /* Check for SErrors synchronized by the ESB instruction */ 65 mrs x30, DISR_EL1 66 tbz x30, #DISR_A_BIT, 1f 67 68 /* Save GP registers and restore them afterwards */ 69 bl save_gp_registers 70 bl handle_lower_el_ea_esb 71 bl restore_gp_registers 72 731: 74#else 75 /* Unmask the SError interrupt */ 76 msr daifclr, #DAIF_ABT_BIT 77 78 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 79#endif 80 .endm 81 82 /* --------------------------------------------------------------------- 83 * This macro handles Synchronous exceptions. 84 * Only SMC exceptions are supported. 85 * --------------------------------------------------------------------- 86 */ 87 .macro handle_sync_exception 88#if ENABLE_RUNTIME_INSTRUMENTATION 89 /* 90 * Read the timestamp value and store it in per-cpu data. The value 91 * will be extracted from per-cpu data by the C level SMC handler and 92 * saved to the PMF timestamp region. 93 */ 94 mrs x30, cntpct_el0 95 str x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] 96 mrs x29, tpidr_el3 97 str x30, [x29, #CPU_DATA_PMF_TS0_OFFSET] 98 ldr x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] 99#endif 100 101 mrs x30, esr_el3 102 ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH 103 104 /* Handle SMC exceptions separately from other synchronous exceptions */ 105 cmp x30, #EC_AARCH32_SMC 106 b.eq smc_handler32 107 108 cmp x30, #EC_AARCH64_SMC 109 b.eq smc_handler64 110 111 /* Synchronous exceptions other than the above are assumed to be EA */ 112 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 113 b enter_lower_el_sync_ea 114 .endm 115 116 117 /* --------------------------------------------------------------------- 118 * This macro handles FIQ or IRQ interrupts i.e. EL3, S-EL1 and NS 119 * interrupts. 120 * --------------------------------------------------------------------- 121 */ 122 .macro handle_interrupt_exception label 123 124 bl save_gp_registers 125 126#if CTX_INCLUDE_PAUTH_REGS 127 bl pauth_context_save 128#endif 129 130 /* Save the EL3 system registers needed to return from this exception */ 131 mrs x0, spsr_el3 132 mrs x1, elr_el3 133 stp x0, x1, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] 134 135 /* Switch to the runtime stack i.e. SP_EL0 */ 136 ldr x2, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] 137 mov x20, sp 138 msr spsel, #0 139 mov sp, x2 140 141 /* 142 * Find out whether this is a valid interrupt type. 143 * If the interrupt controller reports a spurious interrupt then return 144 * to where we came from. 145 */ 146 bl plat_ic_get_pending_interrupt_type 147 cmp x0, #INTR_TYPE_INVAL 148 b.eq interrupt_exit_\label 149 150 /* 151 * Get the registered handler for this interrupt type. 152 * A NULL return value could be 'cause of the following conditions: 153 * 154 * a. An interrupt of a type was routed correctly but a handler for its 155 * type was not registered. 156 * 157 * b. An interrupt of a type was not routed correctly so a handler for 158 * its type was not registered. 159 * 160 * c. An interrupt of a type was routed correctly to EL3, but was 161 * deasserted before its pending state could be read. Another 162 * interrupt of a different type pended at the same time and its 163 * type was reported as pending instead. However, a handler for this 164 * type was not registered. 165 * 166 * a. and b. can only happen due to a programming error. The 167 * occurrence of c. could be beyond the control of Trusted Firmware. 168 * It makes sense to return from this exception instead of reporting an 169 * error. 170 */ 171 bl get_interrupt_type_handler 172 cbz x0, interrupt_exit_\label 173 mov x21, x0 174 175 mov x0, #INTR_ID_UNAVAILABLE 176 177 /* Set the current security state in the 'flags' parameter */ 178 mrs x2, scr_el3 179 ubfx x1, x2, #0, #1 180 181 /* Restore the reference to the 'handle' i.e. SP_EL3 */ 182 mov x2, x20 183 184 /* x3 will point to a cookie (not used now) */ 185 mov x3, xzr 186 187 /* Call the interrupt type handler */ 188 blr x21 189 190interrupt_exit_\label: 191 /* Return from exception, possibly in a different security state */ 192 b el3_exit 193 194 .endm 195 196 197vector_base runtime_exceptions 198 199 /* --------------------------------------------------------------------- 200 * Current EL with SP_EL0 : 0x0 - 0x200 201 * --------------------------------------------------------------------- 202 */ 203vector_entry sync_exception_sp_el0 204 /* We don't expect any synchronous exceptions from EL3 */ 205 b report_unhandled_exception 206end_vector_entry sync_exception_sp_el0 207 208vector_entry irq_sp_el0 209 /* 210 * EL3 code is non-reentrant. Any asynchronous exception is a serious 211 * error. Loop infinitely. 212 */ 213 b report_unhandled_interrupt 214end_vector_entry irq_sp_el0 215 216 217vector_entry fiq_sp_el0 218 b report_unhandled_interrupt 219end_vector_entry fiq_sp_el0 220 221 222vector_entry serror_sp_el0 223 no_ret plat_handle_el3_ea 224end_vector_entry serror_sp_el0 225 226 /* --------------------------------------------------------------------- 227 * Current EL with SP_ELx: 0x200 - 0x400 228 * --------------------------------------------------------------------- 229 */ 230vector_entry sync_exception_sp_elx 231 /* 232 * This exception will trigger if anything went wrong during a previous 233 * exception entry or exit or while handling an earlier unexpected 234 * synchronous exception. There is a high probability that SP_EL3 is 235 * corrupted. 236 */ 237 b report_unhandled_exception 238end_vector_entry sync_exception_sp_elx 239 240vector_entry irq_sp_elx 241 b report_unhandled_interrupt 242end_vector_entry irq_sp_elx 243 244vector_entry fiq_sp_elx 245 b report_unhandled_interrupt 246end_vector_entry fiq_sp_elx 247 248vector_entry serror_sp_elx 249 no_ret plat_handle_el3_ea 250end_vector_entry serror_sp_elx 251 252 /* --------------------------------------------------------------------- 253 * Lower EL using AArch64 : 0x400 - 0x600 254 * --------------------------------------------------------------------- 255 */ 256vector_entry sync_exception_aarch64 257 /* 258 * This exception vector will be the entry point for SMCs and traps 259 * that are unhandled at lower ELs most commonly. SP_EL3 should point 260 * to a valid cpu context where the general purpose and system register 261 * state can be saved. 262 */ 263 check_and_unmask_ea 264 handle_sync_exception 265end_vector_entry sync_exception_aarch64 266 267vector_entry irq_aarch64 268 check_and_unmask_ea 269 handle_interrupt_exception irq_aarch64 270end_vector_entry irq_aarch64 271 272vector_entry fiq_aarch64 273 check_and_unmask_ea 274 handle_interrupt_exception fiq_aarch64 275end_vector_entry fiq_aarch64 276 277vector_entry serror_aarch64 278 msr daifclr, #DAIF_ABT_BIT 279 b enter_lower_el_async_ea 280end_vector_entry serror_aarch64 281 282 /* --------------------------------------------------------------------- 283 * Lower EL using AArch32 : 0x600 - 0x800 284 * --------------------------------------------------------------------- 285 */ 286vector_entry sync_exception_aarch32 287 /* 288 * This exception vector will be the entry point for SMCs and traps 289 * that are unhandled at lower ELs most commonly. SP_EL3 should point 290 * to a valid cpu context where the general purpose and system register 291 * state can be saved. 292 */ 293 check_and_unmask_ea 294 handle_sync_exception 295end_vector_entry sync_exception_aarch32 296 297vector_entry irq_aarch32 298 check_and_unmask_ea 299 handle_interrupt_exception irq_aarch32 300end_vector_entry irq_aarch32 301 302vector_entry fiq_aarch32 303 check_and_unmask_ea 304 handle_interrupt_exception fiq_aarch32 305end_vector_entry fiq_aarch32 306 307vector_entry serror_aarch32 308 msr daifclr, #DAIF_ABT_BIT 309 b enter_lower_el_async_ea 310end_vector_entry serror_aarch32 311 312 /* --------------------------------------------------------------------- 313 * The following code handles secure monitor calls. 314 * Depending upon the execution state from where the SMC has been 315 * invoked, it frees some general purpose registers to perform the 316 * remaining tasks. They involve finding the runtime service handler 317 * that is the target of the SMC & switching to runtime stacks (SP_EL0) 318 * before calling the handler. 319 * 320 * Note that x30 has been explicitly saved and can be used here 321 * --------------------------------------------------------------------- 322 */ 323func smc_handler 324smc_handler32: 325 /* Check whether aarch32 issued an SMC64 */ 326 tbnz x0, #FUNCID_CC_SHIFT, smc_prohibited 327 328smc_handler64: 329 /* NOTE: The code below must preserve x0-x4 */ 330 331 /* Save general purpose registers */ 332 bl save_gp_registers 333 334#if CTX_INCLUDE_PAUTH_REGS 335 bl pauth_context_save 336#endif 337 338 /* 339 * Populate the parameters for the SMC handler. 340 * We already have x0-x4 in place. x5 will point to a cookie (not used 341 * now). x6 will point to the context structure (SP_EL3) and x7 will 342 * contain flags we need to pass to the handler. 343 */ 344 mov x5, xzr 345 mov x6, sp 346 347 /* Get the unique owning entity number */ 348 ubfx x16, x0, #FUNCID_OEN_SHIFT, #FUNCID_OEN_WIDTH 349 ubfx x15, x0, #FUNCID_TYPE_SHIFT, #FUNCID_TYPE_WIDTH 350 orr x16, x16, x15, lsl #FUNCID_OEN_WIDTH 351 352 /* Load descriptor index from array of indices */ 353 adr x14, rt_svc_descs_indices 354 ldrb w15, [x14, x16] 355 356 /* Any index greater than 127 is invalid. Check bit 7. */ 357 tbnz w15, 7, smc_unknown 358 359 /* 360 * Get the descriptor using the index 361 * x11 = (base + off), w15 = index 362 * 363 * handler = (base + off) + (index << log2(size)) 364 */ 365 adr x11, (__RT_SVC_DESCS_START__ + RT_SVC_DESC_HANDLE) 366 lsl w10, w15, #RT_SVC_SIZE_LOG2 367 ldr x15, [x11, w10, uxtw] 368 369 /* 370 * Restore the saved C runtime stack value which will become the new 371 * SP_EL0 i.e. EL3 runtime stack. It was saved in the 'cpu_context' 372 * structure prior to the last ERET from EL3. 373 */ 374 ldr x12, [x6, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] 375 376 /* Switch to SP_EL0 */ 377 msr spsel, #0 378 379 /* 380 * Save the SPSR_EL3, ELR_EL3, & SCR_EL3 in case there is a world 381 * switch during SMC handling. 382 * TODO: Revisit if all system registers can be saved later. 383 */ 384 mrs x16, spsr_el3 385 mrs x17, elr_el3 386 mrs x18, scr_el3 387 stp x16, x17, [x6, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] 388 str x18, [x6, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3] 389 390 /* Copy SCR_EL3.NS bit to the flag to indicate caller's security */ 391 bfi x7, x18, #0, #1 392 393 mov sp, x12 394 395 /* 396 * Call the Secure Monitor Call handler and then drop directly into 397 * el3_exit() which will program any remaining architectural state 398 * prior to issuing the ERET to the desired lower EL. 399 */ 400#if DEBUG 401 cbz x15, rt_svc_fw_critical_error 402#endif 403 blr x15 404 405 b el3_exit 406 407smc_unknown: 408 /* 409 * Unknown SMC call. Populate return value with SMC_UNK, restore 410 * GP registers, and return to caller. 411 */ 412 mov x0, #SMC_UNK 413 str x0, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] 414 b restore_gp_registers_eret 415 416smc_prohibited: 417 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 418 mov x0, #SMC_UNK 419 eret 420 421rt_svc_fw_critical_error: 422 /* Switch to SP_ELx */ 423 msr spsel, #1 424 no_ret report_unhandled_exception 425endfunc smc_handler 426