1/* 2 * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6#include <arch.h> 7#include <asm_macros.S> 8#include <assert_macros.S> 9#include <common/debug.h> 10#include <cortex_a57.h> 11#include <cpu_macros.S> 12 13 /* --------------------------------------------- 14 * Disable intra-cluster coherency 15 * Clobbers: r0-r1 16 * --------------------------------------------- 17 */ 18func cortex_a57_disable_smp 19 ldcopr16 r0, r1, CORTEX_A57_ECTLR 20 bic64_imm r0, r1, CORTEX_A57_ECTLR_SMP_BIT 21 stcopr16 r0, r1, CORTEX_A57_ECTLR 22 bx lr 23endfunc cortex_a57_disable_smp 24 25 /* --------------------------------------------- 26 * Disable all types of L2 prefetches. 27 * Clobbers: r0-r2 28 * --------------------------------------------- 29 */ 30func cortex_a57_disable_l2_prefetch 31 ldcopr16 r0, r1, CORTEX_A57_ECTLR 32 orr64_imm r0, r1, CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT 33 bic64_imm r0, r1, (CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK | \ 34 CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK) 35 stcopr16 r0, r1, CORTEX_A57_ECTLR 36 isb 37 dsb ish 38 bx lr 39endfunc cortex_a57_disable_l2_prefetch 40 41 /* --------------------------------------------- 42 * Disable debug interfaces 43 * --------------------------------------------- 44 */ 45func cortex_a57_disable_ext_debug 46 mov r0, #1 47 stcopr r0, DBGOSDLR 48 isb 49 dsb sy 50 bx lr 51endfunc cortex_a57_disable_ext_debug 52 53 /* -------------------------------------------------- 54 * Errata Workaround for Cortex A57 Errata #806969. 55 * This applies only to revision r0p0 of Cortex A57. 56 * Inputs: 57 * r0: variant[4:7] and revision[0:3] of current cpu. 58 * Shall clobber: r0-r3 59 * -------------------------------------------------- 60 */ 61func errata_a57_806969_wa 62 /* 63 * Compare r0 against revision r0p0 64 */ 65 mov r2, lr 66 bl check_errata_806969 67 mov lr, r2 68 cmp r0, #ERRATA_NOT_APPLIES 69 beq 1f 70 ldcopr16 r0, r1, CORTEX_A57_CPUACTLR 71 orr64_imm r0, r1, CORTEX_A57_CPUACTLR_NO_ALLOC_WBWA 72 stcopr16 r0, r1, CORTEX_A57_CPUACTLR 731: 74 bx lr 75endfunc errata_a57_806969_wa 76 77func check_errata_806969 78 mov r1, #0x00 79 b cpu_rev_var_ls 80endfunc check_errata_806969 81 82 /* --------------------------------------------------- 83 * Errata Workaround for Cortex A57 Errata #813419. 84 * This applies only to revision r0p0 of Cortex A57. 85 * --------------------------------------------------- 86 */ 87func check_errata_813419 88 /* 89 * Even though this is only needed for revision r0p0, it 90 * is always applied due to limitations of the current 91 * errata framework. 92 */ 93 mov r0, #ERRATA_APPLIES 94 bx lr 95endfunc check_errata_813419 96 97 /* --------------------------------------------------- 98 * Errata Workaround for Cortex A57 Errata #813420. 99 * This applies only to revision r0p0 of Cortex A57. 100 * Inputs: 101 * r0: variant[4:7] and revision[0:3] of current cpu. 102 * Shall clobber: r0-r3 103 * --------------------------------------------------- 104 */ 105func errata_a57_813420_wa 106 /* 107 * Compare r0 against revision r0p0 108 */ 109 mov r2, lr 110 bl check_errata_813420 111 mov lr, r2 112 cmp r0, #ERRATA_NOT_APPLIES 113 beq 1f 114 ldcopr16 r0, r1, CORTEX_A57_CPUACTLR 115 orr64_imm r0, r1, CORTEX_A57_CPUACTLR_DCC_AS_DCCI 116 stcopr16 r0, r1, CORTEX_A57_CPUACTLR 1171: 118 bx lr 119endfunc errata_a57_813420_wa 120 121func check_errata_813420 122 mov r1, #0x00 123 b cpu_rev_var_ls 124endfunc check_errata_813420 125 126 /* --------------------------------------------------- 127 * Errata Workaround for Cortex A57 Errata #814670. 128 * This applies only to revision r0p0 of Cortex A57. 129 * Inputs: 130 * r0: variant[4:7] and revision[0:3] of current cpu. 131 * Shall clobber: r0-r3 132 * --------------------------------------------------- 133 */ 134func errata_a57_814670_wa 135 /* 136 * Compare r0 against revision r0p0 137 */ 138 mov r2, lr 139 bl check_errata_814670 140 cmp r0, #ERRATA_NOT_APPLIES 141 beq 1f 142 ldcopr16 r0, r1, CORTEX_A57_CPUACTLR 143 orr64_imm r0, r1, CORTEX_A57_CPUACTLR_DIS_DMB_NULLIFICATION 144 stcopr16 r0, r1, CORTEX_A57_CPUACTLR 145 isb 1461: 147 bx r2 148endfunc errata_a57_814670_wa 149 150func check_errata_814670 151 mov r1, #0x00 152 b cpu_rev_var_ls 153endfunc check_errata_814670 154 155 /* -------------------------------------------------------------------- 156 * Disable the over-read from the LDNP instruction. 157 * 158 * This applies to all revisions <= r1p2. The performance degradation 159 * observed with LDNP/STNP has been fixed on r1p3 and onwards. 160 * 161 * Inputs: 162 * r0: variant[4:7] and revision[0:3] of current cpu. 163 * Shall clobber: r0-r3 164 * --------------------------------------------------------------------- 165 */ 166func a57_disable_ldnp_overread 167 /* 168 * Compare r0 against revision r1p2 169 */ 170 mov r2, lr 171 bl check_errata_disable_ldnp_overread 172 mov lr, r2 173 cmp r0, #ERRATA_NOT_APPLIES 174 beq 1f 175 ldcopr16 r0, r1, CORTEX_A57_CPUACTLR 176 orr64_imm r0, r1, CORTEX_A57_CPUACTLR_DIS_OVERREAD 177 stcopr16 r0, r1, CORTEX_A57_CPUACTLR 1781: 179 bx lr 180endfunc a57_disable_ldnp_overread 181 182func check_errata_disable_ldnp_overread 183 mov r1, #0x12 184 b cpu_rev_var_ls 185endfunc check_errata_disable_ldnp_overread 186 187 /* --------------------------------------------------- 188 * Errata Workaround for Cortex A57 Errata #826974. 189 * This applies only to revision <= r1p1 of Cortex A57. 190 * Inputs: 191 * r0: variant[4:7] and revision[0:3] of current cpu. 192 * Shall clobber: r0-r3 193 * --------------------------------------------------- 194 */ 195func errata_a57_826974_wa 196 /* 197 * Compare r0 against revision r1p1 198 */ 199 mov r2, lr 200 bl check_errata_826974 201 mov lr, r2 202 cmp r0, #ERRATA_NOT_APPLIES 203 beq 1f 204 ldcopr16 r0, r1, CORTEX_A57_CPUACTLR 205 orr64_imm r0, r1, CORTEX_A57_CPUACTLR_DIS_LOAD_PASS_DMB 206 stcopr16 r0, r1, CORTEX_A57_CPUACTLR 2071: 208 bx lr 209endfunc errata_a57_826974_wa 210 211func check_errata_826974 212 mov r1, #0x11 213 b cpu_rev_var_ls 214endfunc check_errata_826974 215 216 /* --------------------------------------------------- 217 * Errata Workaround for Cortex A57 Errata #826977. 218 * This applies only to revision <= r1p1 of Cortex A57. 219 * Inputs: 220 * r0: variant[4:7] and revision[0:3] of current cpu. 221 * Shall clobber: r0-r3 222 * --------------------------------------------------- 223 */ 224func errata_a57_826977_wa 225 /* 226 * Compare r0 against revision r1p1 227 */ 228 mov r2, lr 229 bl check_errata_826977 230 mov lr, r2 231 cmp r0, #ERRATA_NOT_APPLIES 232 beq 1f 233 ldcopr16 r0, r1, CORTEX_A57_CPUACTLR 234 orr64_imm r0, r1, CORTEX_A57_CPUACTLR_GRE_NGRE_AS_NGNRE 235 stcopr16 r0, r1, CORTEX_A57_CPUACTLR 2361: 237 bx lr 238endfunc errata_a57_826977_wa 239 240func check_errata_826977 241 mov r1, #0x11 242 b cpu_rev_var_ls 243endfunc check_errata_826977 244 245 /* --------------------------------------------------- 246 * Errata Workaround for Cortex A57 Errata #828024. 247 * This applies only to revision <= r1p1 of Cortex A57. 248 * Inputs: 249 * r0: variant[4:7] and revision[0:3] of current cpu. 250 * Shall clobber: r0-r3 251 * --------------------------------------------------- 252 */ 253func errata_a57_828024_wa 254 /* 255 * Compare r0 against revision r1p1 256 */ 257 mov r2, lr 258 bl check_errata_828024 259 mov lr, r2 260 cmp r0, #ERRATA_NOT_APPLIES 261 beq 1f 262 ldcopr16 r0, r1, CORTEX_A57_CPUACTLR 263 /* 264 * Setting the relevant bits in CORTEX_A57_CPUACTLR has to be done in 2 265 * instructions here because the resulting bitmask doesn't fit in a 266 * 16-bit value so it cannot be encoded in a single instruction. 267 */ 268 orr64_imm r0, r1, CORTEX_A57_CPUACTLR_NO_ALLOC_WBWA 269 orr64_imm r0, r1, (CORTEX_A57_CPUACTLR_DIS_L1_STREAMING | CORTEX_A57_CPUACTLR_DIS_STREAMING) 270 stcopr16 r0, r1, CORTEX_A57_CPUACTLR 2711: 272 bx lr 273endfunc errata_a57_828024_wa 274 275func check_errata_828024 276 mov r1, #0x11 277 b cpu_rev_var_ls 278endfunc check_errata_828024 279 280 /* --------------------------------------------------- 281 * Errata Workaround for Cortex A57 Errata #829520. 282 * This applies only to revision <= r1p2 of Cortex A57. 283 * Inputs: 284 * r0: variant[4:7] and revision[0:3] of current cpu. 285 * Shall clobber: r0-r3 286 * --------------------------------------------------- 287 */ 288func errata_a57_829520_wa 289 /* 290 * Compare r0 against revision r1p2 291 */ 292 mov r2, lr 293 bl check_errata_829520 294 mov lr, r2 295 cmp r0, #ERRATA_NOT_APPLIES 296 beq 1f 297 ldcopr16 r0, r1, CORTEX_A57_CPUACTLR 298 orr64_imm r0, r1, CORTEX_A57_CPUACTLR_DIS_INDIRECT_PREDICTOR 299 stcopr16 r0, r1, CORTEX_A57_CPUACTLR 3001: 301 bx lr 302endfunc errata_a57_829520_wa 303 304func check_errata_829520 305 mov r1, #0x12 306 b cpu_rev_var_ls 307endfunc check_errata_829520 308 309 /* --------------------------------------------------- 310 * Errata Workaround for Cortex A57 Errata #833471. 311 * This applies only to revision <= r1p2 of Cortex A57. 312 * Inputs: 313 * r0: variant[4:7] and revision[0:3] of current cpu. 314 * Shall clobber: r0-r3 315 * --------------------------------------------------- 316 */ 317func errata_a57_833471_wa 318 /* 319 * Compare r0 against revision r1p2 320 */ 321 mov r2, lr 322 bl check_errata_833471 323 mov lr, r2 324 cmp r0, #ERRATA_NOT_APPLIES 325 beq 1f 326 ldcopr16 r0, r1, CORTEX_A57_CPUACTLR 327 orr64_imm r1, r1, CORTEX_A57_CPUACTLR_FORCE_FPSCR_FLUSH 328 stcopr16 r0, r1, CORTEX_A57_CPUACTLR 3291: 330 bx lr 331endfunc errata_a57_833471_wa 332 333func check_errata_833471 334 mov r1, #0x12 335 b cpu_rev_var_ls 336endfunc check_errata_833471 337 338 /* --------------------------------------------------- 339 * Errata Workaround for Cortex A57 Errata #859972. 340 * This applies only to revision <= r1p3 of Cortex A57. 341 * Inputs: 342 * r0: variant[4:7] and revision[0:3] of current cpu. 343 * Shall clobber: r0-r3 344 * --------------------------------------------------- 345 */ 346func errata_a57_859972_wa 347 mov r2, lr 348 bl check_errata_859972 349 mov lr, r2 350 cmp r0, #ERRATA_NOT_APPLIES 351 beq 1f 352 ldcopr16 r0, r1, CORTEX_A57_CPUACTLR 353 orr64_imm r1, r1, CORTEX_A57_CPUACTLR_DIS_INSTR_PREFETCH 354 stcopr16 r0, r1, CORTEX_A57_CPUACTLR 3551: 356 bx lr 357endfunc errata_a57_859972_wa 358 359func check_errata_859972 360 mov r1, #0x13 361 b cpu_rev_var_ls 362endfunc check_errata_859972 363 364func check_errata_cve_2017_5715 365 mov r0, #ERRATA_MISSING 366 bx lr 367endfunc check_errata_cve_2017_5715 368 369func check_errata_cve_2018_3639 370#if WORKAROUND_CVE_2018_3639 371 mov r0, #ERRATA_APPLIES 372#else 373 mov r0, #ERRATA_MISSING 374#endif 375 bx lr 376endfunc check_errata_cve_2018_3639 377 378 /* ------------------------------------------------- 379 * The CPU Ops reset function for Cortex-A57. 380 * Shall clobber: r0-r6 381 * ------------------------------------------------- 382 */ 383func cortex_a57_reset_func 384 mov r5, lr 385 bl cpu_get_rev_var 386 mov r4, r0 387 388#if ERRATA_A57_806969 389 mov r0, r4 390 bl errata_a57_806969_wa 391#endif 392 393#if ERRATA_A57_813420 394 mov r0, r4 395 bl errata_a57_813420_wa 396#endif 397 398#if ERRATA_A57_814670 399 mov r0, r4 400 bl errata_a57_814670_wa 401#endif 402 403#if A57_DISABLE_NON_TEMPORAL_HINT 404 mov r0, r4 405 bl a57_disable_ldnp_overread 406#endif 407 408#if ERRATA_A57_826974 409 mov r0, r4 410 bl errata_a57_826974_wa 411#endif 412 413#if ERRATA_A57_826977 414 mov r0, r4 415 bl errata_a57_826977_wa 416#endif 417 418#if ERRATA_A57_828024 419 mov r0, r4 420 bl errata_a57_828024_wa 421#endif 422 423#if ERRATA_A57_829520 424 mov r0, r4 425 bl errata_a57_829520_wa 426#endif 427 428#if ERRATA_A57_833471 429 mov r0, r4 430 bl errata_a57_833471_wa 431#endif 432 433#if ERRATA_A57_859972 434 mov r0, r4 435 bl errata_a57_859972_wa 436#endif 437 438#if WORKAROUND_CVE_2018_3639 439 ldcopr16 r0, r1, CORTEX_A57_CPUACTLR 440 orr64_imm r0, r1, CORTEX_A57_CPUACTLR_DIS_LOAD_PASS_STORE 441 stcopr16 r0, r1, CORTEX_A57_CPUACTLR 442 isb 443 dsb sy 444#endif 445 446 /* --------------------------------------------- 447 * Enable the SMP bit. 448 * --------------------------------------------- 449 */ 450 ldcopr16 r0, r1, CORTEX_A57_ECTLR 451 orr64_imm r0, r1, CORTEX_A57_ECTLR_SMP_BIT 452 stcopr16 r0, r1, CORTEX_A57_ECTLR 453 isb 454 bx r5 455endfunc cortex_a57_reset_func 456 457 /* ---------------------------------------------------- 458 * The CPU Ops core power down function for Cortex-A57. 459 * ---------------------------------------------------- 460 */ 461func cortex_a57_core_pwr_dwn 462 push {r12, lr} 463 464 /* Assert if cache is enabled */ 465#if ENABLE_ASSERTIONS 466 ldcopr r0, SCTLR 467 tst r0, #SCTLR_C_BIT 468 ASM_ASSERT(eq) 469#endif 470 471 /* --------------------------------------------- 472 * Disable the L2 prefetches. 473 * --------------------------------------------- 474 */ 475 bl cortex_a57_disable_l2_prefetch 476 477 /* --------------------------------------------- 478 * Flush L1 caches. 479 * --------------------------------------------- 480 */ 481 mov r0, #DC_OP_CISW 482 bl dcsw_op_level1 483 484 /* --------------------------------------------- 485 * Come out of intra cluster coherency 486 * --------------------------------------------- 487 */ 488 bl cortex_a57_disable_smp 489 490 /* --------------------------------------------- 491 * Force the debug interfaces to be quiescent 492 * --------------------------------------------- 493 */ 494 pop {r12, lr} 495 b cortex_a57_disable_ext_debug 496endfunc cortex_a57_core_pwr_dwn 497 498 /* ------------------------------------------------------- 499 * The CPU Ops cluster power down function for Cortex-A57. 500 * Clobbers: r0-r3 501 * ------------------------------------------------------- 502 */ 503func cortex_a57_cluster_pwr_dwn 504 push {r12, lr} 505 506 /* Assert if cache is enabled */ 507#if ENABLE_ASSERTIONS 508 ldcopr r0, SCTLR 509 tst r0, #SCTLR_C_BIT 510 ASM_ASSERT(eq) 511#endif 512 513 /* --------------------------------------------- 514 * Disable the L2 prefetches. 515 * --------------------------------------------- 516 */ 517 bl cortex_a57_disable_l2_prefetch 518 519 /* --------------------------------------------- 520 * Flush L1 caches. 521 * --------------------------------------------- 522 */ 523 mov r0, #DC_OP_CISW 524 bl dcsw_op_level1 525 526 /* --------------------------------------------- 527 * Disable the optional ACP. 528 * --------------------------------------------- 529 */ 530 bl plat_disable_acp 531 532 /* --------------------------------------------- 533 * Flush L2 caches. 534 * --------------------------------------------- 535 */ 536 mov r0, #DC_OP_CISW 537 bl dcsw_op_level2 538 539 /* --------------------------------------------- 540 * Come out of intra cluster coherency 541 * --------------------------------------------- 542 */ 543 bl cortex_a57_disable_smp 544 545 /* --------------------------------------------- 546 * Force the debug interfaces to be quiescent 547 * --------------------------------------------- 548 */ 549 pop {r12, lr} 550 b cortex_a57_disable_ext_debug 551endfunc cortex_a57_cluster_pwr_dwn 552 553#if REPORT_ERRATA 554/* 555 * Errata printing function for Cortex A57. Must follow AAPCS. 556 */ 557func cortex_a57_errata_report 558 push {r12, lr} 559 560 bl cpu_get_rev_var 561 mov r4, r0 562 563 /* 564 * Report all errata. The revision-variant information is passed to 565 * checking functions of each errata. 566 */ 567 report_errata ERRATA_A57_806969, cortex_a57, 806969 568 report_errata ERRATA_A57_813419, cortex_a57, 813419 569 report_errata ERRATA_A57_813420, cortex_a57, 813420 570 report_errata ERRATA_A57_814670, cortex_a57, 814670 571 report_errata A57_DISABLE_NON_TEMPORAL_HINT, cortex_a57, \ 572 disable_ldnp_overread 573 report_errata ERRATA_A57_826974, cortex_a57, 826974 574 report_errata ERRATA_A57_826977, cortex_a57, 826977 575 report_errata ERRATA_A57_828024, cortex_a57, 828024 576 report_errata ERRATA_A57_829520, cortex_a57, 829520 577 report_errata ERRATA_A57_833471, cortex_a57, 833471 578 report_errata ERRATA_A57_859972, cortex_a57, 859972 579 report_errata WORKAROUND_CVE_2017_5715, cortex_a57, cve_2017_5715 580 report_errata WORKAROUND_CVE_2018_3639, cortex_a57, cve_2018_3639 581 582 pop {r12, lr} 583 bx lr 584endfunc cortex_a57_errata_report 585#endif 586 587declare_cpu_ops cortex_a57, CORTEX_A57_MIDR, \ 588 cortex_a57_reset_func, \ 589 cortex_a57_core_pwr_dwn, \ 590 cortex_a57_cluster_pwr_dwn 591