1 /* 2 * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CORTEX_A55_H 8 #define CORTEX_A55_H 9 10 #include <lib/utils_def.h> 11 12 /* Cortex-A55 MIDR for revision 0 */ 13 #define CORTEX_A55_MIDR U(0x410fd050) 14 15 /******************************************************************************* 16 * CPU Extended Control register specific definitions. 17 ******************************************************************************/ 18 #define CORTEX_A55_CPUPWRCTLR_EL1 S3_0_C15_C2_7 19 #define CORTEX_A55_CPUECTLR_EL1 S3_0_C15_C1_4 20 21 /******************************************************************************* 22 * CPU Auxiliary Control register specific definitions. 23 ******************************************************************************/ 24 #define CORTEX_A55_CPUACTLR_EL1 S3_0_C15_C1_0 25 26 #define CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE (ULL(1) << 31) 27 28 /* Definitions of register field mask in CORTEX_A55_CPUPWRCTLR_EL1 */ 29 #define CORTEX_A55_CORE_PWRDN_EN_MASK U(0x1) 30 31 #endif /* CORTEX_A55_H */ 32