1/* 2 * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6#include <arch.h> 7#include <asm_macros.S> 8#include <assert_macros.S> 9#include <common/bl_common.h> 10#include <common/debug.h> 11#include <cortex_a57.h> 12#include <cpu_macros.S> 13#include <plat_macros.S> 14 15 /* --------------------------------------------- 16 * Disable L1 data cache and unified L2 cache 17 * --------------------------------------------- 18 */ 19func cortex_a57_disable_dcache 20 mrs x1, sctlr_el3 21 bic x1, x1, #SCTLR_C_BIT 22 msr sctlr_el3, x1 23 isb 24 ret 25endfunc cortex_a57_disable_dcache 26 27 /* --------------------------------------------- 28 * Disable all types of L2 prefetches. 29 * --------------------------------------------- 30 */ 31func cortex_a57_disable_l2_prefetch 32 mrs x0, CORTEX_A57_ECTLR_EL1 33 orr x0, x0, #CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT 34 mov x1, #CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK 35 orr x1, x1, #CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK 36 bic x0, x0, x1 37 msr CORTEX_A57_ECTLR_EL1, x0 38 isb 39 dsb ish 40 ret 41endfunc cortex_a57_disable_l2_prefetch 42 43 /* --------------------------------------------- 44 * Disable intra-cluster coherency 45 * --------------------------------------------- 46 */ 47func cortex_a57_disable_smp 48 mrs x0, CORTEX_A57_ECTLR_EL1 49 bic x0, x0, #CORTEX_A57_ECTLR_SMP_BIT 50 msr CORTEX_A57_ECTLR_EL1, x0 51 ret 52endfunc cortex_a57_disable_smp 53 54 /* --------------------------------------------- 55 * Disable debug interfaces 56 * --------------------------------------------- 57 */ 58func cortex_a57_disable_ext_debug 59 mov x0, #1 60 msr osdlr_el1, x0 61 isb 62 dsb sy 63 ret 64endfunc cortex_a57_disable_ext_debug 65 66 /* -------------------------------------------------- 67 * Errata Workaround for Cortex A57 Errata #806969. 68 * This applies only to revision r0p0 of Cortex A57. 69 * Inputs: 70 * x0: variant[4:7] and revision[0:3] of current cpu. 71 * Shall clobber: x0-x17 72 * -------------------------------------------------- 73 */ 74func errata_a57_806969_wa 75 /* 76 * Compare x0 against revision r0p0 77 */ 78 mov x17, x30 79 bl check_errata_806969 80 cbz x0, 1f 81 mrs x1, CORTEX_A57_CPUACTLR_EL1 82 orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA 83 msr CORTEX_A57_CPUACTLR_EL1, x1 841: 85 ret x17 86endfunc errata_a57_806969_wa 87 88func check_errata_806969 89 mov x1, #0x00 90 b cpu_rev_var_ls 91endfunc check_errata_806969 92 93 /* --------------------------------------------------- 94 * Errata Workaround for Cortex A57 Errata #813419. 95 * This applies only to revision r0p0 of Cortex A57. 96 * --------------------------------------------------- 97 */ 98func check_errata_813419 99 /* 100 * Even though this is only needed for revision r0p0, it 101 * is always applied due to limitations of the current 102 * errata framework. 103 */ 104 mov x0, #ERRATA_APPLIES 105 ret 106endfunc check_errata_813419 107 108 /* --------------------------------------------------- 109 * Errata Workaround for Cortex A57 Errata #813420. 110 * This applies only to revision r0p0 of Cortex A57. 111 * Inputs: 112 * x0: variant[4:7] and revision[0:3] of current cpu. 113 * Shall clobber: x0-x17 114 * --------------------------------------------------- 115 */ 116func errata_a57_813420_wa 117 /* 118 * Compare x0 against revision r0p0 119 */ 120 mov x17, x30 121 bl check_errata_813420 122 cbz x0, 1f 123 mrs x1, CORTEX_A57_CPUACTLR_EL1 124 orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DCC_AS_DCCI 125 msr CORTEX_A57_CPUACTLR_EL1, x1 1261: 127 ret x17 128endfunc errata_a57_813420_wa 129 130func check_errata_813420 131 mov x1, #0x00 132 b cpu_rev_var_ls 133endfunc check_errata_813420 134 135 /* --------------------------------------------------- 136 * Errata Workaround for Cortex A57 Errata #814670. 137 * This applies only to revision r0p0 of Cortex A57. 138 * Inputs: 139 * x0: variant[4:7] and revision[0:3] of current cpu. 140 * Shall clobber: x0-x17 141 * --------------------------------------------------- 142 */ 143func errata_a57_814670_wa 144 /* 145 * Compare x0 against revision r0p0 146 */ 147 mov x17, x30 148 bl check_errata_814670 149 cbz x0, 1f 150 mrs x1, CORTEX_A57_CPUACTLR_EL1 151 orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_DMB_NULLIFICATION 152 msr CORTEX_A57_CPUACTLR_EL1, x1 153 isb 1541: 155 ret x17 156endfunc errata_a57_814670_wa 157 158func check_errata_814670 159 mov x1, #0x00 160 b cpu_rev_var_ls 161endfunc check_errata_814670 162 163 /* -------------------------------------------------------------------- 164 * Disable the over-read from the LDNP instruction. 165 * 166 * This applies to all revisions <= r1p2. The performance degradation 167 * observed with LDNP/STNP has been fixed on r1p3 and onwards. 168 * 169 * Inputs: 170 * x0: variant[4:7] and revision[0:3] of current cpu. 171 * Shall clobber: x0-x17 172 * --------------------------------------------------------------------- 173 */ 174func a57_disable_ldnp_overread 175 /* 176 * Compare x0 against revision r1p2 177 */ 178 mov x17, x30 179 bl check_errata_disable_ldnp_overread 180 cbz x0, 1f 181 mrs x1, CORTEX_A57_CPUACTLR_EL1 182 orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_OVERREAD 183 msr CORTEX_A57_CPUACTLR_EL1, x1 1841: 185 ret x17 186endfunc a57_disable_ldnp_overread 187 188func check_errata_disable_ldnp_overread 189 mov x1, #0x12 190 b cpu_rev_var_ls 191endfunc check_errata_disable_ldnp_overread 192 193 /* --------------------------------------------------- 194 * Errata Workaround for Cortex A57 Errata #826974. 195 * This applies only to revision <= r1p1 of Cortex A57. 196 * Inputs: 197 * x0: variant[4:7] and revision[0:3] of current cpu. 198 * Shall clobber: x0-x17 199 * --------------------------------------------------- 200 */ 201func errata_a57_826974_wa 202 /* 203 * Compare x0 against revision r1p1 204 */ 205 mov x17, x30 206 bl check_errata_826974 207 cbz x0, 1f 208 mrs x1, CORTEX_A57_CPUACTLR_EL1 209 orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_DMB 210 msr CORTEX_A57_CPUACTLR_EL1, x1 2111: 212 ret x17 213endfunc errata_a57_826974_wa 214 215func check_errata_826974 216 mov x1, #0x11 217 b cpu_rev_var_ls 218endfunc check_errata_826974 219 220 /* --------------------------------------------------- 221 * Errata Workaround for Cortex A57 Errata #826977. 222 * This applies only to revision <= r1p1 of Cortex A57. 223 * Inputs: 224 * x0: variant[4:7] and revision[0:3] of current cpu. 225 * Shall clobber: x0-x17 226 * --------------------------------------------------- 227 */ 228func errata_a57_826977_wa 229 /* 230 * Compare x0 against revision r1p1 231 */ 232 mov x17, x30 233 bl check_errata_826977 234 cbz x0, 1f 235 mrs x1, CORTEX_A57_CPUACTLR_EL1 236 orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_GRE_NGRE_AS_NGNRE 237 msr CORTEX_A57_CPUACTLR_EL1, x1 2381: 239 ret x17 240endfunc errata_a57_826977_wa 241 242func check_errata_826977 243 mov x1, #0x11 244 b cpu_rev_var_ls 245endfunc check_errata_826977 246 247 /* --------------------------------------------------- 248 * Errata Workaround for Cortex A57 Errata #828024. 249 * This applies only to revision <= r1p1 of Cortex A57. 250 * Inputs: 251 * x0: variant[4:7] and revision[0:3] of current cpu. 252 * Shall clobber: x0-x17 253 * --------------------------------------------------- 254 */ 255func errata_a57_828024_wa 256 /* 257 * Compare x0 against revision r1p1 258 */ 259 mov x17, x30 260 bl check_errata_828024 261 cbz x0, 1f 262 mrs x1, CORTEX_A57_CPUACTLR_EL1 263 /* 264 * Setting the relevant bits in CPUACTLR_EL1 has to be done in 2 265 * instructions here because the resulting bitmask doesn't fit in a 266 * 16-bit value so it cannot be encoded in a single instruction. 267 */ 268 orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA 269 orr x1, x1, #(CORTEX_A57_CPUACTLR_EL1_DIS_L1_STREAMING | \ 270 CORTEX_A57_CPUACTLR_EL1_DIS_STREAMING) 271 msr CORTEX_A57_CPUACTLR_EL1, x1 2721: 273 ret x17 274endfunc errata_a57_828024_wa 275 276func check_errata_828024 277 mov x1, #0x11 278 b cpu_rev_var_ls 279endfunc check_errata_828024 280 281 /* --------------------------------------------------- 282 * Errata Workaround for Cortex A57 Errata #829520. 283 * This applies only to revision <= r1p2 of Cortex A57. 284 * Inputs: 285 * x0: variant[4:7] and revision[0:3] of current cpu. 286 * Shall clobber: x0-x17 287 * --------------------------------------------------- 288 */ 289func errata_a57_829520_wa 290 /* 291 * Compare x0 against revision r1p2 292 */ 293 mov x17, x30 294 bl check_errata_829520 295 cbz x0, 1f 296 mrs x1, CORTEX_A57_CPUACTLR_EL1 297 orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_INDIRECT_PREDICTOR 298 msr CORTEX_A57_CPUACTLR_EL1, x1 2991: 300 ret x17 301endfunc errata_a57_829520_wa 302 303func check_errata_829520 304 mov x1, #0x12 305 b cpu_rev_var_ls 306endfunc check_errata_829520 307 308 /* --------------------------------------------------- 309 * Errata Workaround for Cortex A57 Errata #833471. 310 * This applies only to revision <= r1p2 of Cortex A57. 311 * Inputs: 312 * x0: variant[4:7] and revision[0:3] of current cpu. 313 * Shall clobber: x0-x17 314 * --------------------------------------------------- 315 */ 316func errata_a57_833471_wa 317 /* 318 * Compare x0 against revision r1p2 319 */ 320 mov x17, x30 321 bl check_errata_833471 322 cbz x0, 1f 323 mrs x1, CORTEX_A57_CPUACTLR_EL1 324 orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_FORCE_FPSCR_FLUSH 325 msr CORTEX_A57_CPUACTLR_EL1, x1 3261: 327 ret x17 328endfunc errata_a57_833471_wa 329 330func check_errata_833471 331 mov x1, #0x12 332 b cpu_rev_var_ls 333endfunc check_errata_833471 334 335 /* -------------------------------------------------- 336 * Errata Workaround for Cortex A57 Errata #859972. 337 * This applies only to revision <= r1p3 of Cortex A57. 338 * Inputs: 339 * x0: variant[4:7] and revision[0:3] of current cpu. 340 * Shall clobber: 341 * -------------------------------------------------- 342 */ 343func errata_a57_859972_wa 344 mov x17, x30 345 bl check_errata_859972 346 cbz x0, 1f 347 mrs x1, CORTEX_A57_CPUACTLR_EL1 348 orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_INSTR_PREFETCH 349 msr CORTEX_A57_CPUACTLR_EL1, x1 3501: 351 ret x17 352endfunc errata_a57_859972_wa 353 354func check_errata_859972 355 mov x1, #0x13 356 b cpu_rev_var_ls 357endfunc check_errata_859972 358 359func check_errata_cve_2017_5715 360#if WORKAROUND_CVE_2017_5715 361 mov x0, #ERRATA_APPLIES 362#else 363 mov x0, #ERRATA_MISSING 364#endif 365 ret 366endfunc check_errata_cve_2017_5715 367 368func check_errata_cve_2018_3639 369#if WORKAROUND_CVE_2018_3639 370 mov x0, #ERRATA_APPLIES 371#else 372 mov x0, #ERRATA_MISSING 373#endif 374 ret 375endfunc check_errata_cve_2018_3639 376 377 /* ------------------------------------------------- 378 * The CPU Ops reset function for Cortex-A57. 379 * Shall clobber: x0-x19 380 * ------------------------------------------------- 381 */ 382func cortex_a57_reset_func 383 mov x19, x30 384 bl cpu_get_rev_var 385 mov x18, x0 386 387#if ERRATA_A57_806969 388 mov x0, x18 389 bl errata_a57_806969_wa 390#endif 391 392#if ERRATA_A57_813420 393 mov x0, x18 394 bl errata_a57_813420_wa 395#endif 396 397#if ERRATA_A57_814670 398 mov x0, x18 399 bl errata_a57_814670_wa 400#endif 401 402#if A57_DISABLE_NON_TEMPORAL_HINT 403 mov x0, x18 404 bl a57_disable_ldnp_overread 405#endif 406 407#if ERRATA_A57_826974 408 mov x0, x18 409 bl errata_a57_826974_wa 410#endif 411 412#if ERRATA_A57_826977 413 mov x0, x18 414 bl errata_a57_826977_wa 415#endif 416 417#if ERRATA_A57_828024 418 mov x0, x18 419 bl errata_a57_828024_wa 420#endif 421 422#if ERRATA_A57_829520 423 mov x0, x18 424 bl errata_a57_829520_wa 425#endif 426 427#if ERRATA_A57_833471 428 mov x0, x18 429 bl errata_a57_833471_wa 430#endif 431 432#if ERRATA_A57_859972 433 mov x0, x18 434 bl errata_a57_859972_wa 435#endif 436 437#if IMAGE_BL31 && WORKAROUND_CVE_2017_5715 438 adr x0, wa_cve_2017_5715_mmu_vbar 439 msr vbar_el3, x0 440 /* isb will be performed before returning from this function */ 441#endif 442 443#if WORKAROUND_CVE_2018_3639 444 mrs x0, CORTEX_A57_CPUACTLR_EL1 445 orr x0, x0, #CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_STORE 446 msr CORTEX_A57_CPUACTLR_EL1, x0 447 isb 448 dsb sy 449#endif 450 451 /* --------------------------------------------- 452 * Enable the SMP bit. 453 * --------------------------------------------- 454 */ 455 mrs x0, CORTEX_A57_ECTLR_EL1 456 orr x0, x0, #CORTEX_A57_ECTLR_SMP_BIT 457 msr CORTEX_A57_ECTLR_EL1, x0 458 isb 459 ret x19 460endfunc cortex_a57_reset_func 461 462 /* ---------------------------------------------------- 463 * The CPU Ops core power down function for Cortex-A57. 464 * ---------------------------------------------------- 465 */ 466func cortex_a57_core_pwr_dwn 467 mov x18, x30 468 469 /* --------------------------------------------- 470 * Turn off caches. 471 * --------------------------------------------- 472 */ 473 bl cortex_a57_disable_dcache 474 475 /* --------------------------------------------- 476 * Disable the L2 prefetches. 477 * --------------------------------------------- 478 */ 479 bl cortex_a57_disable_l2_prefetch 480 481 /* --------------------------------------------- 482 * Flush L1 caches. 483 * --------------------------------------------- 484 */ 485 mov x0, #DCCISW 486 bl dcsw_op_level1 487 488 /* --------------------------------------------- 489 * Come out of intra cluster coherency 490 * --------------------------------------------- 491 */ 492 bl cortex_a57_disable_smp 493 494 /* --------------------------------------------- 495 * Force the debug interfaces to be quiescent 496 * --------------------------------------------- 497 */ 498 mov x30, x18 499 b cortex_a57_disable_ext_debug 500endfunc cortex_a57_core_pwr_dwn 501 502 /* ------------------------------------------------------- 503 * The CPU Ops cluster power down function for Cortex-A57. 504 * ------------------------------------------------------- 505 */ 506func cortex_a57_cluster_pwr_dwn 507 mov x18, x30 508 509 /* --------------------------------------------- 510 * Turn off caches. 511 * --------------------------------------------- 512 */ 513 bl cortex_a57_disable_dcache 514 515 /* --------------------------------------------- 516 * Disable the L2 prefetches. 517 * --------------------------------------------- 518 */ 519 bl cortex_a57_disable_l2_prefetch 520 521#if !SKIP_A57_L1_FLUSH_PWR_DWN 522 /* ------------------------------------------------- 523 * Flush the L1 caches. 524 * ------------------------------------------------- 525 */ 526 mov x0, #DCCISW 527 bl dcsw_op_level1 528#endif 529 /* --------------------------------------------- 530 * Disable the optional ACP. 531 * --------------------------------------------- 532 */ 533 bl plat_disable_acp 534 535 /* ------------------------------------------------- 536 * Flush the L2 caches. 537 * ------------------------------------------------- 538 */ 539 mov x0, #DCCISW 540 bl dcsw_op_level2 541 542 /* --------------------------------------------- 543 * Come out of intra cluster coherency 544 * --------------------------------------------- 545 */ 546 bl cortex_a57_disable_smp 547 548 /* --------------------------------------------- 549 * Force the debug interfaces to be quiescent 550 * --------------------------------------------- 551 */ 552 mov x30, x18 553 b cortex_a57_disable_ext_debug 554endfunc cortex_a57_cluster_pwr_dwn 555 556#if REPORT_ERRATA 557/* 558 * Errata printing function for Cortex A57. Must follow AAPCS. 559 */ 560func cortex_a57_errata_report 561 stp x8, x30, [sp, #-16]! 562 563 bl cpu_get_rev_var 564 mov x8, x0 565 566 /* 567 * Report all errata. The revision-variant information is passed to 568 * checking functions of each errata. 569 */ 570 report_errata ERRATA_A57_806969, cortex_a57, 806969 571 report_errata ERRATA_A57_813419, cortex_a57, 813419 572 report_errata ERRATA_A57_813420, cortex_a57, 813420 573 report_errata ERRATA_A57_814670, cortex_a57, 814670 574 report_errata A57_DISABLE_NON_TEMPORAL_HINT, cortex_a57, \ 575 disable_ldnp_overread 576 report_errata ERRATA_A57_826974, cortex_a57, 826974 577 report_errata ERRATA_A57_826977, cortex_a57, 826977 578 report_errata ERRATA_A57_828024, cortex_a57, 828024 579 report_errata ERRATA_A57_829520, cortex_a57, 829520 580 report_errata ERRATA_A57_833471, cortex_a57, 833471 581 report_errata ERRATA_A57_859972, cortex_a57, 859972 582 report_errata WORKAROUND_CVE_2017_5715, cortex_a57, cve_2017_5715 583 report_errata WORKAROUND_CVE_2018_3639, cortex_a57, cve_2018_3639 584 585 ldp x8, x30, [sp], #16 586 ret 587endfunc cortex_a57_errata_report 588#endif 589 590 /* --------------------------------------------- 591 * This function provides cortex_a57 specific 592 * register information for crash reporting. 593 * It needs to return with x6 pointing to 594 * a list of register names in ascii and 595 * x8 - x15 having values of registers to be 596 * reported. 597 * --------------------------------------------- 598 */ 599.section .rodata.cortex_a57_regs, "aS" 600cortex_a57_regs: /* The ascii list of register names to be reported */ 601 .asciz "cpuectlr_el1", "cpumerrsr_el1", "l2merrsr_el1", "" 602 603func cortex_a57_cpu_reg_dump 604 adr x6, cortex_a57_regs 605 mrs x8, CORTEX_A57_ECTLR_EL1 606 mrs x9, CORTEX_A57_MERRSR_EL1 607 mrs x10, CORTEX_A57_L2MERRSR_EL1 608 ret 609endfunc cortex_a57_cpu_reg_dump 610 611declare_cpu_ops_wa cortex_a57, CORTEX_A57_MIDR, \ 612 cortex_a57_reset_func, \ 613 check_errata_cve_2017_5715, \ 614 CPU_NO_EXTRA2_FUNC, \ 615 cortex_a57_core_pwr_dwn, \ 616 cortex_a57_cluster_pwr_dwn 617