1# 2# Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7# Default, static values for build variables, listed in alphabetic order. 8# Dependencies between build options, if any, are handled in the top-level 9# Makefile, after this file is included. This ensures that the former is better 10# poised to handle dependencies, as all build variables would have a default 11# value by then. 12 13# Use T32 by default 14AARCH32_INSTRUCTION_SET := T32 15 16# The AArch32 Secure Payload to be built as BL32 image 17AARCH32_SP := none 18 19# The Target build architecture. Supported values are: aarch64, aarch32. 20ARCH := aarch64 21 22# ARM Architecture major and minor versions: 8.0 by default. 23ARM_ARCH_MAJOR := 8 24ARM_ARCH_MINOR := 0 25 26# Base commit to perform code check on 27BASE_COMMIT := origin/master 28 29# Execute BL2 at EL3 30BL2_AT_EL3 := 0 31 32# BL2 image is stored in XIP memory, for now, this option is only supported 33# when BL2_AT_EL3 is 1. 34BL2_IN_XIP_MEM := 0 35 36# By default, consider that the platform may release several CPUs out of reset. 37# The platform Makefile is free to override this value. 38COLD_BOOT_SINGLE_CPU := 0 39 40# Flag to compile in coreboot support code. Exclude by default. The coreboot 41# Makefile system will set this when compiling TF as part of a coreboot image. 42COREBOOT := 0 43 44# For Chain of Trust 45CREATE_KEYS := 1 46 47# Build flag to include AArch32 registers in cpu context save and restore during 48# world switch. This flag must be set to 0 for AArch64-only platforms. 49CTX_INCLUDE_AARCH32_REGS := 1 50 51# Include FP registers in cpu context 52CTX_INCLUDE_FPREGS := 0 53 54# Include pointer authentication (ARMv8.3-PAuth) registers in cpu context. This 55# must be set to 1 if the platform wants to use this feature in the Secure 56# world. It is not needed to use it in the Non-secure world. 57CTX_INCLUDE_PAUTH_REGS := 0 58 59# Debug build 60DEBUG := 0 61 62# Build platform 63DEFAULT_PLAT := fvp 64 65# Enable capability to disable authentication dynamically. Only meant for 66# development platforms. 67DYN_DISABLE_AUTH := 0 68 69# Build option to enable MPAM for lower ELs 70ENABLE_MPAM_FOR_LOWER_ELS := 0 71 72# Flag to Enable Position Independant support (PIE) 73ENABLE_PIE := 0 74 75# Flag to enable Performance Measurement Framework 76ENABLE_PMF := 0 77 78# Flag to enable PSCI STATs functionality 79ENABLE_PSCI_STAT := 0 80 81# Flag to enable runtime instrumentation using PMF 82ENABLE_RUNTIME_INSTRUMENTATION := 0 83 84# Flag to enable stack corruption protection 85ENABLE_STACK_PROTECTOR := 0 86 87# Flag to enable exception handling in EL3 88EL3_EXCEPTION_HANDLING := 0 89 90# Build flag to treat usage of deprecated platform and framework APIs as error. 91ERROR_DEPRECATED := 0 92 93# Fault injection support 94FAULT_INJECTION_SUPPORT := 0 95 96# Byte alignment that each component in FIP is aligned to 97FIP_ALIGN := 0 98 99# Default FIP file name 100FIP_NAME := fip.bin 101 102# Default FWU_FIP file name 103FWU_FIP_NAME := fwu_fip.bin 104 105# For Chain of Trust 106GENERATE_COT := 0 107 108# Hint platform interrupt control layer that Group 0 interrupts are for EL3. By 109# default, they are for Secure EL1. 110GICV2_G0_FOR_EL3 := 0 111 112# Route External Aborts to EL3. Disabled by default; External Aborts are handled 113# by lower ELs. 114HANDLE_EA_EL3_FIRST := 0 115 116# Whether system coherency is managed in hardware, without explicit software 117# operations. 118HW_ASSISTED_COHERENCY := 0 119 120# Set the default algorithm for the generation of Trusted Board Boot keys 121KEY_ALG := rsa 122 123# Enable use of the console API allowing multiple consoles to be registered 124# at the same time. 125MULTI_CONSOLE_API := 0 126 127# NS timer register save and restore 128NS_TIMER_SWITCH := 0 129 130# Include lib/libc in the final image 131OVERRIDE_LIBC := 0 132 133# Build PL011 UART driver in minimal generic UART mode 134PL011_GENERIC_UART := 0 135 136# By default, consider that the platform's reset address is not programmable. 137# The platform Makefile is free to override this value. 138PROGRAMMABLE_RESET_ADDRESS := 0 139 140# Flag used to choose the power state format viz Extended State-ID or the 141# Original format. 142PSCI_EXTENDED_STATE_ID := 0 143 144# Enable RAS support 145RAS_EXTENSION := 0 146 147# By default, BL1 acts as the reset handler, not BL31 148RESET_TO_BL31 := 0 149 150# For Chain of Trust 151SAVE_KEYS := 0 152 153# Software Delegated Exception support 154SDEI_SUPPORT := 0 155 156# Whether code and read-only data should be put on separate memory pages. The 157# platform Makefile is free to override this value. 158SEPARATE_CODE_AND_RODATA := 0 159 160# If the BL31 image initialisation code is recalimed after use for the secondary 161# cores stack 162RECLAIM_INIT_CODE := 0 163 164# SPD choice 165SPD := none 166 167# For including the Secure Partition Manager 168ENABLE_SPM := 0 169 170# Use the SPM based on MM 171SPM_MM := 1 172 173# Flag to introduce an infinite loop in BL1 just before it exits into the next 174# image. This is meant to help debugging the post-BL2 phase. 175SPIN_ON_BL1_EXIT := 0 176 177# Flags to build TF with Trusted Boot support 178TRUSTED_BOARD_BOOT := 0 179 180# Build option to choose whether Trusted Firmware uses Coherent memory or not. 181USE_COHERENT_MEM := 1 182 183# Build option to choose whether Trusted Firmware uses library at ROM 184USE_ROMLIB := 0 185 186# Use tbbr_oid.h instead of platform_oid.h 187USE_TBBR_DEFS := 1 188 189# Build verbosity 190V := 0 191 192# Whether to enable D-Cache early during warm boot. This is usually 193# applicable for platforms wherein interconnect programming is not 194# required to enable cache coherency after warm reset (eg: single cluster 195# platforms). 196WARMBOOT_ENABLE_DCACHE_EARLY := 0 197 198# Build option to enable/disable the Statistical Profiling Extensions 199ENABLE_SPE_FOR_LOWER_ELS := 1 200 201# SPE is only supported on AArch64 so disable it on AArch32. 202ifeq (${ARCH},aarch32) 203 override ENABLE_SPE_FOR_LOWER_ELS := 0 204endif 205 206ENABLE_AMU := 0 207 208# By default, enable Scalable Vector Extension if implemented for Non-secure 209# lower ELs 210# Note SVE is only supported on AArch64 - therefore do not enable in AArch32 211ifneq (${ARCH},aarch32) 212 ENABLE_SVE_FOR_NS := 1 213else 214 override ENABLE_SVE_FOR_NS := 0 215endif 216