1/* 2 * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a55.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14 /* -------------------------------------------------- 15 * Errata Workaround for Cortex A55 Errata #768277. 16 * This applies only to revision r0p0 of Cortex A55. 17 * Inputs: 18 * x0: variant[4:7] and revision[0:3] of current cpu. 19 * Shall clobber: x0-x17 20 * -------------------------------------------------- 21 */ 22func errata_a55_768277_wa 23 /* 24 * Compare x0 against revision r0p0 25 */ 26 mov x17, x30 27 bl check_errata_768277 28 cbz x0, 1f 29 mrs x1, CORTEX_A55_CPUACTLR_EL1 30 orr x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE 31 msr CORTEX_A55_CPUACTLR_EL1, x1 32 isb 331: 34 ret x17 35endfunc errata_a55_768277_wa 36 37func check_errata_768277 38 mov x1, #0x00 39 b cpu_rev_var_ls 40endfunc check_errata_768277 41 42func cortex_a55_reset_func 43 mov x19, x30 44 45#if ERRATA_DSU_936184 46 bl errata_dsu_936184_wa 47#endif 48 49 bl cpu_get_rev_var 50 mov x18, x0 51 52#if ERRATA_A55_768277 53 mov x0, x18 54 bl errata_a55_768277_wa 55#endif 56 57 ret x19 58endfunc cortex_a55_reset_func 59 60 /* --------------------------------------------- 61 * HW will do the cache maintenance while powering down 62 * --------------------------------------------- 63 */ 64func cortex_a55_core_pwr_dwn 65 /* --------------------------------------------- 66 * Enable CPU power down bit in power control register 67 * --------------------------------------------- 68 */ 69 mrs x0, CORTEX_A55_CPUPWRCTLR_EL1 70 orr x0, x0, #CORTEX_A55_CORE_PWRDN_EN_MASK 71 msr CORTEX_A55_CPUPWRCTLR_EL1, x0 72 isb 73 ret 74endfunc cortex_a55_core_pwr_dwn 75 76#if REPORT_ERRATA 77/* 78 * Errata printing function for Cortex A55. Must follow AAPCS & can use stack. 79 */ 80func cortex_a55_errata_report 81 stp x8, x30, [sp, #-16]! 82 bl cpu_get_rev_var 83 mov x8, x0 84 85 /* 86 * Report all errata. The revision variant information is at x8, where 87 * "report_errata" is expecting it and it doesn't corrupt it. 88 */ 89 report_errata ERRATA_DSU_936184, cortex_a55, dsu_936184 90 report_errata ERRATA_A55_768277, cortex_a55, 768277 91 92 ldp x8, x30, [sp], #16 93 ret 94endfunc cortex_a55_errata_report 95#endif 96 97 /* --------------------------------------------- 98 * This function provides cortex_a55 specific 99 * register information for crash reporting. 100 * It needs to return with x6 pointing to 101 * a list of register names in ascii and 102 * x8 - x15 having values of registers to be 103 * reported. 104 * --------------------------------------------- 105 */ 106.section .rodata.cortex_a55_regs, "aS" 107cortex_a55_regs: /* The ascii list of register names to be reported */ 108 .asciz "cpuectlr_el1", "" 109 110func cortex_a55_cpu_reg_dump 111 adr x6, cortex_a55_regs 112 mrs x8, CORTEX_A55_CPUECTLR_EL1 113 ret 114endfunc cortex_a55_cpu_reg_dump 115 116declare_cpu_ops cortex_a55, CORTEX_A55_MIDR, \ 117 cortex_a55_reset_func, \ 118 cortex_a55_core_pwr_dwn 119