1/* 2 * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <cortex_a75.h> 10#include <cpuamu.h> 11#include <cpu_macros.S> 12 13 /* -------------------------------------------------- 14 * Errata Workaround for Cortex A75 Errata #764081. 15 * This applies only to revision r0p0 of Cortex A75. 16 * Inputs: 17 * x0: variant[4:7] and revision[0:3] of current cpu. 18 * Shall clobber: x0-x17 19 * -------------------------------------------------- 20 */ 21func errata_a75_764081_wa 22 /* 23 * Compare x0 against revision r0p0 24 */ 25 mov x17, x30 26 bl check_errata_764081 27 cbz x0, 1f 28 mrs x1, sctlr_el3 29 orr x1, x1 ,#SCTLR_IESB_BIT 30 msr sctlr_el3, x1 31 isb 321: 33 ret x17 34endfunc errata_a75_764081_wa 35 36func check_errata_764081 37 mov x1, #0x00 38 b cpu_rev_var_ls 39endfunc check_errata_764081 40 41 /* ------------------------------------------------- 42 * The CPU Ops reset function for Cortex-A75. 43 * ------------------------------------------------- 44 */ 45func cortex_a75_reset_func 46 mov x19, x30 47 bl cpu_get_rev_var 48 49#if ERRATA_A75_764081 50 bl errata_a75_764081_wa 51#endif 52 53#if IMAGE_BL31 && WORKAROUND_CVE_2017_5715 54 cpu_check_csv2 x0, 1f 55 adr x0, wa_cve_2017_5715_bpiall_vbar 56 msr vbar_el3, x0 57 isb 581: 59#endif 60 61#if WORKAROUND_CVE_2018_3639 62 mrs x0, CORTEX_A75_CPUACTLR_EL1 63 orr x0, x0, #CORTEX_A75_CPUACTLR_EL1_DISABLE_LOAD_PASS_STORE 64 msr CORTEX_A75_CPUACTLR_EL1, x0 65 isb 66#endif 67 68#if ERRATA_DSU_936184 69 bl errata_dsu_936184_wa 70#endif 71 72#if ENABLE_AMU 73 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 74 mrs x0, actlr_el3 75 orr x0, x0, #CORTEX_A75_ACTLR_AMEN_BIT 76 msr actlr_el3, x0 77 isb 78 79 /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ 80 mrs x0, actlr_el2 81 orr x0, x0, #CORTEX_A75_ACTLR_AMEN_BIT 82 msr actlr_el2, x0 83 isb 84 85 /* Enable group0 counters */ 86 mov x0, #CORTEX_A75_AMU_GROUP0_MASK 87 msr CPUAMCNTENSET_EL0, x0 88 isb 89 90 /* Enable group1 counters */ 91 mov x0, #CORTEX_A75_AMU_GROUP1_MASK 92 msr CPUAMCNTENSET_EL0, x0 93 isb 94#endif 95 ret x19 96endfunc cortex_a75_reset_func 97 98func check_errata_cve_2017_5715 99 cpu_check_csv2 x0, 1f 100#if WORKAROUND_CVE_2017_5715 101 mov x0, #ERRATA_APPLIES 102#else 103 mov x0, #ERRATA_MISSING 104#endif 105 ret 1061: 107 mov x0, #ERRATA_NOT_APPLIES 108 ret 109endfunc check_errata_cve_2017_5715 110 111func check_errata_cve_2018_3639 112#if WORKAROUND_CVE_2018_3639 113 mov x0, #ERRATA_APPLIES 114#else 115 mov x0, #ERRATA_MISSING 116#endif 117 ret 118endfunc check_errata_cve_2018_3639 119 120 /* --------------------------------------------- 121 * HW will do the cache maintenance while powering down 122 * --------------------------------------------- 123 */ 124func cortex_a75_core_pwr_dwn 125 /* --------------------------------------------- 126 * Enable CPU power down bit in power control register 127 * --------------------------------------------- 128 */ 129 mrs x0, CORTEX_A75_CPUPWRCTLR_EL1 130 orr x0, x0, #CORTEX_A75_CORE_PWRDN_EN_MASK 131 msr CORTEX_A75_CPUPWRCTLR_EL1, x0 132 isb 133 ret 134endfunc cortex_a75_core_pwr_dwn 135 136#if REPORT_ERRATA 137/* 138 * Errata printing function for Cortex A75. Must follow AAPCS. 139 */ 140func cortex_a75_errata_report 141 stp x8, x30, [sp, #-16]! 142 143 bl cpu_get_rev_var 144 mov x8, x0 145 146 /* 147 * Report all errata. The revision-variant information is passed to 148 * checking functions of each errata. 149 */ 150 report_errata ERRATA_A75_764081, cortex_a75, 764081 151 report_errata WORKAROUND_CVE_2017_5715, cortex_a75, cve_2017_5715 152 report_errata WORKAROUND_CVE_2018_3639, cortex_a75, cve_2018_3639 153 report_errata ERRATA_DSU_936184, cortex_a75, dsu_936184 154 155 ldp x8, x30, [sp], #16 156 ret 157endfunc cortex_a75_errata_report 158#endif 159 160 /* --------------------------------------------- 161 * This function provides cortex_a75 specific 162 * register information for crash reporting. 163 * It needs to return with x6 pointing to 164 * a list of register names in ascii and 165 * x8 - x15 having values of registers to be 166 * reported. 167 * --------------------------------------------- 168 */ 169.section .rodata.cortex_a75_regs, "aS" 170cortex_a75_regs: /* The ascii list of register names to be reported */ 171 .asciz "cpuectlr_el1", "" 172 173func cortex_a75_cpu_reg_dump 174 adr x6, cortex_a75_regs 175 mrs x8, CORTEX_A75_CPUECTLR_EL1 176 ret 177endfunc cortex_a75_cpu_reg_dump 178 179declare_cpu_ops_wa cortex_a75, CORTEX_A75_MIDR, \ 180 cortex_a75_reset_func, \ 181 check_errata_cve_2017_5715, \ 182 CPU_NO_EXTRA2_FUNC, \ 183 cortex_a75_core_pwr_dwn 184